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/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dpac.h130 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
131 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */
132 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */
133 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */
134 __I uint32_t H2LBRIDGES_:1; /*!< bit: 4 H2LBRIDGES */
135 __I uint32_t :11; /*!< bit: 5..15 Reserved */
136 __I uint32_t HPB0_:1; /*!< bit: 16 HPB0 */
137 __I uint32_t HPB2_:1; /*!< bit: 17 HPB2 */
138 __I uint32_t HPB3_:1; /*!< bit: 18 HPB3 */
139 __I uint32_t HPB4_:1; /*!< bit: 19 HPB4 */
[all …]
Dmtb.h350 __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
358 __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
359 …__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication …
360 …__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architec…
362 …__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configur…
363 __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
364 …__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) Peripheral Identifi…
365 …__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) Peripheral Identifi…
366 …__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) Peripheral Identifi…
367 …__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) Peripheral Identifi…
[all …]
Devsys.h363 __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
364 __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
365 __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
366 __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
367 __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
368 __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
369 __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
370 __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
371 __I uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun */
372 __I uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun */
[all …]
Drtc.h759 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
760 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
761 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
762 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
763 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
764 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
765 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
766 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
767 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
768 __I uint16_t :6; /*!< bit: 9..14 Reserved */
[all …]
Dusb.h605 __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
606 __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
607 __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
608 __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
609 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
610 __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
611 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
612 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
613 __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
614 __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
[all …]
Ddsu.h581 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
587 …__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identificat…
591 …__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Tabl…
592 …__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Tabl…
594 …__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Tabl…
595 …__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identif…
596 …__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identif…
597 …__I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identif…
598 …__I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identif…
599 …__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identif…
[all …]
Doscctrl.h147 __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
148 __I uint32_t :3; /*!< bit: 1.. 3 Reserved */
149 __I uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */
150 __I uint32_t :3; /*!< bit: 5.. 7 Reserved */
151 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
152 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
153 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
154 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
155 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
156 __I uint32_t :3; /*!< bit: 13..15 Reserved */
[all …]
Ddac.h220 __I uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */
221 __I uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */
222 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
223 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
224 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
227 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */
228 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
229 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
445 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
446 …__I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy…
Dsercom.h780 __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
781 __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
782 __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
783 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
804 __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
805 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
806 __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
807 __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
808 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
831 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
[all …]
Dac.h229 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
230 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
231 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
232 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
233 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
236 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
237 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
238 __I uint8_t WIN:1; /*!< bit: 4 Window x */
239 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
570 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
[all …]
Dsupc.h131 __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
132 __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
133 __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
134 __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
135 __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
136 __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
137 __I uint32_t :2; /*!< bit: 6.. 7 Reserved */
138 __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
139 __I uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */
140 __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
[all …]
Dtc.h355 __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
356 __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
357 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
358 __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
359 __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
360 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
363 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
364 __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
365 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
759 …__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Stat…
[all …]
Dtrng.h122 __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
123 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
165 __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
Dosc32kctrl.h87 __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
88 __I uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */
89 __I uint32_t :30; /*!< bit: 2..31 Reserved */
273 …__I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Sta…
Dtcc.h958 __I uint32_t OVF:1; /*!< bit: 0 Overflow */
959 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
960 __I uint32_t CNT:1; /*!< bit: 2 Counter */
961 __I uint32_t ERR:1; /*!< bit: 3 Error */
962 __I uint32_t :6; /*!< bit: 4.. 9 Reserved */
963 __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
964 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
965 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
966 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
967 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
[all …]
Dadc.h222 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
223 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
224 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
225 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
702 __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */
716 …__I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy…
718 __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */
Daes.h167 __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
168 __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
169 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
Ddmac.h867 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
868 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
869 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
870 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
1078 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
1079 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
1080 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
1081 …__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and L…
1093 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm3.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
350 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
364 …__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
365 …__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
366 …__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
367 …__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
368 …__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
576 …__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
615 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_sc300.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
350 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
364 …__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
365 …__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
366 …__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
367 …__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
368 …__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
571 …__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
595 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_cm4.h244 #define __I volatile /*!< Defines 'read only' permissions */ macro
246 #define __I volatile const /*!< Defines 'read only' permissions */
397 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
411 …__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
412 …__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
413 …__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
414 …__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
415 …__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
615 …__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…
655 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
[all …]
Dcore_cm7.h259 #define __I volatile /*!< Defines 'read only' permissions */ macro
261 #define __I volatile const /*!< Defines 'read only' permissions */
412 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
426 …__I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register …
427 …__I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register …
428 …__I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register …
429 …__I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register …
430 …__I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…
432 …__I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register …
433 …__I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register …
[all …]
Dcore_cm0plus.h203 #define __I volatile /*!< Defines 'read only' permissions */ macro
205 #define __I volatile const /*!< Defines 'read only' permissions */
347 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
465 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
512 …__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register …
Dcore_sc000.h198 #define __I volatile /*!< Defines 'read only' permissions */ macro
200 #define __I volatile const /*!< Defines 'read only' permissions */
342 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
484 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …
531 …__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register …
Dcore_cm0.h193 #define __I volatile /*!< Defines 'read only' permissions */ macro
195 #define __I volatile const /*!< Defines 'read only' permissions */
336 …__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register …
444 …__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register …

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