1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_ADC_H 38 #define __STM32L0xx_HAL_ADC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup ADC 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup ADC_Exported_Types ADC Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief ADC group regular oversampling structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Ratio; /*!< Configures the oversampling ratio. 66 This parameter can be a value of @ref ADC_Oversampling_Ratio */ 67 68 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 69 This parameter can be a value of @ref ADC_Right_Bit_Shift */ 70 71 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 72 This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */ 73 }ADC_OversamplingTypeDef; 74 75 /** 76 * @brief Structure definition of ADC instance and ADC group regular. 77 * @note Parameters of this structure are shared within 2 scopes: 78 * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 79 * ScanConvMode, EOCSelection, LowPowerAutoWait. 80 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 81 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 82 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 83 * ADC state can be either: 84 * - For all parameters: ADC disabled 85 * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. 86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 87 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 88 * (which fulfills the ADC state condition) on the fly). 89 */ 90 typedef struct 91 { 92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler. 93 This parameter can be a value of @ref ADC_ClockPrescaler. 94 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 95 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 96 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 97 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. 98 Note: This parameter can be modified only if the ADC is disabled. */ 99 100 uint32_t Resolution; /*!< Configure the ADC resolution. 101 This parameter can be a value of @ref ADC_Resolution */ 102 103 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 104 Refer to reference manual for alignments formats versus resolutions. 105 This parameter can be a value of @ref ADC_Data_align */ 106 107 uint32_t ScanConvMode; /*!< Configure the sequencer of regular group. 108 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 109 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): 110 If only 1 channel is set: Conversion is performed in single mode. 111 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 112 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). 113 This parameter can be a value of @ref ADC_Scan_mode */ 114 115 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 116 This parameter can be a value of @ref ADC_EOCSelection. */ 117 118 uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 119 conversion (for ADC group regular) has been retrieved by user software, 120 using function HAL_ADC_GetValue(). 121 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 122 for low frequency applications. 123 This parameter can be set to ENABLE or DISABLE. 124 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag 125 to free the IRQ vector sequencer. 126 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 127 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ 128 129 uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 130 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 131 This parameter can be set to ENABLE or DISABLE. 132 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 133 134 uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 135 after the first ADC conversion start trigger occurred (software start or external trigger). 136 This parameter can be set to ENABLE or DISABLE. */ 137 138 uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 139 (main sequence subdivided in successive parts). 140 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 141 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 142 This parameter can be set to ENABLE or DISABLE. 143 Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ 144 145 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 146 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 147 This parameter can be a value of @ref ADC_regular_external_trigger_source. 148 Caution: external trigger source is common to all ADC instances. */ 149 150 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 151 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 152 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 153 154 uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 155 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 156 This parameter can be set to ENABLE or DISABLE. 157 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 158 159 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 160 This parameter can be a value of @ref ADC_Overrun. 161 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 162 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 163 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 164 Note: Error reporting with respect to the conversion mode: 165 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 166 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 167 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 168 169 uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz, 170 it is mandatory to first enable the Low Frequency Mode. 171 This parameter can be set to ENABLE or DISABLE. 172 Note: This parameter can be modified only if there is no conversion is ongoing. */ 173 174 175 uint32_t SamplingTime; /*!< The sample time common to all channels. 176 Unit: ADC clock cycles 177 This parameter can be a value of @ref ADC_sampling_times 178 Note: This parameter can be modified only if there is no conversion ongoing. */ 179 180 uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 181 This parameter can be set to ENABLE or DISABLE. 182 Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ 183 184 185 ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters 186 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 187 }ADC_InitTypeDef; 188 189 /** 190 * @brief Structure definition of ADC channel for regular group 191 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 192 * ADC state can be either: 193 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 194 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 195 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 196 */ 197 typedef struct 198 { 199 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 200 This parameter can be a value of @ref ADC_channels 201 Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 202 203 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. 204 On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number 205 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 206 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. 207 This parameter can be a value of @ref ADC_rank */ 208 }ADC_ChannelConfTypeDef; 209 210 /** 211 * @brief Structure definition of ADC analog watchdog 212 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 213 * ADC state can be either: 214 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular 215 * - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going) 216 */ 217 typedef struct 218 { 219 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels. 220 This parameter can be a value of @ref ADC_analog_watchdog_mode */ 221 222 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 223 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 224 This parameter can be a value of @ref ADC_channels */ 225 226 uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 227 This parameter can be set to ENABLE or DISABLE */ 228 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 229 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 230 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 231 232 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 233 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 234 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 235 }ADC_AnalogWDGConfTypeDef; 236 237 /** 238 * @brief HAL ADC state machine: ADC states definition (bitfields) 239 * @note ADC state machine is managed by bitfields, state must be compared 240 * with bit by bit. 241 * For example: 242 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 243 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 244 */ 245 /* States of ADC global scope */ 246 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ 247 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ 248 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */ 249 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ 250 251 /* States of ADC errors */ 252 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ 253 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ 254 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ 255 256 /* States of ADC group regular */ 257 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 258 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 259 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ 260 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ 261 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ 262 263 /* States of ADC group injected */ 264 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode, 265 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 266 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on this STM32 serie: Conversion data available on group injected */ 267 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on this STM32 serie: Injected queue overflow occurrence */ 268 269 /* States of ADC analog watchdogs */ 270 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 271 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */ 272 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */ 273 274 /* States of ADC multi-mode */ 275 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */ 276 277 278 279 /** 280 * @brief ADC handle Structure definition 281 */ 282 typedef struct 283 { 284 ADC_TypeDef *Instance; /*!< Register base address */ 285 286 ADC_InitTypeDef Init; /*!< ADC required parameters */ 287 288 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 289 290 HAL_LockTypeDef Lock; /*!< ADC locking object */ 291 292 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 293 294 __IO uint32_t ErrorCode; /*!< ADC Error code */ 295 }ADC_HandleTypeDef; 296 /** 297 * @} 298 */ 299 300 301 /* Exported constants --------------------------------------------------------*/ 302 303 /** @defgroup ADC_Exported_Constants ADC Exported Constants 304 * @{ 305 */ 306 307 /** @defgroup ADC_Error_Code ADC Error Code 308 * @{ 309 */ 310 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ 311 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking, 312 enable/disable, erroneous state, ...) */ 313 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ 314 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup ADC_TimeOut_Values ADC TimeOut Values 320 * @{ 321 */ 322 323 /* Fixed timeout values for ADC calibration, enable settling time, disable */ 324 /* settling time. */ 325 /* Values defined to be higher than worst cases: low clocks freq, */ 326 /* maximum prescalers. */ 327 /* Unit: ms */ 328 #define ADC_ENABLE_TIMEOUT 10U 329 #define ADC_DISABLE_TIMEOUT 10U 330 #define ADC_STOP_CONVERSION_TIMEOUT 10U 331 332 /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */ 333 /* the minimum number of CPU cycles to fulfill this delay */ 334 #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U 335 /** 336 * @} 337 */ 338 339 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 340 * @{ 341 */ 342 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */ 343 #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 344 #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 345 #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 346 #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */ 347 #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 348 #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 349 #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 350 #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */ 351 #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 352 #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ 353 #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ 354 355 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1 356 This configuration must be enabled only if PCLK has a 50% 357 duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock 358 must by 50% duty cycle)*/ 359 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */ 360 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */ 361 362 /** 363 * @} 364 */ 365 366 /** @defgroup ADC_Resolution ADC Resolution 367 * @{ 368 */ 369 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */ 370 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ 371 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ 372 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup ADC_Data_align ADC conversion data alignment 378 * @{ 379 */ 380 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) 381 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) 382 /** 383 * @} 384 */ 385 386 /** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group 387 * @{ 388 */ 389 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) 390 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) 391 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) 392 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) 393 /** 394 * @} 395 */ 396 397 /** @defgroup ADC_EOCSelection ADC EOC Selection 398 * @{ 399 */ 400 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) 401 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) 402 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ 403 /** 404 * @} 405 */ 406 407 /** @defgroup ADC_Overrun ADC Overrun 408 * @{ 409 */ 410 #define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U) 411 #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) 412 /** 413 * @} 414 */ 415 416 417 /** @defgroup ADC_rank ADC rank 418 * @{ 419 */ 420 #define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 421 #define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ 422 /** 423 * @} 424 */ 425 426 427 /** @defgroup ADC_channels ADC_Channels 428 * @{ 429 */ 430 #define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0)) 431 #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0) 432 #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1) 433 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) 434 #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2) 435 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) 436 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) 437 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) 438 #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3) 439 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0) 440 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1) 441 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) 442 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2) 443 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) 444 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) 445 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) 446 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) 447 #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4) 448 #endif 449 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0) 450 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1) 451 452 /* Internal channels */ 453 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) 454 #define ADC_CHANNEL_VLCD ADC_CHANNEL_16 455 #endif 456 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 457 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18 458 /** 459 * @} 460 */ 461 462 /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks 463 * @{ 464 */ 465 #define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU) 466 #define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U) 467 /** 468 * @} 469 */ 470 471 /** @defgroup ADC_sampling_times ADC Sampling Cycles 472 * @{ 473 */ 474 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */ 475 #define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */ 476 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */ 477 #define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */ 478 #define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */ 479 #define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */ 480 #define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */ 481 #define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup ADC_Scan_mode ADC Scan mode 487 * @{ 488 */ 489 /* Note: Scan mode values must be compatible with other STM32 devices having */ 490 /* a configurable sequencer. */ 491 /* Scan direction setting values are defined by taking in account */ 492 /* already defined values for other STM32 devices: */ 493 /* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */ 494 /* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */ 495 /* Scan direction forward is considered as default setting equivalent */ 496 /* to scan enable. */ 497 /* Scan direction backward is considered as additional setting. */ 498 /* In case of migration from another STM32 device, the user will be */ 499 /* warned of change of setting choices with assert check. */ 500 #define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ 501 #define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ 502 503 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio 509 * @{ 510 */ 511 512 #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC Oversampling ratio 2x */ 513 #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /*!< ADC Oversampling ratio 4x */ 514 #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /*!< ADC Oversampling ratio 8x */ 515 #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /*!< ADC Oversampling ratio 16x */ 516 #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /*!< ADC Oversampling ratio 32x */ 517 #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /*!< ADC Oversampling ratio 64x */ 518 #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /*!< ADC Oversampling ratio 128x */ 519 #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /*!< ADC Oversampling ratio 256x */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift 525 * @{ 526 */ 527 #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ 528 #define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /*!< ADC 1 bit shift for oversampling */ 529 #define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /*!< ADC 2 bits shift for oversampling */ 530 #define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /*!< ADC 3 bits shift for oversampling */ 531 #define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /*!< ADC 4 bits shift for oversampling */ 532 #define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /*!< ADC 5 bits shift for oversampling */ 533 #define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /*!< ADC 6 bits shift for oversampling */ 534 #define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /*!< ADC 7 bits shift for oversampling */ 535 #define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /*!< ADC 8 bits shift for oversampling */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode 541 * @{ 542 */ 543 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ 544 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /*!< ADC No bit shift for oversampling */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 550 * @{ 551 */ 552 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U) 553 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) 554 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) 555 /** 556 * @} 557 */ 558 559 /** @defgroup ADC_conversion_type ADC Conversion Group 560 * @{ 561 */ 562 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) 563 /** 564 * @} 565 */ 566 567 /** @defgroup ADC_Event_type ADC Event 568 * @{ 569 */ 570 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 571 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 572 /** 573 * @} 574 */ 575 576 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 577 * @{ 578 */ 579 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */ 580 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ 581 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 582 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ 583 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 584 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */ 585 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup ADC_flags_definition ADC flags definition 591 * @{ 592 */ 593 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 594 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 595 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 596 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ 597 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 598 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ 599 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */ 600 601 602 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 603 ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL) 604 /** 605 * @} 606 */ 607 608 /** 609 * @} 610 */ 611 612 613 /* Exported macro ------------------------------------------------------------*/ 614 615 /** @defgroup ADC_Exported_Macros ADC Exported Macros 616 * @{ 617 */ 618 /** @brief Reset ADC handle state 619 * @param __HANDLE__: ADC handle 620 * @retval None 621 */ 622 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 623 624 /** 625 * @brief Enable the ADC peripheral 626 * @param __HANDLE__: ADC handle 627 * @retval None 628 */ 629 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 630 631 /** 632 * @brief Verification of hardware constraints before ADC can be enabled 633 * @param __HANDLE__: ADC handle 634 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 635 */ 636 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 637 (( ( ((__HANDLE__)->Instance->CR) & \ 638 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \ 639 ADC_CR_ADDIS | ADC_CR_ADEN ) \ 640 ) == RESET \ 641 ) ? SET : RESET) 642 643 /** 644 * @brief Disable the ADC peripheral 645 * @param __HANDLE__: ADC handle 646 * @retval None 647 */ 648 #define __HAL_ADC_DISABLE(__HANDLE__) \ 649 do{ \ 650 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 651 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 652 } while(0) 653 654 /** 655 * @brief Verification of hardware constraints before ADC can be disabled 656 * @param __HANDLE__: ADC handle 657 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 658 */ 659 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 660 (( ( ((__HANDLE__)->Instance->CR) & \ 661 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 662 ) ? SET : RESET) 663 664 /** 665 * @brief Verification of ADC state: enabled or disabled 666 * @param __HANDLE__: ADC handle 667 * @retval SET (ADC enabled) or RESET (ADC disabled) 668 */ 669 #define ADC_IS_ENABLE(__HANDLE__) \ 670 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 671 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 672 ) ? SET : RESET) 673 674 /** 675 * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution. 676 * @param __HANDLE__: ADC handle 677 * @retval None 678 */ 679 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) 680 /** 681 * @brief Test if conversion trigger of regular group is software start 682 * or external trigger. 683 * @param __HANDLE__: ADC handle 684 * @retval SET (software start) or RESET (external trigger) 685 */ 686 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 687 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) 688 689 690 691 /** 692 * @brief Check if no conversion on going on regular group 693 * @param __HANDLE__: ADC handle 694 * @retval SET (conversion is on going) or RESET (no conversion is on going) 695 */ 696 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 697 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 698 ) ? RESET : SET) 699 700 /** 701 * @brief Enable ADC continuous conversion mode. 702 * @param _CONTINUOUS_MODE_: Continuous mode. 703 * @retval None 704 */ 705 #define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) 706 707 /** 708 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 709 * @param _SCAN_MODE_: Scan conversion mode. 710 * @retval None 711 */ 712 #define ADC_SCANDIR(_SCAN_MODE_) \ 713 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ 714 )? (ADC_CFGR1_SCANDIR) : (0x00000000U) \ 715 ) 716 717 /** 718 * @brief Configures the number of discontinuous conversions for the regular group channels. 719 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 720 * @retval None 721 */ 722 #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) 723 724 /** 725 * @brief Enable the ADC DMA continuous request. 726 * @param _DMAContReq_MODE_: DMA continuous request mode. 727 * @retval None 728 */ 729 #define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U) 730 731 /** 732 * @brief Enable the ADC Auto Delay. 733 * @param _AutoDelay_: Auto delay bit enable or disable. 734 * @retval None 735 */ 736 #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U) 737 738 /** 739 * @brief Enable the ADC LowPowerAutoPowerOff. 740 * @param _AUTOFF_: AutoOff bit enable or disable. 741 * @retval None 742 */ 743 #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U) 744 745 /** 746 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 747 * @param _Threshold_: Threshold value 748 * @retval None 749 */ 750 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) 751 752 /** 753 * @brief Enable the ADC Low Frequency mode. 754 * @param _LOW_FREQUENCY_MODE_: Low Frequency mode. 755 * @retval None 756 */ 757 #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U) 758 759 /** 760 * @brief Shift the offset in function of the selected ADC resolution. 761 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 762 * If resolution 12 bits, no shift. 763 * If resolution 10 bits, shift of 2 ranks on the right. 764 * If resolution 8 bits, shift of 4 ranks on the right. 765 * If resolution 6 bits, shift of 6 ranks on the right. 766 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 767 * @param __HANDLE__: ADC handle. 768 * @param _Offset_: Value to be shifted 769 * @retval None 770 */ 771 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ 772 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U)) 773 774 /** 775 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 776 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0 777 * If resolution 12 bits, no shift. 778 * If resolution 10 bits, shift of 2 ranks on the right. 779 * If resolution 8 bits, shift of 4 ranks on the right. 780 * If resolution 6 bits, shift of 6 ranks on the right. 781 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 782 * @param __HANDLE__: ADC handle. 783 * @param _Threshold_: Value to be shifted 784 * @retval None 785 */ 786 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 787 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) 788 789 /** 790 * @brief Shift the value on the left, less significant are set to 0. 791 * @param _Value_: Value to be shifted 792 * @param _Shift_: Number of shift to be done 793 * @retval None 794 */ 795 #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_)) 796 797 798 /** 799 * @brief Enable the ADC end of conversion interrupt. 800 * @param __HANDLE__: ADC handle. 801 * @param __INTERRUPT__: ADC Interrupt. 802 * @retval None 803 */ 804 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 805 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 806 807 /** 808 * @brief Disable the ADC end of conversion interrupt. 809 * @param __HANDLE__: ADC handle. 810 * @param __INTERRUPT__: ADC interrupt. 811 * @retval None 812 */ 813 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 814 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 815 816 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 817 * @param __HANDLE__: ADC handle 818 * @param __INTERRUPT__: ADC interrupt source to check 819 * @arg ... 820 * @arg ... 821 * @retval State of interruption (TRUE or FALSE) 822 */ 823 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 824 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 825 826 /** 827 * @brief Clear the ADC's pending flags 828 * @param __HANDLE__: ADC handle. 829 * @param __FLAG__: ADC flag. 830 * @retval None 831 */ 832 /* Note: bit cleared bit by writing 1 */ 833 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 834 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 835 836 /** 837 * @brief Get the selected ADC's flag status. 838 * @param __HANDLE__: ADC handle. 839 * @param __FLAG__: ADC flag. 840 * @retval None 841 */ 842 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 843 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 844 845 846 /** 847 * @brief Simultaneously clears and sets specific bits of the handle State 848 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 849 * the first parameter is the ADC handle State, the second parameter is the 850 * bit field to clear, the third and last parameter is the bit field to set. 851 * @retval None 852 */ 853 #define ADC_STATE_CLR_SET MODIFY_REG 854 855 /** 856 * @brief Clear ADC error code (set it to error code: "no error") 857 * @param __HANDLE__: ADC handle 858 * @retval None 859 */ 860 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 861 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 862 863 864 /** 865 * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler 866 * @param __HANDLE__: ADC handle 867 * @retval None 868 */ 869 870 #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \ 871 do{ \ 872 if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 873 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 874 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \ 875 { \ 876 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ 877 (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \ 878 } \ 879 else \ 880 { \ 881 /* CKMOD bits must be reset */ \ 882 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ 883 ADC->CCR &= ~(ADC_CCR_PRESC); \ 884 ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \ 885 } \ 886 } while(0) 887 888 889 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ 890 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ 891 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ 892 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ 893 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ 894 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ 895 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ 896 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ 897 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ 898 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ 899 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ 900 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ 901 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ 902 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ 903 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ 904 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) 905 906 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 907 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 908 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 909 ((RESOLUTION) == ADC_RESOLUTION_6B)) 910 911 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 912 ((RESOLUTION) == ADC_RESOLUTION_6B)) 913 914 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 915 ((ALIGN) == ADC_DATAALIGN_LEFT)) 916 917 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 918 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 919 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 920 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 921 922 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 923 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ 924 ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV)) 925 926 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 927 ((OVR) == ADC_OVR_DATA_OVERWRITTEN)) 928 929 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ 930 ((WATCHDOG) == ADC_RANK_NONE)) 931 932 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) 933 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 934 ((CHANNEL) == ADC_CHANNEL_1) || \ 935 ((CHANNEL) == ADC_CHANNEL_2) || \ 936 ((CHANNEL) == ADC_CHANNEL_3) || \ 937 ((CHANNEL) == ADC_CHANNEL_4) || \ 938 ((CHANNEL) == ADC_CHANNEL_5) || \ 939 ((CHANNEL) == ADC_CHANNEL_6) || \ 940 ((CHANNEL) == ADC_CHANNEL_7) || \ 941 ((CHANNEL) == ADC_CHANNEL_8) || \ 942 ((CHANNEL) == ADC_CHANNEL_9) || \ 943 ((CHANNEL) == ADC_CHANNEL_10) || \ 944 ((CHANNEL) == ADC_CHANNEL_11) || \ 945 ((CHANNEL) == ADC_CHANNEL_12) || \ 946 ((CHANNEL) == ADC_CHANNEL_13) || \ 947 ((CHANNEL) == ADC_CHANNEL_14) || \ 948 ((CHANNEL) == ADC_CHANNEL_15) || \ 949 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 950 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 951 ((CHANNEL) == ADC_CHANNEL_VLCD)) 952 #else 953 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 954 ((CHANNEL) == ADC_CHANNEL_1) || \ 955 ((CHANNEL) == ADC_CHANNEL_2) || \ 956 ((CHANNEL) == ADC_CHANNEL_3) || \ 957 ((CHANNEL) == ADC_CHANNEL_4) || \ 958 ((CHANNEL) == ADC_CHANNEL_5) || \ 959 ((CHANNEL) == ADC_CHANNEL_6) || \ 960 ((CHANNEL) == ADC_CHANNEL_7) || \ 961 ((CHANNEL) == ADC_CHANNEL_8) || \ 962 ((CHANNEL) == ADC_CHANNEL_9) || \ 963 ((CHANNEL) == ADC_CHANNEL_10) || \ 964 ((CHANNEL) == ADC_CHANNEL_11) || \ 965 ((CHANNEL) == ADC_CHANNEL_12) || \ 966 ((CHANNEL) == ADC_CHANNEL_13) || \ 967 ((CHANNEL) == ADC_CHANNEL_14) || \ 968 ((CHANNEL) == ADC_CHANNEL_15) || \ 969 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 970 ((CHANNEL) == ADC_CHANNEL_VREFINT)) 971 #endif 972 973 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \ 974 ((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \ 975 ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \ 976 ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \ 977 ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \ 978 ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \ 979 ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \ 980 ((TIME) == ADC_SAMPLETIME_160CYCLES_5)) 981 982 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ 983 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)) 984 985 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \ 986 ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \ 987 ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \ 988 ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \ 989 ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \ 990 ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \ 991 ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \ 992 ((RATIO) == ADC_OVERSAMPLING_RATIO_256 )) 993 994 #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \ 995 ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \ 996 ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \ 997 ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \ 998 ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \ 999 ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \ 1000 ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \ 1001 ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \ 1002 ((SHIFT) == ADC_RIGHTBITSHIFT_8 )) 1003 1004 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1005 ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1006 1007 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \ 1008 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1009 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG )) 1010 1011 #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP) 1012 1013 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 1014 ((EVENT) == ADC_OVR_EVENT)) 1015 1016 1017 /** @defgroup ADC_range_verification ADC Range Verification 1018 * in function of ADC resolution selected (12, 10, 8 or 6 bits) 1019 * @{ 1020 */ 1021 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 1022 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \ 1023 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \ 1024 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \ 1025 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU)))) 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification 1031 * @{ 1032 */ 1033 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U))) 1034 /** 1035 * @} 1036 */ 1037 1038 /** 1039 * @} 1040 */ 1041 1042 /* Include ADC HAL Extended module */ 1043 #include "stm32l0xx_hal_adc_ex.h" 1044 1045 /* Exported functions --------------------------------------------------------*/ 1046 /** @addtogroup ADC_Exported_Functions 1047 * @{ 1048 */ 1049 1050 /** @addtogroup ADC_Exported_Functions_Group1 1051 * @brief Initialization and Configuration functions 1052 * @{ 1053 */ 1054 /* Initialization and de-initialization functions ****************************/ 1055 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 1056 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1057 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 1058 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 1059 /** 1060 * @} 1061 */ 1062 1063 /** @addtogroup ADC_Exported_Functions_Group2 1064 * @brief IO operation functions 1065 * @{ 1066 */ 1067 /* IO operation functions *****************************************************/ 1068 1069 /* Blocking mode: Polling */ 1070 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 1071 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 1072 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1073 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 1074 1075 /* Non-blocking mode: Interruption */ 1076 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 1077 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 1078 1079 /* Non-blocking mode: DMA */ 1080 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 1081 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 1082 1083 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1084 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 1085 1086 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1087 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 1088 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 1089 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 1090 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 1091 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1092 /** 1093 * @} 1094 */ 1095 1096 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1097 * @brief Peripheral Control functions 1098 * @{ 1099 */ 1100 /* Peripheral Control functions ***********************************************/ 1101 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 1102 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 1103 /** 1104 * @} 1105 */ 1106 1107 /* Peripheral State functions *************************************************/ 1108 /** @addtogroup ADC_Exported_Functions_Group4 1109 * @{ 1110 */ 1111 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 1112 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1113 /** 1114 * @} 1115 */ 1116 1117 1118 /** 1119 * @} 1120 */ 1121 1122 /** 1123 * @} 1124 */ 1125 1126 /** 1127 * @} 1128 */ 1129 1130 #ifdef __cplusplus 1131 } 1132 #endif 1133 1134 1135 #endif /*__STM32L0xx_HAL_ADC_H */ 1136 1137 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1138
