Searched refs:Tc (Results 1 – 13 of 13) sorted by relevance
86 while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { in hri_tc_wait_for_sync()92 return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; in hri_tc_is_syncing()98 ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_set_COUNT_COUNT_bf()105 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_get_COUNT_COUNT_bf()114 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_write_COUNT_COUNT_bf()117 ((Tc *)hw)->COUNT16.COUNT.reg = tmp; in hri_tccount16_write_COUNT_COUNT_bf()124 ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_clear_COUNT_COUNT_bf()131 ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_toggle_COUNT_COUNT_bf()138 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_read_COUNT_COUNT_bf()146 ((Tc *)hw)->COUNT16.COUNT.reg |= mask; in hri_tccount16_set_COUNT_reg()[all …]
561 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */563 #define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */564 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */
551 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */
823 } Tc; typedef
