1 /** 2 * \file 3 * 4 * \brief Instance description for TC4 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TC4_INSTANCE_ 30 #define _SAML21_TC4_INSTANCE_ 31 32 /* ========== Register definition for TC4 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TC4_CTRLA (0x43000800) /**< \brief (TC4) Control A */ 35 #define REG_TC4_CTRLBCLR (0x43000804) /**< \brief (TC4) Control B Clear */ 36 #define REG_TC4_CTRLBSET (0x43000805) /**< \brief (TC4) Control B Set */ 37 #define REG_TC4_EVCTRL (0x43000806) /**< \brief (TC4) Event Control */ 38 #define REG_TC4_INTENCLR (0x43000808) /**< \brief (TC4) Interrupt Enable Clear */ 39 #define REG_TC4_INTENSET (0x43000809) /**< \brief (TC4) Interrupt Enable Set */ 40 #define REG_TC4_INTFLAG (0x4300080A) /**< \brief (TC4) Interrupt Flag Status and Clear */ 41 #define REG_TC4_STATUS (0x4300080B) /**< \brief (TC4) Status */ 42 #define REG_TC4_WAVE (0x4300080C) /**< \brief (TC4) Waveform Generation Control */ 43 #define REG_TC4_DRVCTRL (0x4300080D) /**< \brief (TC4) Control C */ 44 #define REG_TC4_DBGCTRL (0x4300080F) /**< \brief (TC4) Debug Control */ 45 #define REG_TC4_SYNCBUSY (0x43000810) /**< \brief (TC4) Synchronization Status */ 46 #define REG_TC4_COUNT16_COUNT (0x43000814) /**< \brief (TC4) COUNT16 Count */ 47 #define REG_TC4_COUNT16_CC0 (0x4300081C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ 48 #define REG_TC4_COUNT16_CC1 (0x4300081E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ 49 #define REG_TC4_COUNT16_CCBUF0 (0x43000830) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ 50 #define REG_TC4_COUNT16_CCBUF1 (0x43000832) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ 51 #define REG_TC4_COUNT32_COUNT (0x43000814) /**< \brief (TC4) COUNT32 Count */ 52 #define REG_TC4_COUNT32_CC0 (0x4300081C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ 53 #define REG_TC4_COUNT32_CC1 (0x43000820) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ 54 #define REG_TC4_COUNT32_CCBUF0 (0x43000830) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ 55 #define REG_TC4_COUNT32_CCBUF1 (0x43000834) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ 56 #define REG_TC4_COUNT8_COUNT (0x43000814) /**< \brief (TC4) COUNT8 Count */ 57 #define REG_TC4_COUNT8_PER (0x4300081B) /**< \brief (TC4) COUNT8 Period */ 58 #define REG_TC4_COUNT8_CC0 (0x4300081C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ 59 #define REG_TC4_COUNT8_CC1 (0x4300081D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ 60 #define REG_TC4_COUNT8_PERBUF (0x4300082F) /**< \brief (TC4) COUNT8 Period Buffer */ 61 #define REG_TC4_COUNT8_CCBUF0 (0x43000830) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ 62 #define REG_TC4_COUNT8_CCBUF1 (0x43000831) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ 63 #else 64 #define REG_TC4_CTRLA (*(RwReg *)0x43000800UL) /**< \brief (TC4) Control A */ 65 #define REG_TC4_CTRLBCLR (*(RwReg8 *)0x43000804UL) /**< \brief (TC4) Control B Clear */ 66 #define REG_TC4_CTRLBSET (*(RwReg8 *)0x43000805UL) /**< \brief (TC4) Control B Set */ 67 #define REG_TC4_EVCTRL (*(RwReg16*)0x43000806UL) /**< \brief (TC4) Event Control */ 68 #define REG_TC4_INTENCLR (*(RwReg8 *)0x43000808UL) /**< \brief (TC4) Interrupt Enable Clear */ 69 #define REG_TC4_INTENSET (*(RwReg8 *)0x43000809UL) /**< \brief (TC4) Interrupt Enable Set */ 70 #define REG_TC4_INTFLAG (*(RwReg8 *)0x4300080AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */ 71 #define REG_TC4_STATUS (*(RwReg8 *)0x4300080BUL) /**< \brief (TC4) Status */ 72 #define REG_TC4_WAVE (*(RwReg8 *)0x4300080CUL) /**< \brief (TC4) Waveform Generation Control */ 73 #define REG_TC4_DRVCTRL (*(RwReg8 *)0x4300080DUL) /**< \brief (TC4) Control C */ 74 #define REG_TC4_DBGCTRL (*(RwReg8 *)0x4300080FUL) /**< \brief (TC4) Debug Control */ 75 #define REG_TC4_SYNCBUSY (*(RoReg *)0x43000810UL) /**< \brief (TC4) Synchronization Status */ 76 #define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x43000814UL) /**< \brief (TC4) COUNT16 Count */ 77 #define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4300081CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ 78 #define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4300081EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ 79 #define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x43000830UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ 80 #define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x43000832UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ 81 #define REG_TC4_COUNT32_COUNT (*(RwReg *)0x43000814UL) /**< \brief (TC4) COUNT32 Count */ 82 #define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4300081CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ 83 #define REG_TC4_COUNT32_CC1 (*(RwReg *)0x43000820UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ 84 #define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x43000830UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ 85 #define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x43000834UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ 86 #define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x43000814UL) /**< \brief (TC4) COUNT8 Count */ 87 #define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4300081BUL) /**< \brief (TC4) COUNT8 Period */ 88 #define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4300081CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ 89 #define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4300081DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ 90 #define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4300082FUL) /**< \brief (TC4) COUNT8 Period Buffer */ 91 #define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x43000830UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ 92 #define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x43000831UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ 93 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 /* ========== Instance parameters for TC4 peripheral ========== */ 96 #define TC4_CC_NUM 2 97 #define TC4_DMAC_ID_MC_0 35 98 #define TC4_DMAC_ID_MC_1 36 99 #define TC4_DMAC_ID_MC_LSB 35 100 #define TC4_DMAC_ID_MC_MSB 36 101 #define TC4_DMAC_ID_MC_SIZE 2 102 #define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger 103 #define TC4_EXT 0 104 #define TC4_GCLK_ID 29 105 #define TC4_MASTER 0 106 #define TC4_OW_NUM 2 107 108 #endif /* _SAML21_TC4_INSTANCE_ */ 109
