1 /** 2 * \file 3 * 4 * \brief Instance description for TC0 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TC0_INSTANCE_ 30 #define _SAML21_TC0_INSTANCE_ 31 32 /* ========== Register definition for TC0 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */ 35 #define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */ 36 #define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */ 37 #define REG_TC0_EVCTRL (0x42002006) /**< \brief (TC0) Event Control */ 38 #define REG_TC0_INTENCLR (0x42002008) /**< \brief (TC0) Interrupt Enable Clear */ 39 #define REG_TC0_INTENSET (0x42002009) /**< \brief (TC0) Interrupt Enable Set */ 40 #define REG_TC0_INTFLAG (0x4200200A) /**< \brief (TC0) Interrupt Flag Status and Clear */ 41 #define REG_TC0_STATUS (0x4200200B) /**< \brief (TC0) Status */ 42 #define REG_TC0_WAVE (0x4200200C) /**< \brief (TC0) Waveform Generation Control */ 43 #define REG_TC0_DRVCTRL (0x4200200D) /**< \brief (TC0) Control C */ 44 #define REG_TC0_DBGCTRL (0x4200200F) /**< \brief (TC0) Debug Control */ 45 #define REG_TC0_SYNCBUSY (0x42002010) /**< \brief (TC0) Synchronization Status */ 46 #define REG_TC0_COUNT16_COUNT (0x42002014) /**< \brief (TC0) COUNT16 Count */ 47 #define REG_TC0_COUNT16_CC0 (0x4200201C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 48 #define REG_TC0_COUNT16_CC1 (0x4200201E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 49 #define REG_TC0_COUNT16_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 50 #define REG_TC0_COUNT16_CCBUF1 (0x42002032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 51 #define REG_TC0_COUNT32_COUNT (0x42002014) /**< \brief (TC0) COUNT32 Count */ 52 #define REG_TC0_COUNT32_CC0 (0x4200201C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 53 #define REG_TC0_COUNT32_CC1 (0x42002020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 54 #define REG_TC0_COUNT32_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 55 #define REG_TC0_COUNT32_CCBUF1 (0x42002034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 56 #define REG_TC0_COUNT8_COUNT (0x42002014) /**< \brief (TC0) COUNT8 Count */ 57 #define REG_TC0_COUNT8_PER (0x4200201B) /**< \brief (TC0) COUNT8 Period */ 58 #define REG_TC0_COUNT8_CC0 (0x4200201C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 59 #define REG_TC0_COUNT8_CC1 (0x4200201D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 60 #define REG_TC0_COUNT8_PERBUF (0x4200202F) /**< \brief (TC0) COUNT8 Period Buffer */ 61 #define REG_TC0_COUNT8_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 62 #define REG_TC0_COUNT8_CCBUF1 (0x42002031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 63 #else 64 #define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */ 65 #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */ 66 #define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */ 67 #define REG_TC0_EVCTRL (*(RwReg16*)0x42002006UL) /**< \brief (TC0) Event Control */ 68 #define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Clear */ 69 #define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set */ 70 #define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ 71 #define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */ 72 #define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation Control */ 73 #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */ 74 #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */ 75 #define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Status */ 76 #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014UL) /**< \brief (TC0) COUNT16 Count */ 77 #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 78 #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 79 #define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 80 #define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 81 #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */ 82 #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 83 #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 84 #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 85 #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 86 #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */ 87 #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BUL) /**< \brief (TC0) COUNT8 Period */ 88 #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 89 #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 90 #define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FUL) /**< \brief (TC0) COUNT8 Period Buffer */ 91 #define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 92 #define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 93 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 /* ========== Instance parameters for TC0 peripheral ========== */ 96 #define TC0_CC_NUM 2 97 #define TC0_DMAC_ID_MC_0 23 98 #define TC0_DMAC_ID_MC_1 24 99 #define TC0_DMAC_ID_MC_LSB 23 100 #define TC0_DMAC_ID_MC_MSB 24 101 #define TC0_DMAC_ID_MC_SIZE 2 102 #define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger 103 #define TC0_EXT 0 104 #define TC0_GCLK_ID 27 105 #define TC0_MASTER 1 106 #define TC0_OW_NUM 2 107 108 #endif /* _SAML21_TC0_INSTANCE_ */ 109
