1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 37 /* Define to prevent recursive inclusion -------------------------------------*/ 38 #ifndef STM32L4xx_HAL_H 39 #define STM32L4xx_HAL_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* Includes ------------------------------------------------------------------*/ 46 #include "stm32l4xx_hal_conf.h" 47 48 /** @addtogroup STM32L4xx_HAL_Driver 49 * @{ 50 */ 51 52 /** @addtogroup HAL 53 * @{ 54 */ 55 56 /* Exported types ------------------------------------------------------------*/ 57 /* Exported constants --------------------------------------------------------*/ 58 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 59 * @{ 60 */ 61 62 /** @defgroup SYSCFG_BootMode Boot Mode 63 * @{ 64 */ 65 #define SYSCFG_BOOT_MAINFLASH 0U 66 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 67 68 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 69 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 70 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 71 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 72 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 73 /* STM32L496xx || STM32L4A6xx || */ 74 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 75 76 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 77 78 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 79 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 80 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 81 #else 82 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 83 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 84 85 /** 86 * @} 87 */ 88 89 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 90 * @{ 91 */ 92 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 93 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 94 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 95 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 96 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 97 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 98 99 /** 100 * @} 101 */ 102 103 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 104 * @{ 105 */ 106 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 107 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 108 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 109 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 110 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 111 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 112 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 113 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 114 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 115 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 116 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 117 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 118 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 119 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 120 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 121 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 122 #if defined(SYSCFG_SWPR_PAGE31) 123 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 124 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 125 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 126 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 127 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 128 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 129 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 130 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 131 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 132 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 133 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 134 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 135 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 136 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 137 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 138 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 139 #endif /* SYSCFG_SWPR_PAGE31 */ 140 141 /** 142 * @} 143 */ 144 145 #if defined(SYSCFG_SWPR2_PAGE63) 146 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 147 * @{ 148 */ 149 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 150 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 151 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 152 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 153 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 154 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 155 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 156 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 157 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 158 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 159 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 160 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 161 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 162 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 163 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 164 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 165 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 166 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 167 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 168 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 169 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 170 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 171 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 172 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 173 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 174 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 175 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 176 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 177 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 178 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 179 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 180 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 181 182 /** 183 * @} 184 */ 185 #endif /* SYSCFG_SWPR2_PAGE63 */ 186 187 #if defined(VREFBUF) 188 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 189 * @{ 190 */ 191 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 192 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 193 194 /** 195 * @} 196 */ 197 198 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 199 * @{ 200 */ 201 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 202 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 203 204 /** 205 * @} 206 */ 207 #endif /* VREFBUF */ 208 209 /** @defgroup SYSCFG_flags_definition Flags 210 * @{ 211 */ 212 213 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 214 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 215 216 /** 217 * @} 218 */ 219 220 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 221 * @{ 222 */ 223 224 /** @brief Fast-mode Plus driving capability on a specific GPIO 225 */ 226 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 227 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 228 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 229 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 230 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 231 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 232 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 233 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 234 235 /** 236 * @} 237 */ 238 239 /** 240 * @} 241 */ 242 243 /* Exported macros -----------------------------------------------------------*/ 244 245 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 246 * @{ 247 */ 248 249 /** @brief Freeze/Unfreeze Peripherals in Debug mode 250 */ 251 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 252 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 253 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 254 #endif 255 256 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 257 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 258 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 259 #endif 260 261 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 262 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 263 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 264 #endif 265 266 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 267 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 268 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 269 #endif 270 271 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 272 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 273 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 274 #endif 275 276 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 277 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 278 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 279 #endif 280 281 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 282 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 283 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 284 #endif 285 286 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 287 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 288 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 289 #endif 290 291 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 292 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 293 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 294 #endif 295 296 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 297 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 298 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 299 #endif 300 301 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 302 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 303 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 304 #endif 305 306 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 307 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 308 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 309 #endif 310 311 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 312 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 313 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 314 #endif 315 316 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 317 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 318 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 319 #endif 320 321 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 322 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 323 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 324 #endif 325 326 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 327 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 328 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 329 #endif 330 331 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 332 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 333 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 334 #endif 335 336 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 337 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 338 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 339 #endif 340 341 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 342 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 343 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 344 #endif 345 346 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 347 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 348 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 349 #endif 350 351 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 352 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 353 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 354 #endif 355 356 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 357 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 358 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 359 #endif 360 361 /** 362 * @} 363 */ 364 365 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 366 * @{ 367 */ 368 369 /** @brief Main Flash memory mapped at 0x00000000. 370 */ 371 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 372 373 /** @brief System Flash memory mapped at 0x00000000. 374 */ 375 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 376 377 /** @brief Embedded SRAM mapped at 0x00000000. 378 */ 379 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 380 381 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 382 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 383 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 384 385 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 386 */ 387 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 388 389 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 390 /* STM32L496xx || STM32L4A6xx || */ 391 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 392 393 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 394 395 /** @brief OCTOSPI mapped at 0x00000000. 396 */ 397 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 398 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 399 400 #else 401 402 /** @brief QUADSPI mapped at 0x00000000. 403 */ 404 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 405 406 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 407 408 /** 409 * @brief Return the boot mode as configured by user. 410 * @retval The boot mode as configured by user. The returned value can be one 411 * of the following values: 412 * @arg @ref SYSCFG_BOOT_MAINFLASH 413 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 414 @if STM32L486xx 415 * @arg @ref SYSCFG_BOOT_FMC 416 @endif 417 * @arg @ref SYSCFG_BOOT_SRAM 418 * @arg @ref SYSCFG_BOOT_QUADSPI 419 */ 420 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 421 422 /** @brief SRAM2 page 0 to 31 write protection enable macro 423 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 424 * @note Write protection can only be disabled by a system reset 425 */ 426 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 427 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 428 }while(0) 429 430 #if defined(SYSCFG_SWPR2_PAGE63) 431 /** @brief SRAM2 page 32 to 63 write protection enable macro 432 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 433 * @note Write protection can only be disabled by a system reset 434 */ 435 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 436 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 437 }while(0) 438 #endif /* SYSCFG_SWPR2_PAGE63 */ 439 440 /** @brief SRAM2 page write protection unlock prior to erase 441 * @note Writing a wrong key reactivates the write protection 442 */ 443 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 444 SYSCFG->SKR = 0x53;\ 445 }while(0) 446 447 /** @brief SRAM2 erase 448 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 449 */ 450 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 451 452 /** @brief Floating Point Unit interrupt enable/disable macros 453 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 454 */ 455 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 456 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 457 }while(0) 458 459 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 460 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 461 }while(0) 462 463 /** @brief SYSCFG Break ECC lock. 464 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 465 * @note The selected configuration is locked and can be unlocked only by system reset. 466 */ 467 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 468 469 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 470 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 471 * @note The selected configuration is locked and can be unlocked only by system reset. 472 */ 473 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 474 475 /** @brief SYSCFG Break PVD lock. 476 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 477 * @note The selected configuration is locked and can be unlocked only by system reset. 478 */ 479 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 480 481 /** @brief SYSCFG Break SRAM2 parity lock. 482 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 483 * @note The selected configuration is locked and can be unlocked by system reset. 484 */ 485 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 486 487 /** @brief Check SYSCFG flag is set or not. 488 * @param __FLAG__ specifies the flag to check. 489 * This parameter can be one of the following values: 490 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 491 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 492 * @retval The new state of __FLAG__ (TRUE or FALSE). 493 */ 494 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 495 496 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 497 */ 498 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 499 500 /** @brief Fast-mode Plus driving capability enable/disable macros 501 * @param __FASTMODEPLUS__ This parameter can be a value of : 502 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 503 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 504 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 505 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 506 */ 507 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 508 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 509 }while(0) 510 511 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 512 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 513 }while(0) 514 515 /** 516 * @} 517 */ 518 519 /* Private macros ------------------------------------------------------------*/ 520 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 521 * @{ 522 */ 523 524 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 525 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 526 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 527 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 528 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 529 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 530 531 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 532 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 533 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 534 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 535 536 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 537 538 #if defined(VREFBUF) 539 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 540 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 541 542 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 543 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 544 545 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 546 #endif /* VREFBUF */ 547 548 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 549 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 550 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 551 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 552 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 553 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 554 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 555 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 556 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 557 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 558 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 559 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 560 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 561 #else 562 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 563 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 564 #endif 565 /** 566 * @} 567 */ 568 569 /* Exported variables --------------------------------------------------------*/ 570 571 /** @addtogroup HAL_Exported_Variables 572 * @{ 573 */ 574 extern __IO uint32_t uwTick; 575 /** 576 * @} 577 */ 578 579 /* Exported functions --------------------------------------------------------*/ 580 581 /** @addtogroup HAL_Exported_Functions 582 * @{ 583 */ 584 585 /** @addtogroup HAL_Exported_Functions_Group1 586 * @{ 587 */ 588 589 /* Initialization and de-initialization functions ******************************/ 590 HAL_StatusTypeDef HAL_Init(void); 591 HAL_StatusTypeDef HAL_DeInit(void); 592 void HAL_MspInit(void); 593 void HAL_MspDeInit(void); 594 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 595 596 /** 597 * @} 598 */ 599 600 /** @addtogroup HAL_Exported_Functions_Group2 601 * @{ 602 */ 603 604 /* Peripheral Control functions ************************************************/ 605 void HAL_IncTick(void); 606 void HAL_Delay(uint32_t Delay); 607 uint32_t HAL_GetTick(void); 608 void HAL_SuspendTick(void); 609 void HAL_ResumeTick(void); 610 uint32_t HAL_GetHalVersion(void); 611 uint32_t HAL_GetREVID(void); 612 uint32_t HAL_GetDEVID(void); 613 uint32_t HAL_GetUIDw0(void); 614 uint32_t HAL_GetUIDw1(void); 615 uint32_t HAL_GetUIDw2(void); 616 617 /** 618 * @} 619 */ 620 621 /** @addtogroup HAL_Exported_Functions_Group3 622 * @{ 623 */ 624 625 /* DBGMCU Peripheral Control functions *****************************************/ 626 void HAL_DBGMCU_EnableDBGSleepMode(void); 627 void HAL_DBGMCU_DisableDBGSleepMode(void); 628 void HAL_DBGMCU_EnableDBGStopMode(void); 629 void HAL_DBGMCU_DisableDBGStopMode(void); 630 void HAL_DBGMCU_EnableDBGStandbyMode(void); 631 void HAL_DBGMCU_DisableDBGStandbyMode(void); 632 633 /** 634 * @} 635 */ 636 637 /** @addtogroup HAL_Exported_Functions_Group4 638 * @{ 639 */ 640 641 /* SYSCFG Control functions ****************************************************/ 642 void HAL_SYSCFG_SRAM2Erase(void); 643 void HAL_SYSCFG_EnableMemorySwappingBank(void); 644 void HAL_SYSCFG_DisableMemorySwappingBank(void); 645 646 #if defined(VREFBUF) 647 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 648 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 649 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 650 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 651 void HAL_SYSCFG_DisableVREFBUF(void); 652 #endif /* VREFBUF */ 653 654 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 655 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 656 657 /** 658 * @} 659 */ 660 661 /** 662 * @} 663 */ 664 665 /** 666 * @} 667 */ 668 669 /** 670 * @} 671 */ 672 673 #ifdef __cplusplus 674 } 675 #endif 676 677 #endif /* STM32L4xx_HAL_H */ 678 679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 680
