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Searched refs:SPI_CR1_CPHA (Results 1 – 17 of 17) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_spi.h183 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i…
474 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); in LL_SPI_SetClockPhase()
487 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); in LL_SPI_GetClockPhase()
Dstm32l4xx_hal_spi.h285 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_spi.h185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i…
417 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); in LL_SPI_SetClockPhase()
430 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); in LL_SPI_GetClockPhase()
Dstm32l1xx_hal_spi.h241 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_spi.h184 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i…
414 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); in LL_SPI_SetClockPhase()
427 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); in LL_SPI_GetClockPhase()
Dstm32l0xx_hal_spi.h226 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_ll_spi.c65 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_ll_spi.c66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_ll_spi.c66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h4926 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h5433 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h5050 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h5050 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h5282 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h5615 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h5721 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ macro
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h13206 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase … macro