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Searched refs:SHCSR (Results 1 – 17 of 17) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_cortex.c446 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in HAL_MPU_Disable()
469 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in HAL_MPU_Enable()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_cortex.h411 SET_BIT(SCB->SHCSR, Fault); in LL_HANDLER_EnableFault()
426 CLEAR_BIT(SCB->SHCSR, Fault); in LL_HANDLER_DisableFault()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_cortex.h411 SET_BIT(SCB->SHCSR, Fault); in LL_HANDLER_EnableFault()
426 CLEAR_BIT(SCB->SHCSR, Fault); in LL_HANDLER_DisableFault()
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm0.h344 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm0plus.h359 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc000.h350 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm3.h357 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc300.h357 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm4.h404 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm7.h419 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcore_cm0.h399 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm0plus.h417 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc000.h405 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm3.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc300.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm4.h494 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm7.h509 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member