1 /*
2  * Copyright (c) 2017 Google LLC.
3  * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #define DT_DRV_COMPAT atmel_sam0_uart
9 
10 #include <zephyr/device.h>
11 #include <errno.h>
12 #include <zephyr/init.h>
13 #include <zephyr/sys/__assert.h>
14 #include <soc.h>
15 #include <zephyr/drivers/uart.h>
16 #include <zephyr/drivers/dma.h>
17 #include <zephyr/drivers/pinctrl.h>
18 #include <string.h>
19 #include <zephyr/irq.h>
20 
21 /* clang-format off */
22 
23 #ifndef SERCOM_USART_CTRLA_MODE_USART_INT_CLK
24 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK SERCOM_USART_CTRLA_MODE(0x1)
25 #endif
26 
27 /*
28  * Interrupt error flag is only supported in devices with
29  * SERCOM revision 0x500
30  */
31 #if defined(SERCOM_U2201) && (REV_SERCOM == 0x500)
32 #define SERCOM_REV500
33 #endif
34 
35 /* Device constant configuration parameters */
36 struct uart_sam0_dev_cfg {
37 	SercomUsart *regs;
38 	uint32_t baudrate;
39 	uint32_t pads;
40 	bool     collision_detect;
41 	volatile uint32_t *mclk;
42 	uint32_t mclk_mask;
43 	uint32_t gclk_gen;
44 	uint16_t gclk_id;
45 
46 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
47 	void (*irq_config_func)(const struct device *dev);
48 #endif
49 #if CONFIG_UART_SAM0_ASYNC
50 	const struct device *dma_dev;
51 	uint8_t tx_dma_request;
52 	uint8_t tx_dma_channel;
53 	uint8_t rx_dma_request;
54 	uint8_t rx_dma_channel;
55 #endif
56 	const struct pinctrl_dev_config *pcfg;
57 };
58 
59 /* Device run time data */
60 struct uart_sam0_dev_data {
61 	struct uart_config config_cache;
62 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
63 	uart_irq_callback_user_data_t cb;
64 	void *cb_data;
65 	uint8_t txc_cache;
66 #endif
67 #if CONFIG_UART_SAM0_ASYNC
68 	const struct device *dev;
69 	const struct uart_sam0_dev_cfg *cfg;
70 
71 	uart_callback_t async_cb;
72 	void *async_cb_data;
73 
74 	struct k_work_delayable tx_timeout_work;
75 	const uint8_t *tx_buf;
76 	size_t tx_len;
77 
78 	struct k_work_delayable rx_timeout_work;
79 	size_t rx_timeout_time;
80 	size_t rx_timeout_chunk;
81 	uint32_t rx_timeout_start;
82 	uint8_t *rx_buf;
83 	size_t rx_len;
84 	size_t rx_processed_len;
85 	uint8_t *rx_next_buf;
86 	size_t rx_next_len;
87 	bool rx_waiting_for_irq;
88 	bool rx_timeout_from_isr;
89 #endif
90 };
91 
wait_synchronization(SercomUsart * const usart)92 static void wait_synchronization(SercomUsart *const usart)
93 {
94 #if defined(SERCOM_USART_SYNCBUSY_MASK)
95 	/* SYNCBUSY is a register */
96 	while ((usart->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_MASK) != 0) {
97 	}
98 #elif defined(SERCOM_USART_STATUS_SYNCBUSY)
99 	/* SYNCBUSY is a bit */
100 	while ((usart->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) != 0) {
101 	}
102 #else
103 #error Unsupported device
104 #endif
105 }
106 
uart_sam0_set_baudrate(SercomUsart * const usart,uint32_t baudrate,uint32_t clk_freq_hz)107 static int uart_sam0_set_baudrate(SercomUsart *const usart, uint32_t baudrate,
108 				  uint32_t clk_freq_hz)
109 {
110 	uint64_t tmp;
111 	uint16_t baud;
112 
113 	tmp = (uint64_t)baudrate << 20;
114 	tmp = (tmp + (clk_freq_hz >> 1)) / clk_freq_hz;
115 
116 	/* Verify that the calculated result is within range */
117 	if (tmp < 1 || tmp > UINT16_MAX) {
118 		return -ERANGE;
119 	}
120 
121 	baud = 65536 - (uint16_t)tmp;
122 	usart->BAUD.reg = baud;
123 	wait_synchronization(usart);
124 
125 	return 0;
126 }
127 
128 
129 #if CONFIG_UART_SAM0_ASYNC
130 
uart_sam0_dma_tx_done(const struct device * dma_dev,void * arg,uint32_t id,int error_code)131 static void uart_sam0_dma_tx_done(const struct device *dma_dev, void *arg,
132 				  uint32_t id, int error_code)
133 {
134 	ARG_UNUSED(dma_dev);
135 	ARG_UNUSED(id);
136 	ARG_UNUSED(error_code);
137 
138 	struct uart_sam0_dev_data *const dev_data =
139 		(struct uart_sam0_dev_data *const) arg;
140 	const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
141 
142 	SercomUsart * const regs = cfg->regs;
143 
144 	regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC;
145 }
146 
uart_sam0_tx_halt(struct uart_sam0_dev_data * dev_data)147 static int uart_sam0_tx_halt(struct uart_sam0_dev_data *dev_data)
148 {
149 	const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
150 	unsigned int key = irq_lock();
151 	size_t tx_active = dev_data->tx_len;
152 	struct dma_status st;
153 
154 	struct uart_event evt = {
155 		.type = UART_TX_ABORTED,
156 		.data.tx = {
157 			.buf = dev_data->tx_buf,
158 			.len = 0U,
159 		},
160 	};
161 
162 	dev_data->tx_buf = NULL;
163 	dev_data->tx_len = 0U;
164 
165 	dma_stop(cfg->dma_dev, cfg->tx_dma_channel);
166 
167 	irq_unlock(key);
168 
169 	if (dma_get_status(cfg->dma_dev, cfg->tx_dma_channel, &st) == 0) {
170 		evt.data.tx.len = tx_active - st.pending_length;
171 	}
172 
173 	if (tx_active) {
174 		if (dev_data->async_cb) {
175 			dev_data->async_cb(dev_data->dev,
176 					   &evt, dev_data->async_cb_data);
177 		}
178 	} else {
179 		return -EINVAL;
180 	}
181 
182 	return 0;
183 }
184 
uart_sam0_tx_timeout(struct k_work * work)185 static void uart_sam0_tx_timeout(struct k_work *work)
186 {
187 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
188 	struct uart_sam0_dev_data *dev_data = CONTAINER_OF(dwork,
189 							   struct uart_sam0_dev_data, tx_timeout_work);
190 
191 	uart_sam0_tx_halt(dev_data);
192 }
193 
uart_sam0_notify_rx_processed(struct uart_sam0_dev_data * dev_data,size_t processed)194 static void uart_sam0_notify_rx_processed(struct uart_sam0_dev_data *dev_data,
195 					  size_t processed)
196 {
197 	if (!dev_data->async_cb) {
198 		return;
199 	}
200 
201 	if (dev_data->rx_processed_len == processed) {
202 		return;
203 	}
204 
205 	struct uart_event evt = {
206 		.type = UART_RX_RDY,
207 		.data.rx = {
208 			.buf = dev_data->rx_buf,
209 			.offset = dev_data->rx_processed_len,
210 			.len = processed - dev_data->rx_processed_len,
211 		},
212 	};
213 
214 	dev_data->rx_processed_len = processed;
215 
216 	dev_data->async_cb(dev_data->dev,
217 			   &evt, dev_data->async_cb_data);
218 }
219 
uart_sam0_dma_rx_done(const struct device * dma_dev,void * arg,uint32_t id,int error_code)220 static void uart_sam0_dma_rx_done(const struct device *dma_dev, void *arg,
221 				  uint32_t id, int error_code)
222 {
223 	ARG_UNUSED(dma_dev);
224 	ARG_UNUSED(id);
225 	ARG_UNUSED(error_code);
226 
227 	struct uart_sam0_dev_data *const dev_data =
228 		(struct uart_sam0_dev_data *const)arg;
229 	const struct device *dev = dev_data->dev;
230 	const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
231 	SercomUsart * const regs = cfg->regs;
232 	unsigned int key = irq_lock();
233 
234 	if (dev_data->rx_len == 0U) {
235 		irq_unlock(key);
236 		return;
237 	}
238 
239 	uart_sam0_notify_rx_processed(dev_data, dev_data->rx_len);
240 
241 	if (dev_data->async_cb) {
242 		struct uart_event evt = {
243 			.type = UART_RX_BUF_RELEASED,
244 			.data.rx_buf = {
245 				.buf = dev_data->rx_buf,
246 			},
247 		};
248 
249 		dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
250 	}
251 
252 	/* No next buffer, so end the transfer */
253 	if (!dev_data->rx_next_len) {
254 		dev_data->rx_buf = NULL;
255 		dev_data->rx_len = 0U;
256 
257 		if (dev_data->async_cb) {
258 			struct uart_event evt = {
259 				.type = UART_RX_DISABLED,
260 			};
261 
262 			dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
263 		}
264 
265 		irq_unlock(key);
266 		return;
267 	}
268 
269 	dev_data->rx_buf = dev_data->rx_next_buf;
270 	dev_data->rx_len = dev_data->rx_next_len;
271 	dev_data->rx_next_buf = NULL;
272 	dev_data->rx_next_len = 0U;
273 	dev_data->rx_processed_len = 0U;
274 
275 	dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
276 		   (uint32_t)(&(regs->DATA.reg)),
277 		   (uint32_t)dev_data->rx_buf, dev_data->rx_len);
278 
279 	/*
280 	 * If there should be a timeout, handle starting the DMA in the
281 	 * ISR, since reception resets it and DMA completion implies
282 	 * reception.  This also catches the case of DMA completion during
283 	 * timeout handling.
284 	 */
285 	if (dev_data->rx_timeout_time != SYS_FOREVER_US) {
286 		dev_data->rx_waiting_for_irq = true;
287 		regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
288 		irq_unlock(key);
289 		return;
290 	}
291 
292 	/* Otherwise, start the transfer immediately. */
293 	dma_start(cfg->dma_dev, cfg->rx_dma_channel);
294 
295 	struct uart_event evt = {
296 		.type = UART_RX_BUF_REQUEST,
297 	};
298 
299 	dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
300 
301 	irq_unlock(key);
302 }
303 
uart_sam0_rx_timeout(struct k_work * work)304 static void uart_sam0_rx_timeout(struct k_work *work)
305 {
306 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
307 	struct uart_sam0_dev_data *dev_data = CONTAINER_OF(dwork,
308 							   struct uart_sam0_dev_data, rx_timeout_work);
309 	const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
310 	SercomUsart * const regs = cfg->regs;
311 	struct dma_status st;
312 	unsigned int key = irq_lock();
313 
314 	if (dev_data->rx_len == 0U) {
315 		irq_unlock(key);
316 		return;
317 	}
318 
319 	/*
320 	 * Stop the DMA transfer and restart the interrupt read
321 	 * component (so the timeout restarts if there's still data).
322 	 * However, just ignore it if the transfer has completed (nothing
323 	 * pending) that means the DMA ISR is already pending, so just let
324 	 * it handle things instead when we re-enable IRQs.
325 	 */
326 	dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
327 	if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel,
328 			   &st) == 0 && st.pending_length == 0U) {
329 		irq_unlock(key);
330 		return;
331 	}
332 
333 	uint8_t *rx_dma_start = dev_data->rx_buf + dev_data->rx_len -
334 			     st.pending_length;
335 	size_t rx_processed = rx_dma_start - dev_data->rx_buf;
336 
337 	/*
338 	 * We know we still have space, since the above will catch the
339 	 * empty buffer, so always restart the transfer.
340 	 */
341 	dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
342 		   (uint32_t)(&(regs->DATA.reg)),
343 		   (uint32_t)rx_dma_start,
344 		   dev_data->rx_len - rx_processed);
345 
346 	dev_data->rx_waiting_for_irq = true;
347 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
348 
349 	/*
350 	 * Never do a notify on a timeout started from the ISR: timing
351 	 * granularity means the first timeout can be in the middle
352 	 * of reception but still have the total elapsed time exhausted.
353 	 * So we require a timeout chunk with no data seen at all
354 	 * (i.e. no ISR entry).
355 	 */
356 	if (dev_data->rx_timeout_from_isr) {
357 		dev_data->rx_timeout_from_isr = false;
358 		k_work_reschedule(&dev_data->rx_timeout_work,
359 				      K_USEC(dev_data->rx_timeout_chunk));
360 		irq_unlock(key);
361 		return;
362 	}
363 
364 	uint32_t now = k_uptime_get_32();
365 	uint32_t elapsed = now - dev_data->rx_timeout_start;
366 
367 	if (elapsed >= dev_data->rx_timeout_time) {
368 		/*
369 		 * No time left, so call the handler, and let the ISR
370 		 * restart the timeout when it sees data.
371 		 */
372 		uart_sam0_notify_rx_processed(dev_data, rx_processed);
373 	} else {
374 		/*
375 		 * Still have time left, so start another timeout.
376 		 */
377 		uint32_t remaining = MIN(dev_data->rx_timeout_time - elapsed,
378 				      dev_data->rx_timeout_chunk);
379 
380 		k_work_reschedule(&dev_data->rx_timeout_work,
381 				      K_USEC(remaining));
382 	}
383 
384 	irq_unlock(key);
385 }
386 
387 #endif
388 
389 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_sam0_configure(const struct device * dev,const struct uart_config * new_cfg)390 static int uart_sam0_configure(const struct device *dev,
391 			       const struct uart_config *new_cfg)
392 {
393 	int retval;
394 
395 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
396 	struct uart_sam0_dev_data *const dev_data = dev->data;
397 	SercomUsart * const usart = cfg->regs;
398 
399 	wait_synchronization(usart);
400 
401 	usart->CTRLA.bit.ENABLE = 0;
402 	wait_synchronization(usart);
403 
404 	if (new_cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
405 		/* Flow control not yet supported though in principle possible
406 		 * on this soc family.
407 		 */
408 		return -ENOTSUP;
409 	}
410 
411 	dev_data->config_cache.flow_ctrl = new_cfg->flow_ctrl;
412 
413 	SERCOM_USART_CTRLA_Type CTRLA_temp = usart->CTRLA;
414 	SERCOM_USART_CTRLB_Type CTRLB_temp = usart->CTRLB;
415 
416 	switch (new_cfg->parity) {
417 	case UART_CFG_PARITY_NONE:
418 		CTRLA_temp.bit.FORM = 0x0;
419 		break;
420 	case UART_CFG_PARITY_ODD:
421 		CTRLA_temp.bit.FORM = 0x1;
422 		CTRLB_temp.bit.PMODE = 1;
423 		break;
424 	case UART_CFG_PARITY_EVEN:
425 		CTRLA_temp.bit.FORM = 0x1;
426 		CTRLB_temp.bit.PMODE = 0;
427 		break;
428 	default:
429 		return -ENOTSUP;
430 	}
431 
432 	dev_data->config_cache.parity = new_cfg->parity;
433 
434 	switch (new_cfg->stop_bits) {
435 	case UART_CFG_STOP_BITS_1:
436 		CTRLB_temp.bit.SBMODE = 0;
437 		break;
438 	case UART_CFG_STOP_BITS_2:
439 		CTRLB_temp.bit.SBMODE = 1;
440 		break;
441 	default:
442 		return -ENOTSUP;
443 	}
444 
445 	dev_data->config_cache.stop_bits = new_cfg->stop_bits;
446 
447 	switch (new_cfg->data_bits) {
448 	case UART_CFG_DATA_BITS_5:
449 		CTRLB_temp.bit.CHSIZE = 0x5;
450 		break;
451 	case UART_CFG_DATA_BITS_6:
452 		CTRLB_temp.bit.CHSIZE = 0x6;
453 		break;
454 	case UART_CFG_DATA_BITS_7:
455 		CTRLB_temp.bit.CHSIZE = 0x7;
456 		break;
457 	case UART_CFG_DATA_BITS_8:
458 		CTRLB_temp.bit.CHSIZE = 0x0;
459 		break;
460 	case UART_CFG_DATA_BITS_9:
461 		CTRLB_temp.bit.CHSIZE = 0x1;
462 		break;
463 	default:
464 		return -ENOTSUP;
465 	}
466 
467 	dev_data->config_cache.data_bits = new_cfg->data_bits;
468 
469 #if defined(SERCOM_REV500)
470 	CTRLB_temp.bit.COLDEN = cfg->pads;
471 #endif
472 
473 	usart->CTRLA = CTRLA_temp;
474 	wait_synchronization(usart);
475 
476 	usart->CTRLB = CTRLB_temp;
477 	wait_synchronization(usart);
478 
479 	retval = uart_sam0_set_baudrate(usart, new_cfg->baudrate,
480 					SOC_ATMEL_SAM0_GCLK0_FREQ_HZ);
481 	if (retval != 0) {
482 		return retval;
483 	}
484 
485 	dev_data->config_cache.baudrate = new_cfg->baudrate;
486 
487 	usart->CTRLA.bit.ENABLE = 1;
488 	wait_synchronization(usart);
489 
490 	return 0;
491 }
492 
uart_sam0_config_get(const struct device * dev,struct uart_config * out_cfg)493 static int uart_sam0_config_get(const struct device *dev,
494 				struct uart_config *out_cfg)
495 {
496 	struct uart_sam0_dev_data *const dev_data = dev->data;
497 
498 	memcpy(out_cfg, &(dev_data->config_cache),
499 				sizeof(dev_data->config_cache));
500 
501 	return 0;
502 }
503 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
504 
uart_sam0_init(const struct device * dev)505 static int uart_sam0_init(const struct device *dev)
506 {
507 	int retval;
508 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
509 	struct uart_sam0_dev_data *const dev_data = dev->data;
510 
511 	SercomUsart * const usart = cfg->regs;
512 
513 	*cfg->mclk |= cfg->mclk_mask;
514 
515 #ifdef MCLK
516 	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
517 					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
518 #else
519 	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
520 			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
521 			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
522 #endif
523 
524 	/* Disable all USART interrupts */
525 	usart->INTENCLR.reg = SERCOM_USART_INTENCLR_MASK;
526 	wait_synchronization(usart);
527 
528 	/* 8 bits of data, no parity, 1 stop bit in normal mode */
529 	usart->CTRLA.reg =
530 	    cfg->pads
531 	    /* Internal clock */
532 	    | SERCOM_USART_CTRLA_MODE_USART_INT_CLK
533 #if defined(SERCOM_USART_CTRLA_SAMPR)
534 	    /* 16x oversampling with arithmetic baud rate generation */
535 	    | SERCOM_USART_CTRLA_SAMPR(0)
536 #endif
537 	    | SERCOM_USART_CTRLA_FORM(0) |
538 	    SERCOM_USART_CTRLA_CPOL | SERCOM_USART_CTRLA_DORD;
539 	wait_synchronization(usart);
540 
541 	/* Enable PINMUX based on PINCTRL */
542 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
543 	if (retval < 0) {
544 		return retval;
545 	}
546 
547 	dev_data->config_cache.flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
548 	dev_data->config_cache.parity = UART_CFG_PARITY_NONE;
549 	dev_data->config_cache.stop_bits = UART_CFG_STOP_BITS_1;
550 	dev_data->config_cache.data_bits = UART_CFG_DATA_BITS_8;
551 
552 	/* Enable receiver and transmitter */
553 	usart->CTRLB.reg = SERCOM_USART_CTRLB_CHSIZE(0) |
554 			   SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN;
555 	wait_synchronization(usart);
556 
557 	retval = uart_sam0_set_baudrate(usart, cfg->baudrate,
558 					SOC_ATMEL_SAM0_GCLK0_FREQ_HZ);
559 	if (retval != 0) {
560 		return retval;
561 	}
562 	dev_data->config_cache.baudrate = cfg->baudrate;
563 
564 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
565 	cfg->irq_config_func(dev);
566 #endif
567 
568 #ifdef CONFIG_UART_SAM0_ASYNC
569 	dev_data->dev = dev;
570 	dev_data->cfg = cfg;
571 	if (!device_is_ready(cfg->dma_dev)) {
572 		return -ENODEV;
573 	}
574 
575 	k_work_init_delayable(&dev_data->tx_timeout_work, uart_sam0_tx_timeout);
576 	k_work_init_delayable(&dev_data->rx_timeout_work, uart_sam0_rx_timeout);
577 
578 	if (cfg->tx_dma_channel != 0xFFU) {
579 		struct dma_config dma_cfg = { 0 };
580 		struct dma_block_config dma_blk = { 0 };
581 
582 		dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
583 		dma_cfg.source_data_size = 1;
584 		dma_cfg.dest_data_size = 1;
585 		dma_cfg.user_data = dev_data;
586 		dma_cfg.dma_callback = uart_sam0_dma_tx_done;
587 		dma_cfg.block_count = 1;
588 		dma_cfg.head_block = &dma_blk;
589 		dma_cfg.dma_slot = cfg->tx_dma_request;
590 
591 		dma_blk.block_size = 1;
592 		dma_blk.dest_address = (uint32_t)(&(usart->DATA.reg));
593 		dma_blk.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
594 
595 		retval = dma_config(cfg->dma_dev, cfg->tx_dma_channel,
596 				    &dma_cfg);
597 		if (retval != 0) {
598 			return retval;
599 		}
600 	}
601 
602 	if (cfg->rx_dma_channel != 0xFFU) {
603 		struct dma_config dma_cfg = { 0 };
604 		struct dma_block_config dma_blk = { 0 };
605 
606 		dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
607 		dma_cfg.source_data_size = 1;
608 		dma_cfg.dest_data_size = 1;
609 		dma_cfg.user_data = dev_data;
610 		dma_cfg.dma_callback = uart_sam0_dma_rx_done;
611 		dma_cfg.block_count = 1;
612 		dma_cfg.head_block = &dma_blk;
613 		dma_cfg.dma_slot = cfg->rx_dma_request;
614 
615 		dma_blk.block_size = 1;
616 		dma_blk.source_address = (uint32_t)(&(usart->DATA.reg));
617 		dma_blk.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
618 
619 		retval = dma_config(cfg->dma_dev, cfg->rx_dma_channel,
620 				    &dma_cfg);
621 		if (retval != 0) {
622 			return retval;
623 		}
624 	}
625 
626 #endif
627 
628 	usart->CTRLA.bit.ENABLE = 1;
629 	wait_synchronization(usart);
630 
631 	return 0;
632 }
633 
uart_sam0_poll_in(const struct device * dev,unsigned char * c)634 static int uart_sam0_poll_in(const struct device *dev, unsigned char *c)
635 {
636 	const struct uart_sam0_dev_cfg *config = dev->config;
637 
638 	SercomUsart * const usart = config->regs;
639 
640 	if (!usart->INTFLAG.bit.RXC) {
641 		return -EBUSY;
642 	}
643 
644 	*c = (unsigned char)usart->DATA.reg;
645 	return 0;
646 }
647 
uart_sam0_poll_out(const struct device * dev,unsigned char c)648 static void uart_sam0_poll_out(const struct device *dev, unsigned char c)
649 {
650 	const struct uart_sam0_dev_cfg *config = dev->config;
651 
652 	SercomUsart * const usart = config->regs;
653 
654 	while (!usart->INTFLAG.bit.DRE) {
655 	}
656 
657 	/* send a character */
658 	usart->DATA.reg = c;
659 }
660 
uart_sam0_err_check(const struct device * dev)661 static int uart_sam0_err_check(const struct device *dev)
662 {
663 	const struct uart_sam0_dev_cfg *config = dev->config;
664 
665 	SercomUsart * const regs = config->regs;
666 	uint32_t err = 0U;
667 
668 	if (regs->STATUS.reg & SERCOM_USART_STATUS_BUFOVF) {
669 		err |= UART_ERROR_OVERRUN;
670 	}
671 
672 	if (regs->STATUS.reg & SERCOM_USART_STATUS_FERR) {
673 		err |= UART_ERROR_PARITY;
674 	}
675 
676 	if (regs->STATUS.reg & SERCOM_USART_STATUS_PERR) {
677 		err |= UART_ERROR_FRAMING;
678 	}
679 
680 #if defined(SERCOM_REV500)
681 	if (regs->STATUS.reg & SERCOM_USART_STATUS_ISF) {
682 		err |= UART_BREAK;
683 	}
684 
685 	if (regs->STATUS.reg & SERCOM_USART_STATUS_COLL) {
686 		err |= UART_ERROR_COLLISION;
687 	}
688 
689 	regs->STATUS.reg |=	SERCOM_USART_STATUS_BUFOVF
690 			 |	SERCOM_USART_STATUS_FERR
691 			 |	SERCOM_USART_STATUS_PERR
692 			 |	SERCOM_USART_STATUS_COLL
693 			 |	SERCOM_USART_STATUS_ISF;
694 #else
695 	regs->STATUS.reg |=	SERCOM_USART_STATUS_BUFOVF
696 			 |	SERCOM_USART_STATUS_FERR
697 			 |	SERCOM_USART_STATUS_PERR;
698 #endif
699 
700 	wait_synchronization(regs);
701 	return err;
702 }
703 
704 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
705 
uart_sam0_isr(const struct device * dev)706 static void uart_sam0_isr(const struct device *dev)
707 {
708 	struct uart_sam0_dev_data *const dev_data = dev->data;
709 
710 #if CONFIG_UART_INTERRUPT_DRIVEN
711 	if (dev_data->cb) {
712 		dev_data->cb(dev, dev_data->cb_data);
713 	}
714 #endif
715 
716 #if CONFIG_UART_SAM0_ASYNC
717 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
718 	SercomUsart * const regs = cfg->regs;
719 
720 	if (dev_data->tx_len && regs->INTFLAG.bit.TXC) {
721 		regs->INTENCLR.reg = SERCOM_USART_INTENCLR_TXC;
722 
723 		k_work_cancel_delayable(&dev_data->tx_timeout_work);
724 
725 		unsigned int key = irq_lock();
726 
727 		struct uart_event evt = {
728 			.type = UART_TX_DONE,
729 			.data.tx = {
730 				.buf = dev_data->tx_buf,
731 				.len = dev_data->tx_len,
732 			},
733 		};
734 
735 		dev_data->tx_buf = NULL;
736 		dev_data->tx_len = 0U;
737 
738 		if (evt.data.tx.len != 0U && dev_data->async_cb) {
739 			dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
740 		}
741 
742 		irq_unlock(key);
743 	}
744 
745 	if (dev_data->rx_len && regs->INTFLAG.bit.RXC &&
746 	    dev_data->rx_waiting_for_irq) {
747 		dev_data->rx_waiting_for_irq = false;
748 		regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
749 
750 		/* Receive started, so request the next buffer */
751 		if (dev_data->rx_next_len == 0U && dev_data->async_cb) {
752 			struct uart_event evt = {
753 				.type = UART_RX_BUF_REQUEST,
754 			};
755 
756 			dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
757 		}
758 
759 		/*
760 		 * If we have a timeout, restart the time remaining whenever
761 		 * we see data.
762 		 */
763 		if (dev_data->rx_timeout_time != SYS_FOREVER_US) {
764 			dev_data->rx_timeout_from_isr = true;
765 			dev_data->rx_timeout_start = k_uptime_get_32();
766 			k_work_reschedule(&dev_data->rx_timeout_work,
767 					      K_USEC(dev_data->rx_timeout_chunk));
768 		}
769 
770 		/* DMA will read the currently ready byte out */
771 		dma_start(cfg->dma_dev, cfg->rx_dma_channel);
772 	}
773 #endif
774 }
775 
776 #endif
777 
778 #if CONFIG_UART_INTERRUPT_DRIVEN
779 
uart_sam0_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)780 static int uart_sam0_fifo_fill(const struct device *dev,
781 			       const uint8_t *tx_data, int len)
782 {
783 	const struct uart_sam0_dev_cfg *config = dev->config;
784 	SercomUsart *regs = config->regs;
785 
786 	if (regs->INTFLAG.bit.DRE && len >= 1) {
787 		regs->DATA.reg = tx_data[0];
788 		return 1;
789 	} else {
790 		return 0;
791 	}
792 }
793 
uart_sam0_irq_tx_enable(const struct device * dev)794 static void uart_sam0_irq_tx_enable(const struct device *dev)
795 {
796 	const struct uart_sam0_dev_cfg *config = dev->config;
797 	SercomUsart * const regs = config->regs;
798 
799 	regs->INTENSET.reg = SERCOM_USART_INTENSET_DRE
800 			   | SERCOM_USART_INTENSET_TXC;
801 }
802 
uart_sam0_irq_tx_disable(const struct device * dev)803 static void uart_sam0_irq_tx_disable(const struct device *dev)
804 {
805 	const struct uart_sam0_dev_cfg *config = dev->config;
806 	SercomUsart * const regs = config->regs;
807 
808 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_DRE
809 			   | SERCOM_USART_INTENCLR_TXC;
810 }
811 
uart_sam0_irq_tx_ready(const struct device * dev)812 static int uart_sam0_irq_tx_ready(const struct device *dev)
813 {
814 	const struct uart_sam0_dev_cfg *config = dev->config;
815 	SercomUsart * const regs = config->regs;
816 
817 	return (regs->INTFLAG.bit.DRE != 0) && (regs->INTENSET.bit.DRE != 0);
818 }
819 
uart_sam0_irq_tx_complete(const struct device * dev)820 static int uart_sam0_irq_tx_complete(const struct device *dev)
821 {
822 	const struct uart_sam0_dev_cfg *config = dev->config;
823 	struct uart_sam0_dev_data *const dev_data = dev->data;
824 	SercomUsart * const regs = config->regs;
825 
826 	return (dev_data->txc_cache != 0) && (regs->INTENSET.bit.TXC != 0);
827 }
828 
uart_sam0_irq_rx_enable(const struct device * dev)829 static void uart_sam0_irq_rx_enable(const struct device *dev)
830 {
831 	const struct uart_sam0_dev_cfg *config = dev->config;
832 	SercomUsart * const regs = config->regs;
833 
834 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
835 }
836 
uart_sam0_irq_rx_disable(const struct device * dev)837 static void uart_sam0_irq_rx_disable(const struct device *dev)
838 {
839 	const struct uart_sam0_dev_cfg *config = dev->config;
840 	SercomUsart * const regs = config->regs;
841 
842 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
843 }
844 
uart_sam0_irq_rx_ready(const struct device * dev)845 static int uart_sam0_irq_rx_ready(const struct device *dev)
846 {
847 	const struct uart_sam0_dev_cfg *config = dev->config;
848 	SercomUsart * const regs = config->regs;
849 
850 	return regs->INTFLAG.bit.RXC != 0;
851 }
852 
uart_sam0_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)853 static int uart_sam0_fifo_read(const struct device *dev, uint8_t *rx_data,
854 			       const int size)
855 {
856 	const struct uart_sam0_dev_cfg *config = dev->config;
857 	SercomUsart * const regs = config->regs;
858 
859 	if (regs->INTFLAG.bit.RXC) {
860 		uint8_t ch = regs->DATA.reg;
861 
862 		if (size >= 1) {
863 			*rx_data = ch;
864 			return 1;
865 		} else {
866 			return -EINVAL;
867 		}
868 	}
869 	return 0;
870 }
871 
uart_sam0_irq_is_pending(const struct device * dev)872 static int uart_sam0_irq_is_pending(const struct device *dev)
873 {
874 	const struct uart_sam0_dev_cfg *config = dev->config;
875 	SercomUsart * const regs = config->regs;
876 
877 	return (regs->INTENSET.reg & regs->INTFLAG.reg) != 0;
878 }
879 
880 #if defined(SERCOM_REV500)
uart_sam0_irq_err_enable(const struct device * dev)881 static void uart_sam0_irq_err_enable(const struct device *dev)
882 {
883 	const struct uart_sam0_dev_cfg *config = dev->config;
884 	SercomUsart * const regs = config->regs;
885 
886 	regs->INTENSET.reg |= SERCOM_USART_INTENCLR_ERROR;
887 	wait_synchronization(regs);
888 }
889 
uart_sam0_irq_err_disable(const struct device * dev)890 static void uart_sam0_irq_err_disable(const struct device *dev)
891 {
892 	const struct uart_sam0_dev_cfg *config = dev->config;
893 	SercomUsart * const regs = config->regs;
894 
895 	regs->INTENCLR.reg |= SERCOM_USART_INTENSET_ERROR;
896 	wait_synchronization(regs);
897 }
898 #endif
899 
uart_sam0_irq_update(const struct device * dev)900 static int uart_sam0_irq_update(const struct device *dev)
901 {
902 	/* Clear sticky interrupts */
903 	const struct uart_sam0_dev_cfg *config = dev->config;
904 	SercomUsart * const regs = config->regs;
905 
906 #if defined(SERCOM_REV500)
907 	/*
908 	 * Cache the TXC flag, and use this cached value to clear the interrupt
909 	 * if we do not used the cached value, there is a chance TXC will set
910 	 * after caching...this will cause TXC to never cached.
911 	 */
912 	struct uart_sam0_dev_data *const dev_data = dev->data;
913 
914 	dev_data->txc_cache = regs->INTFLAG.bit.TXC;
915 	regs->INTFLAG.reg = SERCOM_USART_INTENCLR_ERROR
916 			  | SERCOM_USART_INTENCLR_RXBRK
917 			  | SERCOM_USART_INTENCLR_CTSIC
918 			  | SERCOM_USART_INTENCLR_RXS
919 			  | (dev_data->txc_cache << SERCOM_USART_INTENCLR_TXC_Pos);
920 #else
921 	regs->INTFLAG.reg = SERCOM_USART_INTENCLR_RXS;
922 #endif
923 	return 1;
924 }
925 
uart_sam0_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)926 static void uart_sam0_irq_callback_set(const struct device *dev,
927 				       uart_irq_callback_user_data_t cb,
928 				       void *cb_data)
929 {
930 	struct uart_sam0_dev_data *const dev_data = dev->data;
931 
932 	dev_data->cb = cb;
933 	dev_data->cb_data = cb_data;
934 
935 #if defined(CONFIG_UART_SAM0_ASYNC) && defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
936 	dev_data->async_cb = NULL;
937 	dev_data->async_cb_data = NULL;
938 #endif
939 }
940 #endif
941 
942 #ifdef CONFIG_UART_SAM0_ASYNC
943 
uart_sam0_callback_set(const struct device * dev,uart_callback_t callback,void * user_data)944 static int uart_sam0_callback_set(const struct device *dev,
945 				  uart_callback_t callback,
946 				  void *user_data)
947 {
948 	struct uart_sam0_dev_data *const dev_data = dev->data;
949 
950 	dev_data->async_cb = callback;
951 	dev_data->async_cb_data = user_data;
952 
953 #if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
954 	dev_data->cb = NULL;
955 	dev_data->cb_data = NULL;
956 #endif
957 
958 	return 0;
959 }
960 
uart_sam0_tx(const struct device * dev,const uint8_t * buf,size_t len,int32_t timeout)961 static int uart_sam0_tx(const struct device *dev, const uint8_t *buf,
962 			size_t len,
963 			int32_t timeout)
964 {
965 	struct uart_sam0_dev_data *const dev_data = dev->data;
966 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
967 	SercomUsart *regs = cfg->regs;
968 	int retval;
969 
970 	if (cfg->tx_dma_channel == 0xFFU) {
971 		return -ENOTSUP;
972 	}
973 
974 	if (len > 0xFFFFU) {
975 		return -EINVAL;
976 	}
977 
978 	unsigned int key = irq_lock();
979 
980 	if (dev_data->tx_len != 0U) {
981 		retval = -EBUSY;
982 		goto err;
983 	}
984 
985 	dev_data->tx_buf = buf;
986 	dev_data->tx_len = len;
987 
988 	irq_unlock(key);
989 
990 	retval = dma_reload(cfg->dma_dev, cfg->tx_dma_channel, (uint32_t)buf,
991 			    (uint32_t)(&(regs->DATA.reg)), len);
992 	if (retval != 0U) {
993 		return retval;
994 	}
995 
996 	if (timeout != SYS_FOREVER_US) {
997 		k_work_reschedule(&dev_data->tx_timeout_work,
998 				      K_USEC(timeout));
999 	}
1000 
1001 	return dma_start(cfg->dma_dev, cfg->tx_dma_channel);
1002 err:
1003 	irq_unlock(key);
1004 	return retval;
1005 }
1006 
uart_sam0_tx_abort(const struct device * dev)1007 static int uart_sam0_tx_abort(const struct device *dev)
1008 {
1009 	struct uart_sam0_dev_data *const dev_data = dev->data;
1010 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
1011 
1012 	if (cfg->tx_dma_channel == 0xFFU) {
1013 		return -ENOTSUP;
1014 	}
1015 
1016 	k_work_cancel_delayable(&dev_data->tx_timeout_work);
1017 
1018 	return uart_sam0_tx_halt(dev_data);
1019 }
1020 
uart_sam0_rx_enable(const struct device * dev,uint8_t * buf,size_t len,int32_t timeout)1021 static int uart_sam0_rx_enable(const struct device *dev, uint8_t *buf,
1022 			       size_t len,
1023 			       int32_t timeout)
1024 {
1025 	struct uart_sam0_dev_data *const dev_data = dev->data;
1026 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
1027 	SercomUsart *regs = cfg->regs;
1028 	int retval;
1029 
1030 	if (cfg->rx_dma_channel == 0xFFU) {
1031 		return -ENOTSUP;
1032 	}
1033 
1034 	if (len > 0xFFFFU) {
1035 		return -EINVAL;
1036 	}
1037 
1038 	unsigned int key = irq_lock();
1039 
1040 	if (dev_data->rx_len != 0U) {
1041 		retval = -EBUSY;
1042 		goto err;
1043 	}
1044 
1045 	/* Read off anything that was already there */
1046 	while (regs->INTFLAG.bit.RXC) {
1047 		char discard = regs->DATA.reg;
1048 
1049 		(void)discard;
1050 	}
1051 
1052 	retval = dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
1053 			    (uint32_t)(&(regs->DATA.reg)),
1054 			    (uint32_t)buf, len);
1055 	if (retval != 0) {
1056 		return retval;
1057 	}
1058 
1059 	dev_data->rx_buf = buf;
1060 	dev_data->rx_len = len;
1061 	dev_data->rx_processed_len = 0U;
1062 	dev_data->rx_waiting_for_irq = true;
1063 	dev_data->rx_timeout_from_isr = true;
1064 	dev_data->rx_timeout_time = timeout;
1065 	dev_data->rx_timeout_chunk = MAX(timeout / 4U, 1);
1066 
1067 	regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
1068 
1069 	irq_unlock(key);
1070 	return 0;
1071 
1072 err:
1073 	irq_unlock(key);
1074 	return retval;
1075 }
1076 
uart_sam0_rx_buf_rsp(const struct device * dev,uint8_t * buf,size_t len)1077 static int uart_sam0_rx_buf_rsp(const struct device *dev, uint8_t *buf,
1078 				size_t len)
1079 {
1080 	if (len > 0xFFFFU) {
1081 		return -EINVAL;
1082 	}
1083 
1084 	struct uart_sam0_dev_data *const dev_data = dev->data;
1085 	unsigned int key = irq_lock();
1086 	int retval = 0;
1087 
1088 	if (dev_data->rx_len == 0U) {
1089 		retval = -EACCES;
1090 		goto err;
1091 	}
1092 
1093 	if (dev_data->rx_next_len != 0U) {
1094 		retval = -EBUSY;
1095 		goto err;
1096 	}
1097 
1098 	dev_data->rx_next_buf = buf;
1099 	dev_data->rx_next_len = len;
1100 
1101 	irq_unlock(key);
1102 	return 0;
1103 
1104 err:
1105 	irq_unlock(key);
1106 	return retval;
1107 }
1108 
uart_sam0_rx_disable(const struct device * dev)1109 static int uart_sam0_rx_disable(const struct device *dev)
1110 {
1111 	struct uart_sam0_dev_data *const dev_data = dev->data;
1112 	const struct uart_sam0_dev_cfg *const cfg = dev->config;
1113 	SercomUsart * const regs = cfg->regs;
1114 	struct dma_status st;
1115 
1116 	k_work_cancel_delayable(&dev_data->rx_timeout_work);
1117 
1118 	unsigned int key = irq_lock();
1119 
1120 	if (dev_data->rx_len == 0U) {
1121 		irq_unlock(key);
1122 		return -EINVAL;
1123 	}
1124 
1125 	regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
1126 	dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
1127 
1128 
1129 	if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel,
1130 			   &st) == 0 && st.pending_length != 0U) {
1131 		size_t rx_processed = dev_data->rx_len - st.pending_length;
1132 
1133 		uart_sam0_notify_rx_processed(dev_data, rx_processed);
1134 	}
1135 
1136 	struct uart_event evt = {
1137 		.type = UART_RX_BUF_RELEASED,
1138 		.data.rx_buf = {
1139 			.buf = dev_data->rx_buf,
1140 		},
1141 	};
1142 
1143 	dev_data->rx_buf = NULL;
1144 	dev_data->rx_len = 0U;
1145 
1146 	if (dev_data->async_cb) {
1147 		dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
1148 	}
1149 
1150 	if (dev_data->rx_next_len) {
1151 		struct uart_event next_evt = {
1152 			.type = UART_RX_BUF_RELEASED,
1153 			.data.rx_buf = {
1154 				.buf = dev_data->rx_next_buf,
1155 			},
1156 		};
1157 
1158 		dev_data->rx_next_buf = NULL;
1159 		dev_data->rx_next_len = 0U;
1160 
1161 		if (dev_data->async_cb) {
1162 			dev_data->async_cb(dev, &next_evt, dev_data->async_cb_data);
1163 		}
1164 	}
1165 
1166 	evt.type = UART_RX_DISABLED;
1167 	if (dev_data->async_cb) {
1168 		dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
1169 	}
1170 
1171 	irq_unlock(key);
1172 
1173 	return 0;
1174 }
1175 
1176 #endif
1177 
1178 static DEVICE_API(uart, uart_sam0_driver_api) = {
1179 	.poll_in = uart_sam0_poll_in,
1180 	.poll_out = uart_sam0_poll_out,
1181 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1182 	.configure = uart_sam0_configure,
1183 	.config_get = uart_sam0_config_get,
1184 #endif
1185 	.err_check = uart_sam0_err_check,
1186 #if CONFIG_UART_INTERRUPT_DRIVEN
1187 	.fifo_fill = uart_sam0_fifo_fill,
1188 	.fifo_read = uart_sam0_fifo_read,
1189 	.irq_tx_enable = uart_sam0_irq_tx_enable,
1190 	.irq_tx_disable = uart_sam0_irq_tx_disable,
1191 	.irq_tx_ready = uart_sam0_irq_tx_ready,
1192 	.irq_tx_complete = uart_sam0_irq_tx_complete,
1193 	.irq_rx_enable = uart_sam0_irq_rx_enable,
1194 	.irq_rx_disable = uart_sam0_irq_rx_disable,
1195 	.irq_rx_ready = uart_sam0_irq_rx_ready,
1196 	.irq_is_pending = uart_sam0_irq_is_pending,
1197 #if defined(SERCOM_REV500)
1198 	.irq_err_enable = uart_sam0_irq_err_enable,
1199 	.irq_err_disable = uart_sam0_irq_err_disable,
1200 #endif
1201 	.irq_update = uart_sam0_irq_update,
1202 	.irq_callback_set = uart_sam0_irq_callback_set,
1203 #endif
1204 #if CONFIG_UART_SAM0_ASYNC
1205 	.callback_set = uart_sam0_callback_set,
1206 	.tx = uart_sam0_tx,
1207 	.tx_abort = uart_sam0_tx_abort,
1208 	.rx_enable = uart_sam0_rx_enable,
1209 	.rx_buf_rsp = uart_sam0_rx_buf_rsp,
1210 	.rx_disable = uart_sam0_rx_disable,
1211 #endif
1212 };
1213 
1214 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
1215 
1216 #define SAM0_UART_IRQ_CONNECT(n, m)					\
1217 	do {								\
1218 		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq),		\
1219 			    DT_INST_IRQ_BY_IDX(n, m, priority),		\
1220 			    uart_sam0_isr,				\
1221 			    DEVICE_DT_INST_GET(n), 0);			\
1222 		irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq));		\
1223 	} while (false)
1224 
1225 #define UART_SAM0_IRQ_HANDLER_DECL(n)					\
1226 	static void uart_sam0_irq_config_##n(const struct device *dev)
1227 #define UART_SAM0_IRQ_HANDLER_FUNC(n)					\
1228 	.irq_config_func = uart_sam0_irq_config_##n,
1229 
1230 #if DT_INST_IRQ_HAS_IDX(0, 3)
1231 #define UART_SAM0_IRQ_HANDLER(n)					\
1232 static void uart_sam0_irq_config_##n(const struct device *dev)		\
1233 {									\
1234 	SAM0_UART_IRQ_CONNECT(n, 0);					\
1235 	SAM0_UART_IRQ_CONNECT(n, 1);					\
1236 	SAM0_UART_IRQ_CONNECT(n, 2);					\
1237 	SAM0_UART_IRQ_CONNECT(n, 3);					\
1238 }
1239 #else
1240 #define UART_SAM0_IRQ_HANDLER(n)					\
1241 static void uart_sam0_irq_config_##n(const struct device *dev)		\
1242 {									\
1243 	SAM0_UART_IRQ_CONNECT(n, 0);					\
1244 }
1245 #endif
1246 #else
1247 #define UART_SAM0_IRQ_HANDLER_DECL(n)
1248 #define UART_SAM0_IRQ_HANDLER_FUNC(n)
1249 #define UART_SAM0_IRQ_HANDLER(n)
1250 #endif
1251 
1252 #if CONFIG_UART_SAM0_ASYNC
1253 #define UART_SAM0_DMA_CHANNELS(n)					\
1254 	.dma_dev = DEVICE_DT_GET(ATMEL_SAM0_DT_INST_DMA_CTLR(n, tx)),	\
1255 	.tx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx),	\
1256 	.tx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, tx),	\
1257 	.rx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx),	\
1258 	.rx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
1259 #else
1260 #define UART_SAM0_DMA_CHANNELS(n)
1261 #endif
1262 
1263 #define UART_SAM0_SERCOM_PADS(n) \
1264 	(DT_INST_PROP(n, rxpo) << SERCOM_USART_CTRLA_RXPO_Pos) |	\
1265 	(DT_INST_PROP(n, txpo) << SERCOM_USART_CTRLA_TXPO_Pos)
1266 
1267 #define UART_SAM0_SERCOM_COLLISION_DETECT(n) \
1268 	(DT_INST_PROP(n, collision_detection))
1269 
1270 #define ASSIGNED_CLOCKS_CELL_BY_NAME					\
1271 	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
1272 
1273 #define UART_SAM0_CONFIG_DEFN(n)					\
1274 static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		\
1275 	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
1276 	.baudrate = DT_INST_PROP(n, current_speed),			\
1277 	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
1278 	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
1279 	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
1280 	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
1281 	.pads = UART_SAM0_SERCOM_PADS(n),				\
1282 	.collision_detect = UART_SAM0_SERCOM_COLLISION_DETECT(n),	\
1283 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
1284 	UART_SAM0_IRQ_HANDLER_FUNC(n)					\
1285 	UART_SAM0_DMA_CHANNELS(n)					\
1286 }
1287 
1288 #define UART_SAM0_DEVICE_INIT(n)					\
1289 PINCTRL_DT_INST_DEFINE(n);						\
1290 static struct uart_sam0_dev_data uart_sam0_data_##n;			\
1291 UART_SAM0_IRQ_HANDLER_DECL(n);						\
1292 UART_SAM0_CONFIG_DEFN(n);						\
1293 DEVICE_DT_INST_DEFINE(n, uart_sam0_init, NULL,				\
1294 		    &uart_sam0_data_##n,				\
1295 		    &uart_sam0_config_##n, PRE_KERNEL_1,		\
1296 		    CONFIG_SERIAL_INIT_PRIORITY,			\
1297 		    &uart_sam0_driver_api);				\
1298 UART_SAM0_IRQ_HANDLER(n)
1299 
1300 DT_INST_FOREACH_STATUS_OKAY(UART_SAM0_DEVICE_INIT)
1301 
1302 /* clang-format on */
1303