/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/ |
D | stm32l1xx_hal_pwr.c | 472 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode() 518 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode() 534 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode() 554 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode() 576 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit() 589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit() 602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend() 615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/ |
D | stm32l0xx_hal_pwr.c | 496 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSLEEPMode() 558 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode() 575 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode() 598 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTANDBYMode() 619 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit() 632 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit() 645 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend() 658 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/ |
D | stm32l4xx_hal_pwr.c | 491 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode() 579 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode() 602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit() 615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit() 629 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend() 642 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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D | stm32l4xx_hal_pwr_ex.c | 1184 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode() 1201 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode() 1235 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode() 1252 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode() 1287 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode() 1304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode() 1327 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSHUTDOWNMode()
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D | stm32l4xx_hal_rtc_ex.c | 498 hrtc->Instance->SCR = RTC_SCR_CTSF; in HAL_RTCEx_TamperTimeStampIRQHandler() 505 tamp->SCR = tmp; in HAL_RTCEx_TamperTimeStampIRQHandler() 1012 hrtc->Instance->SCR = RTC_SCR_CWUTF; 2036 tamp->SCR = Tamper;
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D | stm32l4xx_hal_rtc.c | 1692 hrtc->Instance->SCR = RTC_SCR_CALRAF; in HAL_RTC_AlarmIRQHandler() 1705 hrtc->Instance->SCR = RTC_SCR_CALRBF; in HAL_RTC_AlarmIRQHandler()
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/ |
D | stm32l1xx_ll_cortex.h | 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep() 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep() 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit() 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit() 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend() 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/ |
D | stm32l4xx_ll_cortex.h | 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep() 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep() 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit() 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit() 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend() 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
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D | stm32l4xx_ll_pwr.h | 1460 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); in LL_PWR_ClearFlag_SB() 1470 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU() 1480 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5() 1490 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4() 1500 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3() 1510 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2() 1520 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
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D | stm32l4xx_hal_pwr.h | 234 (PWR->SCR = (__FLAG__)) :\ 235 (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
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D | stm32l4xx_ll_rtc.h | 3593 SET_BIT(RTCx->SCR, RTC_SCR_CITSF); in LL_RTC_ClearFlag_ITS() 3604 SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); in LL_RTC_ClearFlag_TSOV() 3615 SET_BIT(RTCx->SCR, RTC_SCR_CTSF); in LL_RTC_ClearFlag_TS() 3626 SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); in LL_RTC_ClearFlag_WUT() 3637 SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); in LL_RTC_ClearFlag_ALRB() 3648 SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); in LL_RTC_ClearFlag_ALRA() 3859 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); in LL_RTC_ClearFlag_TAMP1() 3870 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); in LL_RTC_ClearFlag_TAMP2()
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D | stm32l4xx_hal_rtc.h | 737 …_, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF)… 738 … ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))
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D | stm32l4xx_hal_rtc_ex.h | 557 #define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__)) 1150 …TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) = (__FLAG__))
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/ |
D | stm32l0xx_ll_cortex.h | 318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep() 329 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep() 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit() 353 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit() 365 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend() 377 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
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/loramac-node-3.4.0/src/boards/mcu/saml21/hri/ |
D | hri_systemcontrol_l21.h | 960 ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_set_SCR_SLEEPONEXIT_bit() 967 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_get_SCR_SLEEPONEXIT_bit() 976 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_write_SCR_SLEEPONEXIT_bit() 979 ((Systemcontrol *)hw)->SCR.reg = tmp; in hri_systemcontrol_write_SCR_SLEEPONEXIT_bit() 986 ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit() 993 ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit() 1000 ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP; in hri_systemcontrol_set_SCR_SLEEPDEEP_bit() 1007 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_get_SCR_SLEEPDEEP_bit() 1016 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_write_SCR_SLEEPDEEP_bit() 1019 ((Systemcontrol *)hw)->SCR.reg = tmp; in hri_systemcontrol_write_SCR_SLEEPDEEP_bit() [all …]
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/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/ |
D | core_cm0.h | 340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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D | core_cm0plus.h | 355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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D | core_sc000.h | 346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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D | core_cm3.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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D | core_sc300.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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D | core_cm4.h | 401 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/ |
D | core_cm0.h | 395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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D | core_cm0plus.h | 413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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D | core_sc000.h | 401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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D | core_cm3.h | 423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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