Searched refs:RwReg8 (Results 1 – 25 of 47) sorted by relevance
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178 #define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */180 #define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Servi…185 #define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Addres…192 #define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT …196 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPO…197 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDP…198 #define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDP…199 #define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT …203 #define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPO…204 #define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDP…[all …]
80 #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000014UL) /**< \brief (SERCOM0) I2CM Interrupt E…81 #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000016UL) /**< \brief (SERCOM0) I2CM Interrupt E…82 #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000018UL) /**< \brief (SERCOM0) I2CM Interrupt F…86 #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000028UL) /**< \brief (SERCOM0) I2CM Data */87 #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000030UL) /**< \brief (SERCOM0) I2CM Debug Contr…90 #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000014UL) /**< \brief (SERCOM0) I2CS Interrupt E…91 #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000016UL) /**< \brief (SERCOM0) I2CS Interrupt E…92 #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000018UL) /**< \brief (SERCOM0) I2CS Interrupt F…96 #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000028UL) /**< \brief (SERCOM0) I2CS Data */99 #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200000CUL) /**< \brief (SERCOM0) SPI Baud Rate */[all …]
80 #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM1) I2CM Interrupt E…81 #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM1) I2CM Interrupt E…82 #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM1) I2CM Interrupt F…86 #define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM1) I2CM Data */87 #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM1) I2CM Debug Contr…90 #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM1) I2CS Interrupt E…91 #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM1) I2CS Interrupt E…92 #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM1) I2CS Interrupt F…96 #define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM1) I2CS Data */99 #define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM1) SPI Baud Rate */[all …]
80 #define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM2) I2CM Interrupt E…81 #define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM2) I2CM Interrupt E…82 #define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM2) I2CM Interrupt F…86 #define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM2) I2CM Data */87 #define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM2) I2CM Debug Contr…90 #define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM2) I2CS Interrupt E…91 #define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM2) I2CS Interrupt E…92 #define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM2) I2CS Interrupt F…96 #define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM2) I2CS Data */99 #define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM2) SPI Baud Rate */[all …]
80 #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) I2CM Interrupt E…81 #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) I2CM Interrupt E…82 #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) I2CM Interrupt F…86 #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM3) I2CM Data */87 #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM3) I2CM Debug Contr…90 #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) I2CS Interrupt E…91 #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) I2CS Interrupt E…92 #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) I2CS Interrupt F…96 #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM3) I2CS Data */99 #define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM3) SPI Baud Rate */[all …]
80 #define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM4) I2CM Interrupt E…81 #define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM4) I2CM Interrupt E…82 #define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM4) I2CM Interrupt F…86 #define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM4) I2CM Data */87 #define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM4) I2CM Debug Contr…90 #define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM4) I2CS Interrupt E…91 #define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM4) I2CS Interrupt E…92 #define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM4) I2CS Interrupt F…96 #define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM4) I2CS Data */99 #define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM4) SPI Baud Rate */[all …]
80 #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CM Interrupt E…81 #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CM Interrupt E…82 #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CM Interrupt F…86 #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x43000428UL) /**< \brief (SERCOM5) I2CM Data */87 #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) I2CM Debug Contr…90 #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CS Interrupt E…91 #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CS Interrupt E…92 #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CS Interrupt F…96 #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x43000428UL) /**< \brief (SERCOM5) I2CS Data */99 #define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4300040CUL) /**< \brief (SERCOM5) SPI Baud Rate */[all …]
65 #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */66 #define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */68 #define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Cle…69 #define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set…70 #define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Statu…71 #define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */72 #define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation …73 #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */74 #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */86 #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */[all …]
65 #define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TC1) Control B Clear */66 #define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TC1) Control B Set */68 #define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408UL) /**< \brief (TC1) Interrupt Enable Cle…69 #define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set…70 #define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AUL) /**< \brief (TC1) Interrupt Flag Statu…71 #define REG_TC1_STATUS (*(RwReg8 *)0x4200240BUL) /**< \brief (TC1) Status */72 #define REG_TC1_WAVE (*(RwReg8 *)0x4200240CUL) /**< \brief (TC1) Waveform Generation …73 #define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Control C */74 #define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FUL) /**< \brief (TC1) Debug Control */86 #define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414UL) /**< \brief (TC1) COUNT8 Count */[all …]
65 #define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */66 #define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */68 #define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Interrupt Enable Cle…69 #define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set…70 #define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TC2) Interrupt Flag Statu…71 #define REG_TC2_STATUS (*(RwReg8 *)0x4200280BUL) /**< \brief (TC2) Status */72 #define REG_TC2_WAVE (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Waveform Generation …73 #define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Control C */74 #define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FUL) /**< \brief (TC2) Debug Control */86 #define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Count */[all …]
65 #define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */66 #define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */68 #define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Cle…69 #define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set…70 #define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Statu…71 #define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */72 #define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation …73 #define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */74 #define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */86 #define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */[all …]
65 #define REG_TC4_CTRLBCLR (*(RwReg8 *)0x43000804UL) /**< \brief (TC4) Control B Clear */66 #define REG_TC4_CTRLBSET (*(RwReg8 *)0x43000805UL) /**< \brief (TC4) Control B Set */68 #define REG_TC4_INTENCLR (*(RwReg8 *)0x43000808UL) /**< \brief (TC4) Interrupt Enable Cle…69 #define REG_TC4_INTENSET (*(RwReg8 *)0x43000809UL) /**< \brief (TC4) Interrupt Enable Set…70 #define REG_TC4_INTFLAG (*(RwReg8 *)0x4300080AUL) /**< \brief (TC4) Interrupt Flag Statu…71 #define REG_TC4_STATUS (*(RwReg8 *)0x4300080BUL) /**< \brief (TC4) Status */72 #define REG_TC4_WAVE (*(RwReg8 *)0x4300080CUL) /**< \brief (TC4) Waveform Generation …73 #define REG_TC4_DRVCTRL (*(RwReg8 *)0x4300080DUL) /**< \brief (TC4) Control C */74 #define REG_TC4_DBGCTRL (*(RwReg8 *)0x4300080FUL) /**< \brief (TC4) Debug Control */86 #define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x43000814UL) /**< \brief (TC4) COUNT8 Count */[all …]
91 #define REG_TAL_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (TAL) Control A */92 #define REG_TAL_RSTCTRL (*(RwReg8 *)0x40002C04UL) /**< \brief (TAL) Reset Control */93 #define REG_TAL_EXTCTRL (*(RwReg8 *)0x40002C05UL) /**< \brief (TAL) External Break Contr…94 #define REG_TAL_EVCTRL (*(RwReg8 *)0x40002C06UL) /**< \brief (TAL) Event Control */95 #define REG_TAL_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (TAL) Interrupt Enable Cle…96 #define REG_TAL_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (TAL) Interrupt Enable Set…97 #define REG_TAL_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (TAL) Interrupt Flag Statu…98 #define REG_TAL_GLOBMASK (*(RwReg8 *)0x40002C0BUL) /**< \brief (TAL) Global Break Request…102 #define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40002C10UL) /**< \brief (TAL) Cross-Trigger Interf…103 #define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40002C11UL) /**< \brief (TAL) Cross-Trigger Interf…[all …]
57 #define REG_ADC_CTRLA (*(RwReg8 *)0x43000C00UL) /**< \brief (ADC) Control A */58 #define REG_ADC_CTRLB (*(RwReg8 *)0x43000C01UL) /**< \brief (ADC) Control B */59 #define REG_ADC_REFCTRL (*(RwReg8 *)0x43000C02UL) /**< \brief (ADC) Reference Control */60 #define REG_ADC_EVCTRL (*(RwReg8 *)0x43000C03UL) /**< \brief (ADC) Event Control */61 #define REG_ADC_INTENCLR (*(RwReg8 *)0x43000C04UL) /**< \brief (ADC) Interrupt Enable Cle…62 #define REG_ADC_INTENSET (*(RwReg8 *)0x43000C05UL) /**< \brief (ADC) Interrupt Enable Set…63 #define REG_ADC_INTFLAG (*(RwReg8 *)0x43000C06UL) /**< \brief (ADC) Interrupt Flag Statu…67 #define REG_ADC_AVGCTRL (*(RwReg8 *)0x43000C0CUL) /**< \brief (ADC) Average Control */68 #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x43000C0DUL) /**< \brief (ADC) Sample Time Control …73 #define REG_ADC_SWTRIG (*(RwReg8 *)0x43000C18UL) /**< \brief (ADC) Software Trigger */[all …]
50 #define REG_AC_CTRLA (*(RwReg8 *)0x43001000UL) /**< \brief (AC) Control A */53 #define REG_AC_INTENCLR (*(RwReg8 *)0x43001004UL) /**< \brief (AC) Interrupt Enable Clea…54 #define REG_AC_INTENSET (*(RwReg8 *)0x43001005UL) /**< \brief (AC) Interrupt Enable Set …55 #define REG_AC_INTFLAG (*(RwReg8 *)0x43001006UL) /**< \brief (AC) Interrupt Flag Status…58 #define REG_AC_DBGCTRL (*(RwReg8 *)0x43001009UL) /**< \brief (AC) Debug Control */59 #define REG_AC_WINCTRL (*(RwReg8 *)0x4300100AUL) /**< \brief (AC) Window Control */60 #define REG_AC_SCALER0 (*(RwReg8 *)0x4300100CUL) /**< \brief (AC) Scaler 0 */61 #define REG_AC_SCALER1 (*(RwReg8 *)0x4300100DUL) /**< \brief (AC) Scaler 1 */
43 #define REG_PM_CTRLA (*(RwReg8 *)0x40000000UL) /**< \brief (PM) Control A */44 #define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000001UL) /**< \brief (PM) Sleep Configuration */45 #define REG_PM_PLCFG (*(RwReg8 *)0x40000002UL) /**< \brief (PM) Performance Level Con…46 #define REG_PM_INTENCLR (*(RwReg8 *)0x40000004UL) /**< \brief (PM) Interrupt Enable Clea…47 #define REG_PM_INTENSET (*(RwReg8 *)0x40000005UL) /**< \brief (PM) Interrupt Enable Set …48 #define REG_PM_INTFLAG (*(RwReg8 *)0x40000006UL) /**< \brief (PM) Interrupt Flag Status…50 #define REG_PM_PWSAKDLY (*(RwReg8 *)0x4000000CUL) /**< \brief (PM) Power Switch Acknowle…
62 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4400040CUL) /**< \brief (DMAC) CRC Status */63 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4400040DUL) /**< \brief (DMAC) Debug Control */64 #define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4400040EUL) /**< \brief (DMAC) QOS Control */74 #define REG_DMAC_CHID (*(RwReg8 *)0x4400043FUL) /**< \brief (DMAC) Channel ID */75 #define REG_DMAC_CHCTRLA (*(RwReg8 *)0x44000440UL) /**< \brief (DMAC) Channel Control A */77 #define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4400044CUL) /**< \brief (DMAC) Channel Interrupt E…78 #define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4400044DUL) /**< \brief (DMAC) Channel Interrupt E…79 #define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4400044EUL) /**< \brief (DMAC) Channel Interrupt F…
48 #define REG_MCLK_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (MCLK) Control A */49 #define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000401UL) /**< \brief (MCLK) Interrupt Enable Cl…50 #define REG_MCLK_INTENSET (*(RwReg8 *)0x40000402UL) /**< \brief (MCLK) Interrupt Enable Se…51 #define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000403UL) /**< \brief (MCLK) Interrupt Flag Stat…52 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404UL) /**< \brief (MCLK) CPU Clock Division …53 #define REG_MCLK_LPDIV (*(RwReg8 *)0x40000405UL) /**< \brief (MCLK) Low-Power Clock Div…54 #define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000406UL) /**< \brief (MCLK) Backup Clock Divisi…
50 #define REG_DAC_CTRLA (*(RwReg8 *)0x42003000UL) /**< \brief (DAC) Control A */51 #define REG_DAC_CTRLB (*(RwReg8 *)0x42003001UL) /**< \brief (DAC) Control B */52 #define REG_DAC_EVCTRL (*(RwReg8 *)0x42003002UL) /**< \brief (DAC) Event Control */53 #define REG_DAC_INTENCLR (*(RwReg8 *)0x42003004UL) /**< \brief (DAC) Interrupt Enable Cle…54 #define REG_DAC_INTENSET (*(RwReg8 *)0x42003005UL) /**< \brief (DAC) Interrupt Enable Set…55 #define REG_DAC_INTFLAG (*(RwReg8 *)0x42003006UL) /**< \brief (DAC) Interrupt Flag Statu…64 #define REG_DAC_DBGCTRL (*(RwReg8 *)0x42003018UL) /**< \brief (DAC) Debug Control */
43 #define REG_WDT_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (WDT) Control */44 #define REG_WDT_CONFIG (*(RwReg8 *)0x40001C01UL) /**< \brief (WDT) Configuration */45 #define REG_WDT_EWCTRL (*(RwReg8 *)0x40001C02UL) /**< \brief (WDT) Early Warning Interr…46 #define REG_WDT_INTENCLR (*(RwReg8 *)0x40001C04UL) /**< \brief (WDT) Interrupt Enable Cle…47 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05UL) /**< \brief (WDT) Interrupt Enable Set…48 #define REG_WDT_INTFLAG (*(RwReg8 *)0x40001C06UL) /**< \brief (WDT) Interrupt Flag Statu…
41 #define REG_TRNG_CTRLA (*(RwReg8 *)0x42003800UL) /**< \brief (TRNG) Control A */42 #define REG_TRNG_EVCTRL (*(RwReg8 *)0x42003804UL) /**< \brief (TRNG) Event Control */43 #define REG_TRNG_INTENCLR (*(RwReg8 *)0x42003808UL) /**< \brief (TRNG) Interrupt Enable Cl…44 #define REG_TRNG_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TRNG) Interrupt Enable Se…45 #define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200380AUL) /**< \brief (TRNG) Interrupt Flag Stat…
66 #define REG_AES_CTRLB (*(RwReg8 *)0x42003404UL) /**< \brief (AES) Control B */67 #define REG_AES_INTENCLR (*(RwReg8 *)0x42003405UL) /**< \brief (AES) Interrupt Enable Cle…68 #define REG_AES_INTENSET (*(RwReg8 *)0x42003406UL) /**< \brief (AES) Interrupt Enable Set…69 #define REG_AES_INTFLAG (*(RwReg8 *)0x42003407UL) /**< \brief (AES) Interrupt Flag Statu…70 #define REG_AES_DATABUFPTR (*(RwReg8 *)0x42003408UL) /**< \brief (AES) Data buffer pointer …
56 #define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14UL) /**< \brief (OSCCTRL) 16MHz Internal O…60 #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24UL) /**< \brief (OSCCTRL) DFLL48M Synchron…61 #define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28UL) /**< \brief (OSCCTRL) DPLL Control */64 #define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34UL) /**< \brief (OSCCTRL) DPLL Prescaler */
42 #define REG_CCL_CTRL (*(RwReg8 *)0x43001C00UL) /**< \brief (CCL) Control */43 #define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x43001C04UL) /**< \brief (CCL) SEQ Control x 0 */44 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05UL) /**< \brief (CCL) SEQ Control x 1 */
51 #define REG_PAC_EVCTRL (*(RwReg8 *)0x44000004UL) /**< \brief (PAC) Event control */52 #define REG_PAC_INTENCLR (*(RwReg8 *)0x44000008UL) /**< \brief (PAC) Interrupt enable cle…53 #define REG_PAC_INTENSET (*(RwReg8 *)0x44000009UL) /**< \brief (PAC) Interrupt enable set…
