Searched refs:RwReg (Results 1 – 25 of 46) sorted by relevance
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84 #define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001820UL) /**< \brief (GCLK) Generic Clock Gener…85 #define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001824UL) /**< \brief (GCLK) Generic Clock Gener…86 #define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001828UL) /**< \brief (GCLK) Generic Clock Gener…87 #define REG_GCLK_GENCTRL3 (*(RwReg *)0x4000182CUL) /**< \brief (GCLK) Generic Clock Gener…88 #define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001830UL) /**< \brief (GCLK) Generic Clock Gener…89 #define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001834UL) /**< \brief (GCLK) Generic Clock Gener…90 #define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001838UL) /**< \brief (GCLK) Generic Clock Gener…91 #define REG_GCLK_GENCTRL7 (*(RwReg *)0x4000183CUL) /**< \brief (GCLK) Generic Clock Gener…92 #define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001840UL) /**< \brief (GCLK) Generic Clock Gener…93 #define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001880UL) /**< \brief (GCLK) Peripheral Clock Co…[all …]
100 #define REG_EVSYS_INTENCLR (*(RwReg *)0x43000010UL) /**< \brief (EVSYS) Interrupt Enable C…101 #define REG_EVSYS_INTENSET (*(RwReg *)0x43000014UL) /**< \brief (EVSYS) Interrupt Enable S…102 #define REG_EVSYS_INTFLAG (*(RwReg *)0x43000018UL) /**< \brief (EVSYS) Interrupt Flag Sta…104 #define REG_EVSYS_CHANNEL0 (*(RwReg *)0x43000020UL) /**< \brief (EVSYS) Channel 0 */105 #define REG_EVSYS_CHANNEL1 (*(RwReg *)0x43000024UL) /**< \brief (EVSYS) Channel 1 */106 #define REG_EVSYS_CHANNEL2 (*(RwReg *)0x43000028UL) /**< \brief (EVSYS) Channel 2 */107 #define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4300002CUL) /**< \brief (EVSYS) Channel 3 */108 #define REG_EVSYS_CHANNEL4 (*(RwReg *)0x43000030UL) /**< \brief (EVSYS) Channel 4 */109 #define REG_EVSYS_CHANNEL5 (*(RwReg *)0x43000034UL) /**< \brief (EVSYS) Channel 5 */110 #define REG_EVSYS_CHANNEL6 (*(RwReg *)0x43000038UL) /**< \brief (EVSYS) Channel 6 */[all …]
63 #define REG_PORT_DIR0 (*(RwReg *)0x40002800UL) /**< \brief (PORT) Data Direction 0 */64 #define REG_PORT_DIRCLR0 (*(RwReg *)0x40002804UL) /**< \brief (PORT) Data Direction Clea…65 #define REG_PORT_DIRSET0 (*(RwReg *)0x40002808UL) /**< \brief (PORT) Data Direction Set …66 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4000280CUL) /**< \brief (PORT) Data Direction Togg…67 #define REG_PORT_OUT0 (*(RwReg *)0x40002810UL) /**< \brief (PORT) Data Output Value 0…68 #define REG_PORT_OUTCLR0 (*(RwReg *)0x40002814UL) /**< \brief (PORT) Data Output Value C…69 #define REG_PORT_OUTSET0 (*(RwReg *)0x40002818UL) /**< \brief (PORT) Data Output Value S…70 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4000281CUL) /**< \brief (PORT) Data Output Value T…72 #define REG_PORT_CTRL0 (*(RwReg *)0x40002824UL) /**< \brief (PORT) Control 0 */74 #define REG_PORT_EVCTRL0 (*(RwReg *)0x4000282CUL) /**< \brief (PORT) Event Input Control…[all …]
63 #define REG_TCC0_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (TCC0) Control A */67 #define REG_TCC0_FCTRLA (*(RwReg *)0x4200140CUL) /**< \brief (TCC0) Recoverable Fault A…68 #define REG_TCC0_FCTRLB (*(RwReg *)0x42001410UL) /**< \brief (TCC0) Recoverable Fault B…69 #define REG_TCC0_WEXCTRL (*(RwReg *)0x42001414UL) /**< \brief (TCC0) Waveform Extension …70 #define REG_TCC0_DRVCTRL (*(RwReg *)0x42001418UL) /**< \brief (TCC0) Driver Control */72 #define REG_TCC0_EVCTRL (*(RwReg *)0x42001420UL) /**< \brief (TCC0) Event Control */73 #define REG_TCC0_INTENCLR (*(RwReg *)0x42001424UL) /**< \brief (TCC0) Interrupt Enable Cl…74 #define REG_TCC0_INTENSET (*(RwReg *)0x42001428UL) /**< \brief (TCC0) Interrupt Enable Se…75 #define REG_TCC0_INTFLAG (*(RwReg *)0x4200142CUL) /**< \brief (TCC0) Interrupt Flag Stat…76 #define REG_TCC0_STATUS (*(RwReg *)0x42001430UL) /**< \brief (TCC0) Status */[all …]
56 #define REG_TCC2_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC2) Control A */60 #define REG_TCC2_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC2) Recoverable Fault A…61 #define REG_TCC2_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC2) Recoverable Fault B…62 #define REG_TCC2_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC2) Driver Control */64 #define REG_TCC2_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC2) Event Control */65 #define REG_TCC2_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC2) Interrupt Enable Cl…66 #define REG_TCC2_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC2) Interrupt Enable Se…67 #define REG_TCC2_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC2) Interrupt Flag Stat…68 #define REG_TCC2_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC2) Status */69 #define REG_TCC2_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC2) Count */[all …]
58 #define REG_TCC1_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (TCC1) Control A */62 #define REG_TCC1_FCTRLA (*(RwReg *)0x4200180CUL) /**< \brief (TCC1) Recoverable Fault A…63 #define REG_TCC1_FCTRLB (*(RwReg *)0x42001810UL) /**< \brief (TCC1) Recoverable Fault B…64 #define REG_TCC1_DRVCTRL (*(RwReg *)0x42001818UL) /**< \brief (TCC1) Driver Control */66 #define REG_TCC1_EVCTRL (*(RwReg *)0x42001820UL) /**< \brief (TCC1) Event Control */67 #define REG_TCC1_INTENCLR (*(RwReg *)0x42001824UL) /**< \brief (TCC1) Interrupt Enable Cl…68 #define REG_TCC1_INTENSET (*(RwReg *)0x42001828UL) /**< \brief (TCC1) Interrupt Enable Se…69 #define REG_TCC1_INTFLAG (*(RwReg *)0x4200182CUL) /**< \brief (TCC1) Interrupt Flag Stat…70 #define REG_TCC1_STATUS (*(RwReg *)0x42001830UL) /**< \brief (TCC1) Status */71 #define REG_TCC1_COUNT (*(RwReg *)0x42001834UL) /**< \brief (TCC1) Count */[all …]
65 #define REG_AES_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (AES) Control A */80 #define REG_AES_INDATA (*(RwReg *)0x42003438UL) /**< \brief (AES) Indata */85 #define REG_AES_HASHKEY0 (*(RwReg *)0x4200345CUL) /**< \brief (AES) Hash key 0 */86 #define REG_AES_HASHKEY1 (*(RwReg *)0x42003460UL) /**< \brief (AES) Hash key 1 */87 #define REG_AES_HASHKEY2 (*(RwReg *)0x42003464UL) /**< \brief (AES) Hash key 2 */88 #define REG_AES_HASHKEY3 (*(RwReg *)0x42003468UL) /**< \brief (AES) Hash key 3 */89 #define REG_AES_GHASH0 (*(RwReg *)0x4200346CUL) /**< \brief (AES) Galois Hash 0 */90 #define REG_AES_GHASH1 (*(RwReg *)0x42003470UL) /**< \brief (AES) Galois Hash 1 */91 #define REG_AES_GHASH2 (*(RwReg *)0x42003474UL) /**< \brief (AES) Galois Hash 2 */92 #define REG_AES_GHASH3 (*(RwReg *)0x42003478UL) /**< \brief (AES) Galois Hash 3 */[all …]
70 #define REG_RTC_GP0 (*(RwReg *)0x40002040UL) /**< \brief (RTC) General Purpose 0 */71 #define REG_RTC_GP1 (*(RwReg *)0x40002044UL) /**< \brief (RTC) General Purpose 1 */72 #define REG_RTC_GP2 (*(RwReg *)0x40002048UL) /**< \brief (RTC) General Purpose 2 */73 #define REG_RTC_GP3 (*(RwReg *)0x4000204CUL) /**< \brief (RTC) General Purpose 3 */75 #define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE0 Event Control …80 #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002018UL) /**< \brief (RTC) MODE0 Counter Value …81 #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002020UL) /**< \brief (RTC) MODE0 Compare 0 Valu…83 #define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE1 Event Control …93 #define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE2 Event Control …98 #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002018UL) /**< \brief (RTC) MODE2 Clock Value */[all …]
77 #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000000UL) /**< \brief (SERCOM0) I2CM Control A */78 #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000004UL) /**< \brief (SERCOM0) I2CM Control B */79 #define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200000CUL) /**< \brief (SERCOM0) I2CM Baud Rate */85 #define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000024UL) /**< \brief (SERCOM0) I2CM Address */88 #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000000UL) /**< \brief (SERCOM0) I2CS Control A */89 #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000004UL) /**< \brief (SERCOM0) I2CS Control B */95 #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000024UL) /**< \brief (SERCOM0) I2CS Address */97 #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000000UL) /**< \brief (SERCOM0) SPI Control A */98 #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000004UL) /**< \brief (SERCOM0) SPI Control B */105 #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000024UL) /**< \brief (SERCOM0) SPI Address */[all …]
77 #define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM1) I2CM Control A */78 #define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM1) I2CM Control B */79 #define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM1) I2CM Baud Rate */85 #define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM1) I2CM Address */88 #define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM1) I2CS Control A */89 #define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM1) I2CS Control B */95 #define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM1) I2CS Address */97 #define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM1) SPI Control A */98 #define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM1) SPI Control B */105 #define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM1) SPI Address */[all …]
77 #define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM2) I2CM Control A */78 #define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM2) I2CM Control B */79 #define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM2) I2CM Baud Rate */85 #define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM2) I2CM Address */88 #define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM2) I2CS Control A */89 #define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM2) I2CS Control B */95 #define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM2) I2CS Address */97 #define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM2) SPI Control A */98 #define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM2) SPI Control B */105 #define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM2) SPI Address */[all …]
77 #define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) I2CM Control A */78 #define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) I2CM Control B */79 #define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM3) I2CM Baud Rate */85 #define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) I2CM Address */88 #define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) I2CS Control A */89 #define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) I2CS Control B */95 #define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) I2CS Address */97 #define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) SPI Control A */98 #define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) SPI Control B */105 #define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) SPI Address */[all …]
77 #define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM4) I2CM Control A */78 #define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM4) I2CM Control B */79 #define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM4) I2CM Baud Rate */85 #define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM4) I2CM Address */88 #define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM4) I2CS Control A */89 #define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM4) I2CS Control B */95 #define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM4) I2CS Address */97 #define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM4) SPI Control A */98 #define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM4) SPI Control B */105 #define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM4) SPI Address */[all …]
77 #define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CM Control A */78 #define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CM Control B */79 #define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4300040CUL) /**< \brief (SERCOM5) I2CM Baud Rate */85 #define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CM Address */88 #define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) I2CS Control A */89 #define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) I2CS Control B */95 #define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) I2CS Address */97 #define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x43000400UL) /**< \brief (SERCOM5) SPI Control A */98 #define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x43000404UL) /**< \brief (SERCOM5) SPI Control B */105 #define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x43000424UL) /**< \brief (SERCOM5) SPI Address */[all …]
46 #define REG_SUPC_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (SUPC) Interrupt Enable Cl…47 #define REG_SUPC_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (SUPC) Interrupt Enable Se…48 #define REG_SUPC_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (SUPC) Interrupt Flag Stat…50 #define REG_SUPC_BOD33 (*(RwReg *)0x40001410UL) /**< \brief (SUPC) BOD33 Control */51 #define REG_SUPC_BOD12 (*(RwReg *)0x40001414UL) /**< \brief (SUPC) BOD12 Control */52 #define REG_SUPC_VREG (*(RwReg *)0x40001418UL) /**< \brief (SUPC) VREG Control */53 #define REG_SUPC_VREF (*(RwReg *)0x4000141CUL) /**< \brief (SUPC) VREF Control */54 #define REG_SUPC_BBPS (*(RwReg *)0x40001420UL) /**< \brief (SUPC) Battery Backup Powe…55 #define REG_SUPC_BKOUT (*(RwReg *)0x40001424UL) /**< \brief (SUPC) Backup Output Contr…
43 #define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSC32KCTRL) Interrupt Ena…44 #define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSC32KCTRL) Interrupt Ena…45 #define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSC32KCTRL) Interrupt Fla…47 #define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001010UL) /**< \brief (OSC32KCTRL) Clock selecti…48 #define REG_OSC32KCTRL_XOSC32K (*(RwReg *)0x40001014UL) /**< \brief (OSC32KCTRL) 32kHz Externa…49 #define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001018UL) /**< \brief (OSC32KCTRL) 32kHz Interna…50 #define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000101CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra L…
50 #define REG_EIC_EVCTRL (*(RwReg *)0x40002408UL) /**< \brief (EIC) Event Control */51 #define REG_EIC_INTENCLR (*(RwReg *)0x4000240CUL) /**< \brief (EIC) Interrupt Enable Cle…52 #define REG_EIC_INTENSET (*(RwReg *)0x40002410UL) /**< \brief (EIC) Interrupt Enable Set…53 #define REG_EIC_INTFLAG (*(RwReg *)0x40002414UL) /**< \brief (EIC) Interrupt Flag Statu…54 #define REG_EIC_ASYNCH (*(RwReg *)0x40002418UL) /**< \brief (EIC) EIC Asynchronous edg…55 #define REG_EIC_CONFIG0 (*(RwReg *)0x4000241CUL) /**< \brief (EIC) Configuration 0 */56 #define REG_EIC_CONFIG1 (*(RwReg *)0x40002420UL) /**< \brief (EIC) Configuration 1 */
50 #define REG_PAC_WRCTRL (*(RwReg *)0x44000000UL) /**< \brief (PAC) Write control */54 #define REG_PAC_INTFLAGAHB (*(RwReg *)0x44000010UL) /**< \brief (PAC) Bridge interrupt fla…55 #define REG_PAC_INTFLAGA (*(RwReg *)0x44000014UL) /**< \brief (PAC) Peripheral interrupt…56 #define REG_PAC_INTFLAGB (*(RwReg *)0x44000018UL) /**< \brief (PAC) Peripheral interrupt…57 #define REG_PAC_INTFLAGC (*(RwReg *)0x4400001CUL) /**< \brief (PAC) Peripheral interrupt…58 #define REG_PAC_INTFLAGD (*(RwReg *)0x44000020UL) /**< \brief (PAC) Peripheral interrupt…59 #define REG_PAC_INTFLAGE (*(RwReg *)0x44000024UL) /**< \brief (PAC) Peripheral interrupt…
51 #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00UL) /**< \brief (OSCCTRL) Interrupt Enable…52 #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04UL) /**< \brief (OSCCTRL) Interrupt Enable…53 #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08UL) /**< \brief (OSCCTRL) Interrupt Flag S…58 #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CUL) /**< \brief (OSCCTRL) DFLL48M Value */59 #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20UL) /**< \brief (OSCCTRL) DFLL48M Multipli…62 #define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CUL) /**< \brief (OSCCTRL) DPLL Ratio Contr…63 #define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30UL) /**< \brief (OSCCTRL) Digital Core Con…
60 #define REG_MTB_POSITION (*(RwReg *)0x41006000UL) /**< \brief (MTB) MTB Position */61 #define REG_MTB_MASTER (*(RwReg *)0x41006004UL) /**< \brief (MTB) MTB Master */62 #define REG_MTB_FLOW (*(RwReg *)0x41006008UL) /**< \brief (MTB) MTB Flow */64 #define REG_MTB_ITCTRL (*(RwReg *)0x41006F00UL) /**< \brief (MTB) MTB Integration Mode…65 #define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0UL) /**< \brief (MTB) MTB Claim Set */66 #define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4UL) /**< \brief (MTB) MTB Claim Clear */67 #define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0UL) /**< \brief (MTB) MTB Lock Access */
60 #define REG_DMAC_CRCDATAIN (*(RwReg *)0x44000404UL) /**< \brief (DMAC) CRC Data Input */61 #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x44000408UL) /**< \brief (DMAC) CRC Checksum */65 #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x44000410UL) /**< \brief (DMAC) Software Trigger Co…66 #define REG_DMAC_PRICTRL0 (*(RwReg *)0x44000414UL) /**< \brief (DMAC) Priority Control 0 …72 #define REG_DMAC_BASEADDR (*(RwReg *)0x44000434UL) /**< \brief (DMAC) Descriptor Memory S…73 #define REG_DMAC_WRBADDR (*(RwReg *)0x44000438UL) /**< \brief (DMAC) Write-Back Memory S…76 #define REG_DMAC_CHCTRLB (*(RwReg *)0x44000444UL) /**< \brief (DMAC) Channel Control B */
65 #define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */66 #define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */67 #define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */68 #define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication …69 #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication …71 #define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration…72 #define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration…
55 #define REG_MCLK_AHBMASK (*(RwReg *)0x40000410UL) /**< \brief (MCLK) AHB Mask */56 #define REG_MCLK_APBAMASK (*(RwReg *)0x40000414UL) /**< \brief (MCLK) APBA Mask */57 #define REG_MCLK_APBBMASK (*(RwReg *)0x40000418UL) /**< \brief (MCLK) APBB Mask */58 #define REG_MCLK_APBCMASK (*(RwReg *)0x4000041CUL) /**< \brief (MCLK) APBC Mask */59 #define REG_MCLK_APBDMASK (*(RwReg *)0x40000420UL) /**< \brief (MCLK) APBD Mask */60 #define REG_MCLK_APBEMASK (*(RwReg *)0x40000424UL) /**< \brief (MCLK) APBE Mask */
64 #define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */81 #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */82 #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and …83 #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and …84 #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and …85 #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and …
64 #define REG_TC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TC1) Control A */81 #define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414UL) /**< \brief (TC1) COUNT32 Count */82 #define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CUL) /**< \brief (TC1) COUNT32 Compare and …83 #define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420UL) /**< \brief (TC1) COUNT32 Compare and …84 #define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430UL) /**< \brief (TC1) COUNT32 Compare and …85 #define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434UL) /**< \brief (TC1) COUNT32 Compare and …
