Searched refs:RoReg8 (Results 1 – 25 of 47) sorted by relevance
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110 #define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40002C20UL) /**< \brief (TAL) Interrupt 0 Status */111 #define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40002C21UL) /**< \brief (TAL) Interrupt 1 Status */112 #define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40002C22UL) /**< \brief (TAL) Interrupt 2 Status */113 #define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40002C23UL) /**< \brief (TAL) Interrupt 3 Status */114 #define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40002C24UL) /**< \brief (TAL) Interrupt 4 Status */115 #define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40002C25UL) /**< \brief (TAL) Interrupt 5 Status */116 #define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40002C26UL) /**< \brief (TAL) Interrupt 6 Status */117 #define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40002C27UL) /**< \brief (TAL) Interrupt 7 Status */118 #define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40002C28UL) /**< \brief (TAL) Interrupt 8 Status */119 #define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40002C29UL) /**< \brief (TAL) Interrupt 9 Status */[all …]
179 #define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy…181 #define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine…186 #define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */195 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOI…202 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOI…209 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOI…216 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOI…223 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOI…230 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOI…237 #define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOI…[all …]
41 #define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000800UL) /**< \brief (RSTC) Reset Cause */42 #define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000802UL) /**< \brief (RSTC) Backup Exit Source …
56 #define REG_AC_STATUSA (*(RoReg8 *)0x43001007UL) /**< \brief (AC) Status A */57 #define REG_AC_STATUSB (*(RoReg8 *)0x43001008UL) /**< \brief (AC) Status B */
65 #define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38UL) /**< \brief (OSCCTRL) DPLL Synchroniza…66 #define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CUL) /**< \brief (OSCCTRL) DPLL Status */
41 #define REG_OPAMP_STATUS (*(RoReg8 *)0x43001802UL) /**< \brief (OPAMP) Status */
56 #define REG_DAC_STATUS (*(RoReg8 *)0x42003007UL) /**< \brief (DAC) Status */
1347 RoReg8 Reserved1[0x4];1349 RoReg8 Reserved2[0x4];1351 RoReg8 Reserved3[0x1];1353 RoReg8 Reserved4[0x1];1355 RoReg8 Reserved5[0x1];1358 RoReg8 Reserved6[0x4];1361 RoReg8 Reserved7[0x7];1371 RoReg8 Reserved1[0xC];1373 RoReg8 Reserved2[0x1];1375 RoReg8 Reserved3[0x1];[all …]
192 RoReg8 Reserved1[0x1];194 RoReg8 Reserved2[0x1];196 RoReg8 Reserved3[0x3];198 RoReg8 Reserved4[0x2];200 RoReg8 Reserved5[0x2];
1640 RoReg8 Reserved1[0x5];1651 RoReg8 Reserved1[0x1];1661 RoReg8 Reserved1[0x3];1668 RoReg8 Reserved2[0x16];1676 RoReg8 Reserved1[0x2];1684 RoReg8 Reserved2[0x16];1692 RoReg8 Reserved1[0x1];1695 RoReg8 Reserved2[0x4];1698 RoReg8 Reserved3[0x1];1701 RoReg8 Reserved4[0x2];[all …]
158 RoReg8 Reserved1[0x3];160 RoReg8 Reserved2[0x3];164 RoReg8 Reserved3[0x15];
1331 RoReg8 Reserved1[0x3];1339 RoReg8 Reserved1[0x2];1345 RoReg8 Reserved2[0x1];1348 RoReg8 Reserved3[0x3];1350 RoReg8 Reserved4[0x4];1352 RoReg8 Reserved5[0x1C];1361 RoReg8 Reserved1[0x2];1367 RoReg8 Reserved2[0x1];1370 RoReg8 Reserved3[0x3];1372 RoReg8 Reserved4[0x2];[all …]
351 RoReg8 Reserved1[0xEF0];353 RoReg8 Reserved2[0x9C];356 RoReg8 Reserved3[0x8];361 RoReg8 Reserved4[0x8];
308 RoReg8 Reserved1[0x2];310 RoReg8 Reserved2[0xC];313 RoReg8 Reserved3[0x10];316 RoReg8 Reserved4[0x4];
757 RoReg8 Reserved1[0x1];761 RoReg8 Reserved2[0x6];764 RoReg8 Reserved3[0x11];783 RoReg8 Reserved1[0x1];787 RoReg8 Reserved2[0x6];789 RoReg8 Reserved3[0x10];807 RoReg8 Reserved1[0x1];811 RoReg8 Reserved2[0x4];813 RoReg8 Reserved3[0xC];
611 RoReg8 Reserved1[0x2];613 RoReg8 Reserved2[0x3];615 RoReg8 Reserved3[0x2];619 RoReg8 Reserved4[0x3];621 RoReg8 Reserved5[0x3];625 RoReg8 Reserved6[0x3];627 RoReg8 Reserved7[0x3];
237 RoReg8 Reserved1[0x3];239 RoReg8 Reserved2[0x18];241 RoReg8 Reserved3[0x3C];
263 RoReg8 Reserved1[0x1];267 RoReg8 Reserved2[0x1];269 RoReg8 Reserved3[0x2];
854 RoReg8 Reserved1[0x3];858 RoReg8 Reserved2[0x1];867 RoReg8 Reserved3[0x8];869 RoReg8 Reserved4[0x3];871 RoReg8 Reserved5[0x4];873 RoReg8 Reserved6[0x4];875 RoReg8 Reserved7[0x4];879 RoReg8 Reserved8[0x2];
334 RoReg8 Reserved1[0x2];338 RoReg8 Reserved2[0x3];340 RoReg8 Reserved3[0x3];342 RoReg8 Reserved4[0x3];344 RoReg8 Reserved5[0x2];
159 RoReg8 Reserved1[0x1];161 RoReg8 Reserved2[0x1];
178 RoReg8 Reserved1[0x3];180 RoReg8 Reserved2[0x2];
711 RoReg8 Reserved1[0x2];713 RoReg8 Reserved2[0x3];715 RoReg8 Reserved3[0x3];717 RoReg8 Reserved4[0x2];719 RoReg8 Reserved5[0x2];
582 RoReg8 Reserved1[0x1];588 RoReg8 Reserved2[0xD4];590 RoReg8 Reserved3[0xF08];593 RoReg8 Reserved4[0xFC0];
1072 RoReg8 Reserved1[0x1];1075 RoReg8 Reserved2[0x8];1077 RoReg8 Reserved3[0x2];1084 RoReg8 Reserved4[0x3];1087 RoReg8 Reserved5[0x3];1089 RoReg8 Reserved6[0x4];
