Searched refs:RoReg (Results 1 – 25 of 42) sorted by relevance
12
63 #define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */68 #define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */69 #define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication S…70 #define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architect…71 #define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configura…72 #define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */73 #define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) Peripheral Identific…74 #define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) Peripheral Identific…75 #define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) Peripheral Identific…76 #define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) Peripheral Identific…[all …]
70 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identificatio…73 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table …74 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table …75 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table …76 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table …77 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identific…78 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identific…79 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identific…80 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identific…81 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identific…[all …]
60 #define REG_PAC_STATUSA (*(RoReg *)0x44000034UL) /**< \brief (PAC) Peripheral write pro…61 #define REG_PAC_STATUSB (*(RoReg *)0x44000038UL) /**< \brief (PAC) Peripheral write pro…62 #define REG_PAC_STATUSC (*(RoReg *)0x4400003CUL) /**< \brief (PAC) Peripheral write pro…63 #define REG_PAC_STATUSD (*(RoReg *)0x44000040UL) /**< \brief (PAC) Peripheral write pro…64 #define REG_PAC_STATUSE (*(RoReg *)0x44000044UL) /**< \brief (PAC) Peripheral write pro…
68 #define REG_DMAC_INTSTATUS (*(RoReg *)0x44000424UL) /**< \brief (DMAC) Interrupt Status */69 #define REG_DMAC_BUSYCH (*(RoReg *)0x44000428UL) /**< \brief (DMAC) Busy Channels */70 #define REG_DMAC_PENDCH (*(RoReg *)0x4400042CUL) /**< \brief (DMAC) Pending Channels */71 #define REG_DMAC_ACTIVE (*(RoReg *)0x44000430UL) /**< \brief (DMAC) Active Channel and …
84 #define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200001CUL) /**< \brief (SERCOM0) I2CM Synchroniza…94 #define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200001CUL) /**< \brief (SERCOM0) I2CS Synchroniza…104 #define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200001CUL) /**< \brief (SERCOM0) SPI Synchronizat…116 #define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200001CUL) /**< \brief (SERCOM0) USART Synchroniz…
84 #define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM1) I2CM Synchroniza…94 #define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM1) I2CS Synchroniza…104 #define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM1) SPI Synchronizat…116 #define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM1) USART Synchroniz…
84 #define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM2) I2CM Synchroniza…94 #define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM2) I2CS Synchroniza…104 #define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM2) SPI Synchronizat…116 #define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM2) USART Synchroniz…
84 #define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) I2CM Synchroniza…94 #define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) I2CS Synchroniza…104 #define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) SPI Synchronizat…116 #define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) USART Synchroniz…
84 #define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM4) I2CM Synchroniza…94 #define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM4) I2CS Synchroniza…104 #define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM4) SPI Synchronizat…116 #define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM4) USART Synchroniz…
84 #define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CM Synchroniza…94 #define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) I2CS Synchroniza…104 #define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) SPI Synchronizat…116 #define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4300041CUL) /**< \brief (SERCOM5) USART Synchroniz…
79 #define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE0 Synchronizatio…87 #define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE1 Synchronizatio…97 #define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE2 Synchronizatio…
49 #define REG_SUPC_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (SUPC) Power and Clocks St…56 #define REG_SUPC_BKIN (*(RoReg *)0x40001428UL) /**< \brief (SUPC) Backup Input Contro…
71 #define REG_PORT_IN0 (*(RoReg *)0x40002820UL) /**< \brief (PORT) Data Input Value 0 …85 #define REG_PORT_IN1 (*(RoReg *)0x400028A0UL) /**< \brief (PORT) Data Input Value 1 …
145 #define REG_TAL_CPUIRQS0 (*(RoReg *)0x40002C64UL) /**< \brief (TAL) Interrupt Status for…146 #define REG_TAL_CPUIRQS1 (*(RoReg *)0x40002C68UL) /**< \brief (TAL) Interrupt Status for…
46 #define REG_TRNG_DATA (*(RoReg *)0x42003820UL) /**< \brief (TRNG) Output Data */
49 #define REG_WDT_SYNCBUSY (*(RoReg *)0x40001C08UL) /**< \brief (WDT) Synchronization Busy…
46 #define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSC32KCTRL) Power and Clo…
49 #define REG_EIC_SYNCBUSY (*(RoReg *)0x40002404UL) /**< \brief (EIC) Syncbusy register */
64 #define REG_AC_SYNCBUSY (*(RoReg *)0x43001020UL) /**< \brief (AC) Synchronization Busy …
57 #define REG_DAC_SYNCBUSY (*(RoReg *)0x42003008UL) /**< \brief (DAC) Synchronization Busy…
54 #define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CUL) /**< \brief (OSCCTRL) Power and Clocks…
59 #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC2) Synchronization Bus…
61 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x42001808UL) /**< \brief (TCC1) Synchronization Bus…
75 #define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Stat…
75 #define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410UL) /**< \brief (TC1) Synchronization Stat…
