1 /** 2 * \file 3 * 4 * \brief Component description for RSTC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_RSTC_COMPONENT_ 30 #define _SAML21_RSTC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR RSTC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_RSTC Reset Controller */ 36 /*@{*/ 37 38 #define RSTC_U2239 39 #define REV_RSTC 0x110 40 41 /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t POR:1; /*!< bit: 0 Power On Reset */ 46 uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ 47 uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ 48 uint8_t :1; /*!< bit: 3 Reserved */ 49 uint8_t EXT:1; /*!< bit: 4 External Reset */ 50 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ 51 uint8_t SYST:1; /*!< bit: 6 System Reset Request */ 52 uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */ 53 } bit; /*!< Structure used for bit access */ 54 uint8_t reg; /*!< Type used for register access */ 55 } RSTC_RCAUSE_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ 59 60 #define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ 61 #define RSTC_RCAUSE_POR (_U(0x1) << RSTC_RCAUSE_POR_Pos) 62 #define RSTC_RCAUSE_BOD12_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out 12 Detector Reset */ 63 #define RSTC_RCAUSE_BOD12 (_U(0x1) << RSTC_RCAUSE_BOD12_Pos) 64 #define RSTC_RCAUSE_BOD33_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out 33 Detector Reset */ 65 #define RSTC_RCAUSE_BOD33 (_U(0x1) << RSTC_RCAUSE_BOD33_Pos) 66 #define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ 67 #define RSTC_RCAUSE_EXT (_U(0x1) << RSTC_RCAUSE_EXT_Pos) 68 #define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ 69 #define RSTC_RCAUSE_WDT (_U(0x1) << RSTC_RCAUSE_WDT_Pos) 70 #define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ 71 #define RSTC_RCAUSE_SYST (_U(0x1) << RSTC_RCAUSE_SYST_Pos) 72 #define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */ 73 #define RSTC_RCAUSE_BACKUP (_U(0x1) << RSTC_RCAUSE_BACKUP_Pos) 74 #define RSTC_RCAUSE_MASK _U(0xF7) /**< \brief (RSTC_RCAUSE) MASK Register */ 75 76 /* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint8_t EXTWAKE:1; /*!< bit: 0 External Wakeup */ 81 uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */ 82 uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */ 83 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 84 } bit; /*!< Structure used for bit access */ 85 uint8_t reg; /*!< Type used for register access */ 86 } RSTC_BKUPEXIT_Type; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 #define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */ 90 91 #define RSTC_BKUPEXIT_EXTWAKE_Pos 0 /**< \brief (RSTC_BKUPEXIT) External Wakeup */ 92 #define RSTC_BKUPEXIT_EXTWAKE (_U(0x1) << RSTC_BKUPEXIT_EXTWAKE_Pos) 93 #define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */ 94 #define RSTC_BKUPEXIT_RTC (_U(0x1) << RSTC_BKUPEXIT_RTC_Pos) 95 #define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */ 96 #define RSTC_BKUPEXIT_BBPS (_U(0x1) << RSTC_BKUPEXIT_BBPS_Pos) 97 #define RSTC_BKUPEXIT_MASK _U(0x07) /**< \brief (RSTC_BKUPEXIT) MASK Register */ 98 99 /* -------- RSTC_WKDBCONF : (RSTC Offset: 0x04) (R/W 8) Wakeup Debounce Configuration -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint8_t WKDBCNT:5; /*!< bit: 0.. 4 Wakeup Debounce Counter */ 104 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 105 } bit; /*!< Structure used for bit access */ 106 uint8_t reg; /*!< Type used for register access */ 107 } RSTC_WKDBCONF_Type; 108 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 109 110 #define RSTC_WKDBCONF_OFFSET 0x04 /**< \brief (RSTC_WKDBCONF offset) Wakeup Debounce Configuration */ 111 #define RSTC_WKDBCONF_RESETVALUE _U(0x00) /**< \brief (RSTC_WKDBCONF reset_value) Wakeup Debounce Configuration */ 112 113 #define RSTC_WKDBCONF_WKDBCNT_Pos 0 /**< \brief (RSTC_WKDBCONF) Wakeup Debounce Counter */ 114 #define RSTC_WKDBCONF_WKDBCNT_Msk (_U(0x1F) << RSTC_WKDBCONF_WKDBCNT_Pos) 115 #define RSTC_WKDBCONF_WKDBCNT(value) (RSTC_WKDBCONF_WKDBCNT_Msk & ((value) << RSTC_WKDBCONF_WKDBCNT_Pos)) 116 #define RSTC_WKDBCONF_WKDBCNT_OFF_Val _U(0x0) /**< \brief (RSTC_WKDBCONF) No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. */ 117 #define RSTC_WKDBCONF_WKDBCNT_2CK32_Val _U(0x1) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least two 32kHz clock period. */ 118 #define RSTC_WKDBCONF_WKDBCNT_3CK32_Val _U(0x2) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least three 32kHz clock period. */ 119 #define RSTC_WKDBCONF_WKDBCNT_32CK32_Val _U(0x3) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32 32kHz clock period. */ 120 #define RSTC_WKDBCONF_WKDBCNT_512CK32_Val _U(0x4) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 512 32kHz clock period. */ 121 #define RSTC_WKDBCONF_WKDBCNT_4096CK32_Val _U(0x5) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 4096 32kHz clock period. */ 122 #define RSTC_WKDBCONF_WKDBCNT_32768CK32_Val _U(0x6) /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32768 32kHz clock period. */ 123 #define RSTC_WKDBCONF_WKDBCNT_OFF (RSTC_WKDBCONF_WKDBCNT_OFF_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 124 #define RSTC_WKDBCONF_WKDBCNT_2CK32 (RSTC_WKDBCONF_WKDBCNT_2CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 125 #define RSTC_WKDBCONF_WKDBCNT_3CK32 (RSTC_WKDBCONF_WKDBCNT_3CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 126 #define RSTC_WKDBCONF_WKDBCNT_32CK32 (RSTC_WKDBCONF_WKDBCNT_32CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 127 #define RSTC_WKDBCONF_WKDBCNT_512CK32 (RSTC_WKDBCONF_WKDBCNT_512CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 128 #define RSTC_WKDBCONF_WKDBCNT_4096CK32 (RSTC_WKDBCONF_WKDBCNT_4096CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 129 #define RSTC_WKDBCONF_WKDBCNT_32768CK32 (RSTC_WKDBCONF_WKDBCNT_32768CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) 130 #define RSTC_WKDBCONF_MASK _U(0x1F) /**< \brief (RSTC_WKDBCONF) MASK Register */ 131 132 /* -------- RSTC_WKPOL : (RSTC Offset: 0x08) (R/W 16) Wakeup Polarity -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint16_t WKPOL:8; /*!< bit: 0.. 7 Wakeup Polarity */ 137 uint16_t :8; /*!< bit: 8..15 Reserved */ 138 } bit; /*!< Structure used for bit access */ 139 uint16_t reg; /*!< Type used for register access */ 140 } RSTC_WKPOL_Type; 141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 142 143 #define RSTC_WKPOL_OFFSET 0x08 /**< \brief (RSTC_WKPOL offset) Wakeup Polarity */ 144 #define RSTC_WKPOL_RESETVALUE _U(0x0000) /**< \brief (RSTC_WKPOL reset_value) Wakeup Polarity */ 145 146 #define RSTC_WKPOL_WKPOL_Pos 0 /**< \brief (RSTC_WKPOL) Wakeup Polarity */ 147 #define RSTC_WKPOL_WKPOL_Msk (_U(0xFF) << RSTC_WKPOL_WKPOL_Pos) 148 #define RSTC_WKPOL_WKPOL(value) (RSTC_WKPOL_WKPOL_Msk & ((value) << RSTC_WKPOL_WKPOL_Pos)) 149 #define RSTC_WKPOL_MASK _U(0x00FF) /**< \brief (RSTC_WKPOL) MASK Register */ 150 151 /* -------- RSTC_WKEN : (RSTC Offset: 0x0C) (R/W 16) Wakeup Enable -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint16_t WKEN:8; /*!< bit: 0.. 7 Wakeup Enable */ 156 uint16_t :8; /*!< bit: 8..15 Reserved */ 157 } bit; /*!< Structure used for bit access */ 158 uint16_t reg; /*!< Type used for register access */ 159 } RSTC_WKEN_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define RSTC_WKEN_OFFSET 0x0C /**< \brief (RSTC_WKEN offset) Wakeup Enable */ 163 #define RSTC_WKEN_RESETVALUE _U(0x0000) /**< \brief (RSTC_WKEN reset_value) Wakeup Enable */ 164 165 #define RSTC_WKEN_WKEN_Pos 0 /**< \brief (RSTC_WKEN) Wakeup Enable */ 166 #define RSTC_WKEN_WKEN_Msk (_U(0xFF) << RSTC_WKEN_WKEN_Pos) 167 #define RSTC_WKEN_WKEN(value) (RSTC_WKEN_WKEN_Msk & ((value) << RSTC_WKEN_WKEN_Pos)) 168 #define RSTC_WKEN_MASK _U(0x00FF) /**< \brief (RSTC_WKEN) MASK Register */ 169 170 /* -------- RSTC_WKCAUSE : (RSTC Offset: 0x10) (R/W 16) Wakeup Cause -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint16_t WKCAUSE:16; /*!< bit: 0..15 Wakeup Cause */ 175 } bit; /*!< Structure used for bit access */ 176 uint16_t reg; /*!< Type used for register access */ 177 } RSTC_WKCAUSE_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define RSTC_WKCAUSE_OFFSET 0x10 /**< \brief (RSTC_WKCAUSE offset) Wakeup Cause */ 181 #define RSTC_WKCAUSE_RESETVALUE _U(0x0000) /**< \brief (RSTC_WKCAUSE reset_value) Wakeup Cause */ 182 183 #define RSTC_WKCAUSE_WKCAUSE_Pos 0 /**< \brief (RSTC_WKCAUSE) Wakeup Cause */ 184 #define RSTC_WKCAUSE_WKCAUSE_Msk (_U(0xFFFF) << RSTC_WKCAUSE_WKCAUSE_Pos) 185 #define RSTC_WKCAUSE_WKCAUSE(value) (RSTC_WKCAUSE_WKCAUSE_Msk & ((value) << RSTC_WKCAUSE_WKCAUSE_Pos)) 186 #define RSTC_WKCAUSE_MASK _U(0xFFFF) /**< \brief (RSTC_WKCAUSE) MASK Register */ 187 188 /** \brief RSTC hardware registers */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef struct { 191 __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ 192 RoReg8 Reserved1[0x1]; 193 __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */ 194 RoReg8 Reserved2[0x1]; 195 __IO RSTC_WKDBCONF_Type WKDBCONF; /**< \brief Offset: 0x04 (R/W 8) Wakeup Debounce Configuration */ 196 RoReg8 Reserved3[0x3]; 197 __IO RSTC_WKPOL_Type WKPOL; /**< \brief Offset: 0x08 (R/W 16) Wakeup Polarity */ 198 RoReg8 Reserved4[0x2]; 199 __IO RSTC_WKEN_Type WKEN; /**< \brief Offset: 0x0C (R/W 16) Wakeup Enable */ 200 RoReg8 Reserved5[0x2]; 201 __IO RSTC_WKCAUSE_Type WKCAUSE; /**< \brief Offset: 0x10 (R/W 16) Wakeup Cause */ 202 } Rstc; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 /*@}*/ 206 207 #endif /* _SAML21_RSTC_COMPONENT_ */ 208
