1 /** 2 * \file 3 * 4 * \brief Component description for TRNG 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TRNG_COMPONENT_ 30 #define _SAML21_TRNG_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TRNG */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_TRNG True Random Generator */ 36 /*@{*/ 37 38 #define TRNG_U2242 39 #define REV_TRNG 0x100 40 41 /* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t :1; /*!< bit: 0 Reserved */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 48 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 49 uint8_t :1; /*!< bit: 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } TRNG_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */ 56 #define TRNG_CTRLA_RESETVALUE _U(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */ 57 58 #define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */ 59 #define TRNG_CTRLA_ENABLE (_U(0x1) << TRNG_CTRLA_ENABLE_Pos) 60 #define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */ 61 #define TRNG_CTRLA_RUNSTDBY (_U(0x1) << TRNG_CTRLA_RUNSTDBY_Pos) 62 #define TRNG_CTRLA_MASK _U(0x42) /**< \brief (TRNG_CTRLA) MASK Register */ 63 64 /* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */ 65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 66 typedef union { 67 struct { 68 uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */ 69 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } TRNG_EVCTRL_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */ 76 #define TRNG_EVCTRL_RESETVALUE _U(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */ 77 78 #define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */ 79 #define TRNG_EVCTRL_DATARDYEO (_U(0x1) << TRNG_EVCTRL_DATARDYEO_Pos) 80 #define TRNG_EVCTRL_MASK _U(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */ 81 82 /* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 83 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 84 typedef union { 85 struct { 86 uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 87 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 88 } bit; /*!< Structure used for bit access */ 89 uint8_t reg; /*!< Type used for register access */ 90 } TRNG_INTENCLR_Type; 91 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 93 #define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */ 94 #define TRNG_INTENCLR_RESETVALUE _U(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */ 95 96 #define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */ 97 #define TRNG_INTENCLR_DATARDY (_U(0x1) << TRNG_INTENCLR_DATARDY_Pos) 98 #define TRNG_INTENCLR_MASK _U(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */ 99 100 /* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 105 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 106 } bit; /*!< Structure used for bit access */ 107 uint8_t reg; /*!< Type used for register access */ 108 } TRNG_INTENSET_Type; 109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 #define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */ 112 #define TRNG_INTENSET_RESETVALUE _U(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */ 113 114 #define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */ 115 #define TRNG_INTENSET_DATARDY (_U(0x1) << TRNG_INTENSET_DATARDY_Pos) 116 #define TRNG_INTENSET_MASK _U(0x01) /**< \brief (TRNG_INTENSET) MASK Register */ 117 118 /* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 120 typedef union { // __I to avoid read-modify-write on write-to-clear register 121 struct { 122 __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */ 123 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 124 } bit; /*!< Structure used for bit access */ 125 uint8_t reg; /*!< Type used for register access */ 126 } TRNG_INTFLAG_Type; 127 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 #define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */ 130 #define TRNG_INTFLAG_RESETVALUE _U(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */ 131 132 #define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */ 133 #define TRNG_INTFLAG_DATARDY (_U(0x1) << TRNG_INTFLAG_DATARDY_Pos) 134 #define TRNG_INTFLAG_MASK _U(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */ 135 136 /* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */ 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef union { 139 struct { 140 uint32_t DATA:32; /*!< bit: 0..31 Output Data */ 141 } bit; /*!< Structure used for bit access */ 142 uint32_t reg; /*!< Type used for register access */ 143 } TRNG_DATA_Type; 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 #define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */ 147 #define TRNG_DATA_RESETVALUE _U(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */ 148 149 #define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */ 150 #define TRNG_DATA_DATA_Msk (_U(0xFFFFFFFF) << TRNG_DATA_DATA_Pos) 151 #define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos)) 152 #define TRNG_DATA_MASK _U(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */ 153 154 /** \brief TRNG hardware registers */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef struct { 157 __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 158 RoReg8 Reserved1[0x3]; 159 __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */ 160 RoReg8 Reserved2[0x3]; 161 __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 162 __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 163 __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 164 RoReg8 Reserved3[0x15]; 165 __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */ 166 } Trng; 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 168 169 /*@}*/ 170 171 #endif /* _SAML21_TRNG_COMPONENT_ */ 172
