1 /** 2 * \file 3 * 4 * \brief Component description for ADC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_ADC_COMPONENT_ 30 #define _SAML21_ADC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR ADC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_ADC Analog Digital Converter */ 36 /*@{*/ 37 38 #define ADC_U2247 39 #define REV_ADC 0x111 40 41 /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 48 uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 49 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } ADC_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ 56 #define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ 57 58 #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ 59 #define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) 60 #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ 61 #define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) 62 #define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ 63 #define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) 64 #define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ 65 #define ADC_CTRLA_ONDEMAND (_U(0x1) << ADC_CTRLA_ONDEMAND_Pos) 66 #define ADC_CTRLA_MASK _U(0xC3) /**< \brief (ADC_CTRLA) MASK Register */ 67 68 /* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 70 typedef union { 71 struct { 72 uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ 73 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 uint8_t reg; /*!< Type used for register access */ 76 } ADC_CTRLB_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ 80 #define ADC_CTRLB_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ 81 82 #define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ 83 #define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos) 84 #define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) 85 #define ADC_CTRLB_PRESCALER_DIV2_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ 86 #define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ 87 #define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ 88 #define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ 89 #define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ 90 #define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ 91 #define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ 92 #define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ 93 #define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) 94 #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) 95 #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) 96 #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) 97 #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) 98 #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) 99 #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) 100 #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) 101 #define ADC_CTRLB_MASK _U(0x07) /**< \brief (ADC_CTRLB) MASK Register */ 102 103 /* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ 108 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 109 uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ 110 } bit; /*!< Structure used for bit access */ 111 uint8_t reg; /*!< Type used for register access */ 112 } ADC_REFCTRL_Type; 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 #define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ 116 #define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ 117 118 #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ 119 #define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) 120 #define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) 121 #define ADC_REFCTRL_REFSEL_INTREF_Val _U(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ 122 #define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ 123 #define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ 124 #define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External Reference */ 125 #define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External Reference */ 126 #define ADC_REFCTRL_REFSEL_INTVCC2_Val _U(0x5) /**< \brief (ADC_REFCTRL) VCCANA */ 127 #define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) 128 #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) 129 #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) 130 #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) 131 #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) 132 #define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) 133 #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ 134 #define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) 135 #define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ 136 137 /* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ 142 uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ 143 uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ 144 uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ 145 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ 146 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ 147 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 148 } bit; /*!< Structure used for bit access */ 149 uint8_t reg; /*!< Type used for register access */ 150 } ADC_EVCTRL_Type; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 153 #define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ 154 #define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ 155 156 #define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ 157 #define ADC_EVCTRL_FLUSHEI (_U(0x1) << ADC_EVCTRL_FLUSHEI_Pos) 158 #define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ 159 #define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) 160 #define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ 161 #define ADC_EVCTRL_FLUSHINV (_U(0x1) << ADC_EVCTRL_FLUSHINV_Pos) 162 #define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ 163 #define ADC_EVCTRL_STARTINV (_U(0x1) << ADC_EVCTRL_STARTINV_Pos) 164 #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ 165 #define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) 166 #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ 167 #define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) 168 #define ADC_EVCTRL_MASK _U(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ 169 170 /* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ 175 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ 176 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ 177 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 178 } bit; /*!< Structure used for bit access */ 179 uint8_t reg; /*!< Type used for register access */ 180 } ADC_INTENCLR_Type; 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ 184 #define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ 185 186 #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ 187 #define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) 188 #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ 189 #define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) 190 #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ 191 #define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) 192 #define ADC_INTENCLR_MASK _U(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ 193 194 /* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 196 typedef union { 197 struct { 198 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ 199 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ 200 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ 201 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint8_t reg; /*!< Type used for register access */ 204 } ADC_INTENSET_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ 208 #define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ 209 210 #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ 211 #define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) 212 #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ 213 #define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) 214 #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ 215 #define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) 216 #define ADC_INTENSET_MASK _U(0x07) /**< \brief (ADC_INTENSET) MASK Register */ 217 218 /* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { // __I to avoid read-modify-write on write-to-clear register 221 struct { 222 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ 223 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ 224 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ 225 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 226 } bit; /*!< Structure used for bit access */ 227 uint8_t reg; /*!< Type used for register access */ 228 } ADC_INTFLAG_Type; 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 230 231 #define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ 232 #define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 233 234 #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ 235 #define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) 236 #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ 237 #define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) 238 #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ 239 #define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) 240 #define ADC_INTFLAG_MASK _U(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ 241 242 /* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 244 typedef union { 245 struct { 246 uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ 247 uint8_t :2; /*!< bit: 5.. 6 Reserved */ 248 uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ 249 } bit; /*!< Structure used for bit access */ 250 uint8_t reg; /*!< Type used for register access */ 251 } ADC_SEQSTATUS_Type; 252 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 253 254 #define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ 255 #define ADC_SEQSTATUS_RESETVALUE _U(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ 256 257 #define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ 258 #define ADC_SEQSTATUS_SEQSTATE_Msk (_U(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) 259 #define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) 260 #define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ 261 #define ADC_SEQSTATUS_SEQBUSY (_U(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) 262 #define ADC_SEQSTATUS_MASK _U(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ 263 264 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 struct { 268 uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ 269 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 270 uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ 271 uint16_t :3; /*!< bit: 13..15 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 uint16_t reg; /*!< Type used for register access */ 274 } ADC_INPUTCTRL_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ 278 #define ADC_INPUTCTRL_RESETVALUE _U(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ 279 280 #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ 281 #define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) 282 #define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) 283 #define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ 284 #define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ 285 #define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ 286 #define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ 287 #define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ 288 #define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ 289 #define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ 290 #define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ 291 #define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ 292 #define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ 293 #define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ 294 #define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ 295 #define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ 296 #define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ 297 #define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ 298 #define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ 299 #define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ 300 #define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ 301 #define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ 302 #define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ 303 #define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ 304 #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ 305 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ 306 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ 307 #define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) 308 #define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) 309 #define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) 310 #define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) 311 #define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) 312 #define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) 313 #define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) 314 #define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) 315 #define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) 316 #define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) 317 #define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) 318 #define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) 319 #define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) 320 #define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) 321 #define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) 322 #define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) 323 #define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) 324 #define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) 325 #define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) 326 #define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) 327 #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) 328 #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) 329 #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) 330 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) 331 #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ 332 #define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) 333 #define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) 334 #define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ 335 #define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ 336 #define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ 337 #define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ 338 #define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ 339 #define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ 340 #define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal ground */ 341 #define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) 342 #define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) 343 #define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) 344 #define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) 345 #define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) 346 #define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) 347 #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) 348 #define ADC_INPUTCTRL_MASK _U(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ 349 350 /* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ 351 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 352 typedef union { 353 struct { 354 uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ 355 uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ 356 uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ 357 uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ 358 uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ 359 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 360 uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ 361 uint16_t :5; /*!< bit: 11..15 Reserved */ 362 } bit; /*!< Structure used for bit access */ 363 uint16_t reg; /*!< Type used for register access */ 364 } ADC_CTRLC_Type; 365 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 366 367 #define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ 368 #define ADC_CTRLC_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ 369 370 #define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ 371 #define ADC_CTRLC_DIFFMODE (_U(0x1) << ADC_CTRLC_DIFFMODE_Pos) 372 #define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ 373 #define ADC_CTRLC_LEFTADJ (_U(0x1) << ADC_CTRLC_LEFTADJ_Pos) 374 #define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ 375 #define ADC_CTRLC_FREERUN (_U(0x1) << ADC_CTRLC_FREERUN_Pos) 376 #define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ 377 #define ADC_CTRLC_CORREN (_U(0x1) << ADC_CTRLC_CORREN_Pos) 378 #define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ 379 #define ADC_CTRLC_RESSEL_Msk (_U(0x3) << ADC_CTRLC_RESSEL_Pos) 380 #define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) 381 #define ADC_CTRLC_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ 382 #define ADC_CTRLC_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ 383 #define ADC_CTRLC_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ 384 #define ADC_CTRLC_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ 385 #define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) 386 #define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) 387 #define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) 388 #define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) 389 #define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ 390 #define ADC_CTRLC_WINMODE_Msk (_U(0x7) << ADC_CTRLC_WINMODE_Pos) 391 #define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) 392 #define ADC_CTRLC_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ 393 #define ADC_CTRLC_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ 394 #define ADC_CTRLC_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ 395 #define ADC_CTRLC_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ 396 #define ADC_CTRLC_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ 397 #define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) 398 #define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) 399 #define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) 400 #define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) 401 #define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) 402 #define ADC_CTRLC_MASK _U(0x073F) /**< \brief (ADC_CTRLC) MASK Register */ 403 404 /* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ 405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 406 typedef union { 407 struct { 408 uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ 409 uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ 410 uint8_t :1; /*!< bit: 7 Reserved */ 411 } bit; /*!< Structure used for bit access */ 412 uint8_t reg; /*!< Type used for register access */ 413 } ADC_AVGCTRL_Type; 414 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ 417 #define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ 418 419 #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ 420 #define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) 421 #define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) 422 #define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ 423 #define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ 424 #define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ 425 #define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ 426 #define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ 427 #define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ 428 #define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ 429 #define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ 430 #define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ 431 #define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ 432 #define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ 433 #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 434 #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 435 #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 436 #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 437 #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 438 #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 439 #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 440 #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 441 #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 442 #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 443 #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) 444 #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ 445 #define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) 446 #define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) 447 #define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ 448 449 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 451 typedef union { 452 struct { 453 uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ 454 uint8_t :1; /*!< bit: 6 Reserved */ 455 uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ 456 } bit; /*!< Structure used for bit access */ 457 uint8_t reg; /*!< Type used for register access */ 458 } ADC_SAMPCTRL_Type; 459 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 460 461 #define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ 462 #define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ 463 464 #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ 465 #define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) 466 #define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) 467 #define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ 468 #define ADC_SAMPCTRL_OFFCOMP (_U(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) 469 #define ADC_SAMPCTRL_MASK _U(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ 470 471 /* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ 472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 typedef union { 474 struct { 475 uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ 476 } bit; /*!< Structure used for bit access */ 477 uint16_t reg; /*!< Type used for register access */ 478 } ADC_WINLT_Type; 479 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 480 481 #define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ 482 #define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ 483 484 #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ 485 #define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) 486 #define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) 487 #define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ 488 489 /* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 491 typedef union { 492 struct { 493 uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ 494 } bit; /*!< Structure used for bit access */ 495 uint16_t reg; /*!< Type used for register access */ 496 } ADC_WINUT_Type; 497 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 498 499 #define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ 500 #define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ 501 502 #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ 503 #define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) 504 #define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) 505 #define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ 506 507 /* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ 508 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 509 typedef union { 510 struct { 511 uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ 512 uint16_t :4; /*!< bit: 12..15 Reserved */ 513 } bit; /*!< Structure used for bit access */ 514 uint16_t reg; /*!< Type used for register access */ 515 } ADC_GAINCORR_Type; 516 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 517 518 #define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ 519 #define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ 520 521 #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ 522 #define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) 523 #define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) 524 #define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ 525 526 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ 527 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 528 typedef union { 529 struct { 530 uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ 531 uint16_t :4; /*!< bit: 12..15 Reserved */ 532 } bit; /*!< Structure used for bit access */ 533 uint16_t reg; /*!< Type used for register access */ 534 } ADC_OFFSETCORR_Type; 535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 536 537 #define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ 538 #define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ 539 540 #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ 541 #define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) 542 #define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) 543 #define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ 544 545 /* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ 546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 547 typedef union { 548 struct { 549 uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ 550 uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ 551 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 552 } bit; /*!< Structure used for bit access */ 553 uint8_t reg; /*!< Type used for register access */ 554 } ADC_SWTRIG_Type; 555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 556 557 #define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ 558 #define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ 559 560 #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ 561 #define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) 562 #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ 563 #define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) 564 #define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ 565 566 /* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ 567 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 568 typedef union { 569 struct { 570 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 571 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 572 } bit; /*!< Structure used for bit access */ 573 uint8_t reg; /*!< Type used for register access */ 574 } ADC_DBGCTRL_Type; 575 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 576 577 #define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ 578 #define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ 579 580 #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ 581 #define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) 582 #define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ 583 584 /* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ 585 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 586 typedef union { 587 struct { 588 uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ 589 uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ 590 uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ 591 uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ 592 uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ 593 uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ 594 uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ 595 uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ 596 uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ 597 uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ 598 uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ 599 uint16_t :5; /*!< bit: 11..15 Reserved */ 600 } bit; /*!< Structure used for bit access */ 601 uint16_t reg; /*!< Type used for register access */ 602 } ADC_SYNCBUSY_Type; 603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 #define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ 606 #define ADC_SYNCBUSY_RESETVALUE _U(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ 607 608 #define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ 609 #define ADC_SYNCBUSY_SWRST (_U(0x1) << ADC_SYNCBUSY_SWRST_Pos) 610 #define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ 611 #define ADC_SYNCBUSY_ENABLE (_U(0x1) << ADC_SYNCBUSY_ENABLE_Pos) 612 #define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ 613 #define ADC_SYNCBUSY_INPUTCTRL (_U(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) 614 #define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ 615 #define ADC_SYNCBUSY_CTRLC (_U(0x1) << ADC_SYNCBUSY_CTRLC_Pos) 616 #define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ 617 #define ADC_SYNCBUSY_AVGCTRL (_U(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) 618 #define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ 619 #define ADC_SYNCBUSY_SAMPCTRL (_U(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) 620 #define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ 621 #define ADC_SYNCBUSY_WINLT (_U(0x1) << ADC_SYNCBUSY_WINLT_Pos) 622 #define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ 623 #define ADC_SYNCBUSY_WINUT (_U(0x1) << ADC_SYNCBUSY_WINUT_Pos) 624 #define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ 625 #define ADC_SYNCBUSY_GAINCORR (_U(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) 626 #define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ 627 #define ADC_SYNCBUSY_OFFSETCORR (_U(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) 628 #define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ 629 #define ADC_SYNCBUSY_SWTRIG (_U(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) 630 #define ADC_SYNCBUSY_MASK _U(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ 631 632 /* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ 633 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 634 typedef union { 635 struct { 636 uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ 637 } bit; /*!< Structure used for bit access */ 638 uint16_t reg; /*!< Type used for register access */ 639 } ADC_RESULT_Type; 640 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 641 642 #define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ 643 #define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ 644 645 #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ 646 #define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) 647 #define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) 648 #define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ 649 650 /* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ 651 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 652 typedef union { 653 struct { 654 uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ 655 } bit; /*!< Structure used for bit access */ 656 uint32_t reg; /*!< Type used for register access */ 657 } ADC_SEQCTRL_Type; 658 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 659 660 #define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ 661 #define ADC_SEQCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ 662 663 #define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ 664 #define ADC_SEQCTRL_SEQEN_Msk (_U(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) 665 #define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) 666 #define ADC_SEQCTRL_MASK _U(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ 667 668 /* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ 669 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 670 typedef union { 671 struct { 672 uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ 673 uint16_t :5; /*!< bit: 3.. 7 Reserved */ 674 uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ 675 uint16_t :5; /*!< bit: 11..15 Reserved */ 676 } bit; /*!< Structure used for bit access */ 677 uint16_t reg; /*!< Type used for register access */ 678 } ADC_CALIB_Type; 679 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 680 681 #define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ 682 #define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ 683 684 #define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ 685 #define ADC_CALIB_BIASCOMP_Msk (_U(0x7) << ADC_CALIB_BIASCOMP_Pos) 686 #define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) 687 #define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ 688 #define ADC_CALIB_BIASREFBUF_Msk (_U(0x7) << ADC_CALIB_BIASREFBUF_Pos) 689 #define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) 690 #define ADC_CALIB_MASK _U(0x0707) /**< \brief (ADC_CALIB) MASK Register */ 691 692 /** \brief ADC hardware registers */ 693 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 694 typedef struct { 695 __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 696 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 697 __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ 698 __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ 699 __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 700 __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 701 __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 702 __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ 703 __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ 704 __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ 705 __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ 706 __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ 707 __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ 708 __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ 709 __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ 710 __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ 711 RoReg8 Reserved1[0x2]; 712 __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ 713 RoReg8 Reserved2[0x3]; 714 __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ 715 RoReg8 Reserved3[0x3]; 716 __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ 717 RoReg8 Reserved4[0x2]; 718 __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ 719 RoReg8 Reserved5[0x2]; 720 __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ 721 __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ 722 } Adc; 723 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 724 725 /*@}*/ 726 727 #endif /* _SAML21_ADC_COMPONENT_ */ 728
