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Searched refs:RCC (Results 1 – 25 of 41) sorted by relevance

12

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rcc.h657 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
659 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
667 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
674 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
676 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
685 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
693 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
[all …]
Dstm32l4xx_ll_rcc.h51 #if defined(RCC)
1247 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1254 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
2044 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
2054 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
2064 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass()
2074 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
2084 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
2094 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); in LL_RCC_HSE_IsReady()
2113 SET_BIT(RCC->CR, RCC_CR_HSIKERON); in LL_RCC_HSI_EnableInStopMode()
[all …]
Dstm32l4xx_ll_bus.h68 #if defined(RCC)
345 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
347 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
376 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
404 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
433 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
462 CLEAR_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
493 SET_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
495 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
526 CLEAR_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_DisableClockStopSleep()
[all …]
Dstm32l4xx_hal_rcc_ex.h934 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
943 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
956 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
964 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
989 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_…
1006 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PL…
1026 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI…
1031 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_P…
1048 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI…
1063 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI…
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_rcc.h661 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
663 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
668 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
670 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
675 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
677 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
[all …]
Dstm32l1xx_ll_rcc.h51 #if defined(RCC)
392 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
399 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
521 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
532 CLEAR_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_DisableCSS()
542 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
552 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass()
562 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
572 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
582 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); in LL_RCC_HSE_IsReady()
[all …]
Dstm32l1xx_hal_rcc_ex.h180 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
182 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
185 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
195 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
197 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
202 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
204 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
208 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
209 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
221 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
[all …]
Dstm32l1xx_ll_bus.h68 #if defined(RCC)
235 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
237 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
278 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
318 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
359 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
400 CLEAR_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
443 SET_BIT(RCC->AHBLPENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
445 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
488 CLEAR_BIT(RCC->AHBLPENR, Periphs); in LL_AHB1_GRP1_DisableClockSleep()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_rcc_ex.h600 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
602 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
605 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
607 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != RESET)
608 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == RESET)
615 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
617 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
620 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
622 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != RESET)
623 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == RESET)
[all …]
Dstm32l0xx_hal_rcc.h692 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
694 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
700 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
708 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
715 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
716 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
717 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
732 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
[all …]
Dstm32l0xx_ll_rcc.h51 #if defined(RCC)
586 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
593 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
716 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
727 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
737 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass()
747 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
757 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable()
767 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); in LL_RCC_HSE_IsReady()
782 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); in LL_RCC_SetRTC_HSEPrescaler()
[all …]
Dstm32l0xx_ll_bus.h68 #if defined(RCC)
243 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
245 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
270 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
294 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
319 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
344 CLEAR_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
371 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
373 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
400 CLEAR_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_DisableClockSleep()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_rcc.c111 (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
285 SET_BIT(RCC->CR, RCC_CR_MSION); in HAL_RCC_DeInit()
292 while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) in HAL_RCC_DeInit()
301 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); in HAL_RCC_DeInit()
304 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
320 while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) in HAL_RCC_DeInit()
331 …CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | … in HAL_RCC_DeInit()
335 …CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | … in HAL_RCC_DeInit()
339 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON); in HAL_RCC_DeInit()
349 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) in HAL_RCC_DeInit()
[all …]
Dstm32l4xx_hal_rcc_ex.c369 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
374 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
379 RCC->BDCR = tmpregister; in HAL_RCCEx_PeriphCLKConfig()
389 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
758 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) in HAL_RCCEx_PeriphCLKConfig()
948 …PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_P… in HAL_RCCEx_GetPeriphCLKConfig()
950 …PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLL… in HAL_RCCEx_GetPeriphCLKConfig()
952 …PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Po… in HAL_RCCEx_GetPeriphCLKConfig()
954 …PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLS… in HAL_RCCEx_GetPeriphCLKConfig()
955 …PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PL… in HAL_RCCEx_GetPeriphCLKConfig()
[all …]
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dsystem_stm32l1xx.c161 RCC->CR |= (uint32_t)0x00000100; in SystemInit()
164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
167 RCC->CR &= (uint32_t)0xEEFEFFFE; in SystemInit()
170 RCC->CR &= (uint32_t)0xFFFBFFFF; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
176 RCC->CIR = 0x00000000; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
237 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dsystem_stm32l1xx.c161 RCC->CR |= (uint32_t)0x00000100; in SystemInit()
164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
167 RCC->CR &= (uint32_t)0xEEFEFFFE; in SystemInit()
170 RCC->CR &= (uint32_t)0xFFFBFFFF; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
176 RCC->CIR = 0x00000000; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
237 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dsystem_stm32l1xx.c161 RCC->CR |= (uint32_t)0x00000100; in SystemInit()
164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
167 RCC->CR &= (uint32_t)0xEEFEFFFE; in SystemInit()
170 RCC->CR &= (uint32_t)0xFFFBFFFF; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
176 RCC->CIR = 0x00000000; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
237 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dsystem_stm32l1xx.c161 RCC->CR |= (uint32_t)0x00000100; in SystemInit()
164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
167 RCC->CR &= (uint32_t)0xEEFEFFFE; in SystemInit()
170 RCC->CR &= (uint32_t)0xFFFBFFFF; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
176 RCC->CIR = 0x00000000; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
237 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dsystem_stm32l4xx.c205 RCC->CR |= RCC_CR_MSION; in SystemInit()
208 RCC->CFGR = 0x00000000U; in SystemInit()
211 RCC->CR &= 0xEAF6FFFFU; in SystemInit()
214 RCC->PLLCFGR = 0x00001000U; in SystemInit()
217 RCC->CR &= 0xFFFBFFFFU; in SystemInit()
220 RCC->CIER = 0x00000000U; in SystemInit()
277 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) in SystemCoreClockUpdate()
279 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; in SystemCoreClockUpdate()
283 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; in SystemCoreClockUpdate()
289 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dsystem_stm32l0xx.c154 RCC->CR |= (uint32_t)0x00000100U; in SystemInit()
157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
160 RCC->CR &= (uint32_t)0xFEF6FFF6U; in SystemInit()
163 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; in SystemInit()
166 RCC->CR &= (uint32_t)0xFFFBFFFFU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
172 RCC->CIER = 0x00000000U; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
230 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dsystem_stm32l0xx.c154 RCC->CR |= (uint32_t)0x00000100U; in SystemInit()
157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
160 RCC->CR &= (uint32_t)0xFEF6FFF6U; in SystemInit()
163 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; in SystemInit()
166 RCC->CR &= (uint32_t)0xFFFBFFFFU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
172 RCC->CIER = 0x00000000U; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
230 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dsystem_stm32l0xx.c154 RCC->CR |= (uint32_t)0x00000100U; in SystemInit()
157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
160 RCC->CR &= (uint32_t)0xFEF6FFF6U; in SystemInit()
163 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; in SystemInit()
166 RCC->CR &= (uint32_t)0xFFFBFFFFU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
172 RCC->CIER = 0x00000000U; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
230 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_rcc.c276 SET_BIT(RCC->CR, RCC_CR_MSION); in HAL_RCC_DeInit()
279 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); in HAL_RCC_DeInit()
283 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ in HAL_RCC_DeInit()
286 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ in HAL_RCC_DeInit()
289 CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ in HAL_RCC_DeInit()
294 tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ in HAL_RCC_DeInit()
298 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in HAL_RCC_DeInit()
301 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
304 …MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITRI… in HAL_RCC_DeInit()
307 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << 8)); in HAL_RCC_DeInit()
[all …]
Dstm32l0xx_hal_rcc_ex.c177 temp_reg = (RCC->CR & RCC_CR_RTCPRE); in HAL_RCCEx_PeriphCLKConfig()
184 …CClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) in HAL_RCCEx_PeriphCLKConfig()
192 temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
203 temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
210 RCC->CSR = temp_reg; in HAL_RCCEx_PeriphCLKConfig()
349 PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); in HAL_RCCEx_GetPeriphCLKConfig()
414 temp_reg = RCC->CSR; in HAL_RCCEx_GetPeriphCLKFreq()
430 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) in HAL_RCCEx_GetPeriphCLKFreq()
472 if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) in HAL_RCCEx_GetPeriphCLKFreq()
475 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in HAL_RCCEx_GetPeriphCLKFreq()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_rcc.c262 SET_BIT(RCC->CR, RCC_CR_MSION); in HAL_RCC_DeInit()
265 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); in HAL_RCC_DeInit()
268 CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP); in HAL_RCC_DeInit()
270 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
273 …MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), ((0U << RCC_ICSCR_MSITRIM_BITNUMB… in HAL_RCC_DeInit()
276 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (0x10U << POSITION_VAL(RCC_ICSCR_HSITRIM))); in HAL_RCC_DeInit()
279 CLEAR_REG(RCC->CIR); in HAL_RCC_DeInit()
474 … >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER)]; in HAL_RCC_OscConfig()
778 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
886 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
[all …]

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