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Searched refs:MPU_RASR_C_Pos (Results 1 – 15 of 15) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm0plus.h569 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
570 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_sc000.h588 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
589 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm3.h1125 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_sc300.h1105 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm4.h1165 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
1166 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm7.h1349 #define MPU_RASR_C_Pos 17 /*!< MPU … macro
1350 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_cortex.c363 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | in HAL_MPU_ConfigRegion()
/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcore_cm0plus.h631 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
632 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_sc000.h642 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
643 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm3.h1206 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1207 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_sc300.h1188 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1189 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm4.h1267 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1268 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
Dcore_cm7.h1472 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1473 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_cortex.c362 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | in HAL_MPU_ConfigRegion()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_cortex.c508 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | in HAL_MPU_ConfigRegion()