1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16 (+) Access to VREFBUF registers
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
23 *
24 * Redistribution and use in source and binary forms, with or without modification,
25 * are permitted provided that the following conditions are met:
26 * 1. Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.
28 * 2. Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials provided with the distribution.
31 * 3. Neither the name of STMicroelectronics nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
36 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 ******************************************************************************
47 */
48
49 /* Define to prevent recursive inclusion -------------------------------------*/
50 #ifndef STM32L4xx_LL_SYSTEM_H
51 #define STM32L4xx_LL_SYSTEM_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32l4xx.h"
59
60 /** @addtogroup STM32L4xx_LL_Driver
61 * @{
62 */
63
64 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
65
66 /** @defgroup SYSTEM_LL SYSTEM
67 * @{
68 */
69
70 /* Private types -------------------------------------------------------------*/
71 /* Private variables ---------------------------------------------------------*/
72
73 /* Private constants ---------------------------------------------------------*/
74 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
75 * @{
76 */
77
78 /**
79 * @brief Power-down in Run mode Flash key
80 */
81 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
82 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
83 to unlock the RUN_PD bit in FLASH_ACR */
84
85 /**
86 * @}
87 */
88
89 /* Private macros ------------------------------------------------------------*/
90
91 /* Exported types ------------------------------------------------------------*/
92 /* Exported constants --------------------------------------------------------*/
93 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
94 * @{
95 */
96
97 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
98 * @{
99 */
100 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
101 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
102 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
103 #if defined(FMC_Bank1_R)
104 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
105 #endif /* FMC_Bank1_R */
106 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
107 /**
108 * @}
109 */
110
111 #if defined(SYSCFG_MEMRMP_FB_MODE)
112 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
113 * @{
114 */
115 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
116 and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
117 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
118 and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
119 /**
120 * @}
121 */
122
123 #endif /* SYSCFG_MEMRMP_FB_MODE */
124 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
125 * @{
126 */
127 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
128 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
129 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
130 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
131 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
132 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
133 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
134 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
135 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
136 #if defined(I2C2)
137 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
138 #endif /* I2C2 */
139 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
140 #if defined(I2C4)
141 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
142 #endif /* I2C4 */
143 /**
144 * @}
145 */
146
147 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
148 * @{
149 */
150 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
151 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
152 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
153 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
154 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
155 #if defined(GPIOF)
156 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
157 #endif /* GPIOF */
158 #if defined(GPIOG)
159 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
160 #endif /* GPIOG */
161 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
162 #if defined(GPIOI)
163 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
164 #endif /* GPIOI */
165 /**
166 * @}
167 */
168
169 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
170 * @{
171 */
172 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
173 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
174 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
175 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
176 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
177 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
178 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
179 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
180 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
181 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
182 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
183 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
184 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
185 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
186 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
187 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
188 /**
189 * @}
190 */
191
192 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
193 * @{
194 */
195 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
196 with Break Input of TIM1/8/15/16/17 */
197 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
198 with TIM1/8/15/16/17 Break Input
199 and also the PVDE and PLS bits of the Power Control Interface */
200 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
201 with Break Input of TIM1/8/15/16/17 */
202 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
203 with Break Input of TIM1/15/16/17 */
204 /**
205 * @}
206 */
207
208 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
209 * @{
210 */
211 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
212 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
213 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
214 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
215 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
222 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
223 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
224 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
225 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
226 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
227 #if defined(SYSCFG_SWPR_PAGE31)
228 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
229 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
230 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
231 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
232 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
233 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
234 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
235 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
236 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
237 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
238 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
239 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
240 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
241 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
242 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
243 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
244 #endif /* SYSCFG_SWPR_PAGE31 */
245 #if defined(SYSCFG_SWPR2_PAGE63)
246 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
247 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
248 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
249 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
250 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
251 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
252 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
253 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
254 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
255 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
256 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
257 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
258 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
259 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
260 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
261 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
262 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
263 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
264 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
265 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
266 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
267 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
268 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
269 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
270 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
271 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
272 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
273 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
274 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
275 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
276 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
277 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
278 #endif /* SYSCFG_SWPR2_PAGE63 */
279 /**
280 * @}
281 */
282
283 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
284 * @{
285 */
286 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
287 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
288 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
289 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
290 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
291 /**
292 * @}
293 */
294
295 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
296 * @{
297 */
298 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
299 #if defined(TIM3)
300 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
301 #endif /* TIM3 */
302 #if defined(TIM4)
303 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
304 #endif /* TIM4 */
305 #if defined(TIM5)
306 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
307 #endif /* TIM5 */
308 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
309 #if defined(TIM7)
310 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
311 #endif /* TIM7 */
312 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
313 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
314 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
315 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
316 #if defined(I2C2)
317 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
318 #endif /* I2C2 */
319 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
320 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/
321 #if defined(CAN2)
322 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/
323 #endif /* CAN2 */
324 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
325 /**
326 * @}
327 */
328
329 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
330 * @{
331 */
332 #if defined(I2C4)
333 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
334 #endif /* I2C4 */
335 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
336 /**
337 * @}
338 */
339
340 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
341 * @{
342 */
343 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
344 #if defined(TIM8)
345 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
346 #endif /* TIM8 */
347 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
348 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
349 #if defined(TIM17)
350 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
351 #endif /* TIM17 */
352 /**
353 * @}
354 */
355
356 #if defined(VREFBUF)
357 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
358 * @{
359 */
360 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
361 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
362 /**
363 * @}
364 */
365 #endif /* VREFBUF */
366
367 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
368 * @{
369 */
370 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
371 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
372 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
373 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
374 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
375 #if defined(FLASH_ACR_LATENCY_5WS)
376 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
377 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
378 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
379 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
380 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
381 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
382 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
383 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
384 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
385 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
386 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
387 #endif
388 /**
389 * @}
390 */
391
392 /**
393 * @}
394 */
395
396 /* Exported macro ------------------------------------------------------------*/
397
398 /* Exported functions --------------------------------------------------------*/
399 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
400 * @{
401 */
402
403 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
404 * @{
405 */
406
407 /**
408 * @brief Set memory mapping at address 0x00000000
409 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
410 * @param Memory This parameter can be one of the following values:
411 * @arg @ref LL_SYSCFG_REMAP_FLASH
412 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
413 * @arg @ref LL_SYSCFG_REMAP_SRAM
414 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
415 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
416 *
417 * (*) value not defined in all devices
418 * @retval None
419 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)420 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
421 {
422 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
423 }
424
425 /**
426 * @brief Get memory mapping at address 0x00000000
427 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
428 * @retval Returned value can be one of the following values:
429 * @arg @ref LL_SYSCFG_REMAP_FLASH
430 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
431 * @arg @ref LL_SYSCFG_REMAP_SRAM
432 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
433 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
434 *
435 * (*) value not defined in all devices
436 */
LL_SYSCFG_GetRemapMemory(void)437 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
438 {
439 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
440 }
441
442 #if defined(SYSCFG_MEMRMP_FB_MODE)
443 /**
444 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
445 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
446 * @param Bank This parameter can be one of the following values:
447 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
448 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
449 * @retval None
450 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)451 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
452 {
453 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
454 }
455
456 /**
457 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
458 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
459 * @retval Returned value can be one of the following values:
460 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
461 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
462 */
LL_SYSCFG_GetFlashBankMode(void)463 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
464 {
465 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
466 }
467 #endif /* SYSCFG_MEMRMP_FB_MODE */
468
469 /**
470 * @brief Firewall protection enabled
471 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
472 * @retval None
473 */
LL_SYSCFG_EnableFirewall(void)474 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
475 {
476 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
477 }
478
479 /**
480 * @brief Check if Firewall protection is enabled or not
481 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
482 * @retval State of bit (1 or 0).
483 */
LL_SYSCFG_IsEnabledFirewall(void)484 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
485 {
486 return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
487 }
488
489 /**
490 * @brief Enable I/O analog switch voltage booster.
491 * @note When voltage booster is enabled, I/O analog switches are supplied
492 * by a dedicated voltage booster, from VDD power domain. This is
493 * the recommended configuration with low VDDA voltage operation.
494 * @note The I/O analog switch voltage booster is relevant for peripherals
495 * using I/O in analog input: ADC, COMP, OPAMP.
496 * However, COMP and OPAMP inputs have a high impedance and
497 * voltage booster do not impact performance significantly.
498 * Therefore, the voltage booster is mainly intended for
499 * usage with ADC.
500 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
501 * @retval None
502 */
LL_SYSCFG_EnableAnalogBooster(void)503 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
504 {
505 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
506 }
507
508 /**
509 * @brief Disable I/O analog switch voltage booster.
510 * @note When voltage booster is enabled, I/O analog switches are supplied
511 * by a dedicated voltage booster, from VDD power domain. This is
512 * the recommended configuration with low VDDA voltage operation.
513 * @note The I/O analog switch voltage booster is relevant for peripherals
514 * using I/O in analog input: ADC, COMP, OPAMP.
515 * However, COMP and OPAMP inputs have a high impedance and
516 * voltage booster do not impact performance significantly.
517 * Therefore, the voltage booster is mainly intended for
518 * usage with ADC.
519 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
520 * @retval None
521 */
LL_SYSCFG_DisableAnalogBooster(void)522 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
523 {
524 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
525 }
526
527 /**
528 * @brief Enable the I2C fast mode plus driving capability.
529 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
530 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
531 * @param ConfigFastModePlus This parameter can be a combination of the following values:
532 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
533 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
534 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
535 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
536 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
537 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
540 *
541 * (*) value not defined in all devices
542 * @retval None
543 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)544 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
545 {
546 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
547 }
548
549 /**
550 * @brief Disable the I2C fast mode plus driving capability.
551 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
552 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
553 * @param ConfigFastModePlus This parameter can be a combination of the following values:
554 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
555 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
556 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
557 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
558 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
559 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
560 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
562 *
563 * (*) value not defined in all devices
564 * @retval None
565 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)566 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
567 {
568 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
569 }
570
571 /**
572 * @brief Enable Floating Point Unit Invalid operation Interrupt
573 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
574 * @retval None
575 */
LL_SYSCFG_EnableIT_FPU_IOC(void)576 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
577 {
578 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
579 }
580
581 /**
582 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
583 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
584 * @retval None
585 */
LL_SYSCFG_EnableIT_FPU_DZC(void)586 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
587 {
588 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
589 }
590
591 /**
592 * @brief Enable Floating Point Unit Underflow Interrupt
593 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
594 * @retval None
595 */
LL_SYSCFG_EnableIT_FPU_UFC(void)596 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
597 {
598 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
599 }
600
601 /**
602 * @brief Enable Floating Point Unit Overflow Interrupt
603 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
604 * @retval None
605 */
LL_SYSCFG_EnableIT_FPU_OFC(void)606 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
607 {
608 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
609 }
610
611 /**
612 * @brief Enable Floating Point Unit Input denormal Interrupt
613 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
614 * @retval None
615 */
LL_SYSCFG_EnableIT_FPU_IDC(void)616 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
617 {
618 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
619 }
620
621 /**
622 * @brief Enable Floating Point Unit Inexact Interrupt
623 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
624 * @retval None
625 */
LL_SYSCFG_EnableIT_FPU_IXC(void)626 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
627 {
628 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
629 }
630
631 /**
632 * @brief Disable Floating Point Unit Invalid operation Interrupt
633 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
634 * @retval None
635 */
LL_SYSCFG_DisableIT_FPU_IOC(void)636 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
637 {
638 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
639 }
640
641 /**
642 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
643 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
644 * @retval None
645 */
LL_SYSCFG_DisableIT_FPU_DZC(void)646 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
647 {
648 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
649 }
650
651 /**
652 * @brief Disable Floating Point Unit Underflow Interrupt
653 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
654 * @retval None
655 */
LL_SYSCFG_DisableIT_FPU_UFC(void)656 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
657 {
658 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
659 }
660
661 /**
662 * @brief Disable Floating Point Unit Overflow Interrupt
663 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
664 * @retval None
665 */
LL_SYSCFG_DisableIT_FPU_OFC(void)666 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
667 {
668 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
669 }
670
671 /**
672 * @brief Disable Floating Point Unit Input denormal Interrupt
673 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
674 * @retval None
675 */
LL_SYSCFG_DisableIT_FPU_IDC(void)676 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
677 {
678 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
679 }
680
681 /**
682 * @brief Disable Floating Point Unit Inexact Interrupt
683 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
684 * @retval None
685 */
LL_SYSCFG_DisableIT_FPU_IXC(void)686 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
687 {
688 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
689 }
690
691 /**
692 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
693 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
694 * @retval State of bit (1 or 0).
695 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)696 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
697 {
698 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
699 }
700
701 /**
702 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
703 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
704 * @retval State of bit (1 or 0).
705 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)706 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
707 {
708 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
709 }
710
711 /**
712 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
713 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
714 * @retval State of bit (1 or 0).
715 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)716 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
717 {
718 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
719 }
720
721 /**
722 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
723 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
724 * @retval State of bit (1 or 0).
725 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)726 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
727 {
728 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
729 }
730
731 /**
732 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
733 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
734 * @retval State of bit (1 or 0).
735 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)736 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
737 {
738 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
739 }
740
741 /**
742 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
743 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
744 * @retval State of bit (1 or 0).
745 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)746 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
747 {
748 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
749 }
750
751 /**
752 * @brief Configure source input for the EXTI external interrupt.
753 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
754 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
755 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
756 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
757 * @param Port This parameter can be one of the following values:
758 * @arg @ref LL_SYSCFG_EXTI_PORTA
759 * @arg @ref LL_SYSCFG_EXTI_PORTB
760 * @arg @ref LL_SYSCFG_EXTI_PORTC
761 * @arg @ref LL_SYSCFG_EXTI_PORTD
762 * @arg @ref LL_SYSCFG_EXTI_PORTE
763 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
764 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
765 * @arg @ref LL_SYSCFG_EXTI_PORTH
766 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
767 *
768 * (*) value not defined in all devices
769 * @param Line This parameter can be one of the following values:
770 * @arg @ref LL_SYSCFG_EXTI_LINE0
771 * @arg @ref LL_SYSCFG_EXTI_LINE1
772 * @arg @ref LL_SYSCFG_EXTI_LINE2
773 * @arg @ref LL_SYSCFG_EXTI_LINE3
774 * @arg @ref LL_SYSCFG_EXTI_LINE4
775 * @arg @ref LL_SYSCFG_EXTI_LINE5
776 * @arg @ref LL_SYSCFG_EXTI_LINE6
777 * @arg @ref LL_SYSCFG_EXTI_LINE7
778 * @arg @ref LL_SYSCFG_EXTI_LINE8
779 * @arg @ref LL_SYSCFG_EXTI_LINE9
780 * @arg @ref LL_SYSCFG_EXTI_LINE10
781 * @arg @ref LL_SYSCFG_EXTI_LINE11
782 * @arg @ref LL_SYSCFG_EXTI_LINE12
783 * @arg @ref LL_SYSCFG_EXTI_LINE13
784 * @arg @ref LL_SYSCFG_EXTI_LINE14
785 * @arg @ref LL_SYSCFG_EXTI_LINE15
786 * @retval None
787 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)788 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
789 {
790 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
791 }
792
793 /**
794 * @brief Get the configured defined for specific EXTI Line
795 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
796 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
797 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
798 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
799 * @param Line This parameter can be one of the following values:
800 * @arg @ref LL_SYSCFG_EXTI_LINE0
801 * @arg @ref LL_SYSCFG_EXTI_LINE1
802 * @arg @ref LL_SYSCFG_EXTI_LINE2
803 * @arg @ref LL_SYSCFG_EXTI_LINE3
804 * @arg @ref LL_SYSCFG_EXTI_LINE4
805 * @arg @ref LL_SYSCFG_EXTI_LINE5
806 * @arg @ref LL_SYSCFG_EXTI_LINE6
807 * @arg @ref LL_SYSCFG_EXTI_LINE7
808 * @arg @ref LL_SYSCFG_EXTI_LINE8
809 * @arg @ref LL_SYSCFG_EXTI_LINE9
810 * @arg @ref LL_SYSCFG_EXTI_LINE10
811 * @arg @ref LL_SYSCFG_EXTI_LINE11
812 * @arg @ref LL_SYSCFG_EXTI_LINE12
813 * @arg @ref LL_SYSCFG_EXTI_LINE13
814 * @arg @ref LL_SYSCFG_EXTI_LINE14
815 * @arg @ref LL_SYSCFG_EXTI_LINE15
816 * @retval Returned value can be one of the following values:
817 * @arg @ref LL_SYSCFG_EXTI_PORTA
818 * @arg @ref LL_SYSCFG_EXTI_PORTB
819 * @arg @ref LL_SYSCFG_EXTI_PORTC
820 * @arg @ref LL_SYSCFG_EXTI_PORTD
821 * @arg @ref LL_SYSCFG_EXTI_PORTE
822 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
823 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
824 * @arg @ref LL_SYSCFG_EXTI_PORTH
825 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
826 *
827 * (*) value not defined in all devices
828 */
LL_SYSCFG_GetEXTISource(uint32_t Line)829 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
830 {
831 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
832 }
833
834 /**
835 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
836 * automatically cleared at the end of the SRAM2 erase operation.)
837 * @note This bit is write-protected: setting this bit is possible only after the
838 * correct key sequence is written in the SYSCFG_SKR register as described in
839 * the Reference Manual.
840 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
841 * @retval None
842 */
LL_SYSCFG_EnableSRAM2Erase(void)843 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
844 {
845 /* Starts a hardware SRAM2 erase operation*/
846 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
847 }
848
849 /**
850 * @brief Check if SRAM2 erase operation is on going
851 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
852 * @retval State of bit (1 or 0).
853 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)854 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
855 {
856 return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
857 }
858
859 /**
860 * @brief Set connections to TIM1/8/15/16/17 Break inputs
861 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
862 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
863 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
864 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
865 * @param Break This parameter can be a combination of the following values:
866 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
867 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
868 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
869 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
870 * @retval None
871 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)872 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
873 {
874 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
875 }
876
877 /**
878 * @brief Get connections to TIM1/8/15/16/17 Break inputs
879 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
880 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
881 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
882 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
883 * @retval Returned value can be can be a combination of the following values:
884 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
885 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
886 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
887 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
888 */
LL_SYSCFG_GetTIMBreakInputs(void)889 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
890 {
891 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
892 }
893
894 /**
895 * @brief Check if SRAM2 parity error detected
896 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
897 * @retval State of bit (1 or 0).
898 */
LL_SYSCFG_IsActiveFlag_SP(void)899 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
900 {
901 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
902 }
903
904 /**
905 * @brief Clear SRAM2 parity error flag
906 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
907 * @retval None
908 */
LL_SYSCFG_ClearFlag_SP(void)909 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
910 {
911 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
912 }
913
914 /**
915 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
916 * @note Write protection is cleared only by a system reset
917 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
918 * @param SRAM2WRP This parameter can be a combination of the following values:
919 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
920 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
921 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
922 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
923 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
924 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
925 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
926 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
927 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
928 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
929 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
930 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
931 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
932 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
933 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
934 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
935 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
936 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
937 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
938 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
939 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
940 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
941 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
942 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
943 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
944 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
945 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
946 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
947 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
948 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
949 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
950 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
951 *
952 * (*) value not defined in all devices
953 * @retval None
954 */
955 /* Legacy define */
956 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)957 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
958 {
959 SET_BIT(SYSCFG->SWPR, SRAM2WRP);
960 }
961
962 #if defined(SYSCFG_SWPR2_PAGE63)
963 /**
964 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
965 * @note Write protection is cleared only by a system reset
966 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
967 * @param SRAM2WRP This parameter can be a combination of the following values:
968 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
969 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
970 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
971 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
982 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
983 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
984 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
985 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
986 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
987 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
988 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
989 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
990 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
991 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
992 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
993 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
994 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
995 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
996 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
997 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
998 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
999 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
1000 *
1001 * (*) value not defined in all devices
1002 * @retval None
1003 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)1004 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
1005 {
1006 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
1007 }
1008 #endif /* SYSCFG_SWPR2_PAGE63 */
1009
1010 /**
1011 * @brief SRAM2 page write protection lock prior to erase
1012 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
1013 * @retval None
1014 */
LL_SYSCFG_LockSRAM2WRP(void)1015 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1016 {
1017 /* Writing a wrong key reactivates the write protection */
1018 WRITE_REG(SYSCFG->SKR, 0x00);
1019 }
1020
1021 /**
1022 * @brief SRAM2 page write protection unlock prior to erase
1023 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1024 * @retval None
1025 */
LL_SYSCFG_UnlockSRAM2WRP(void)1026 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1027 {
1028 /* unlock the write protection of the SRAM2ER bit */
1029 WRITE_REG(SYSCFG->SKR, 0xCA);
1030 WRITE_REG(SYSCFG->SKR, 0x53);
1031 }
1032
1033 /**
1034 * @}
1035 */
1036
1037
1038 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1039 * @{
1040 */
1041
1042 /**
1043 * @brief Return the device identifier
1044 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1045 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1046 */
LL_DBGMCU_GetDeviceID(void)1047 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1048 {
1049 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1050 }
1051
1052 /**
1053 * @brief Return the device revision identifier
1054 * @note This field indicates the revision of the device.
1055 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1056 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1057 */
LL_DBGMCU_GetRevisionID(void)1058 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1059 {
1060 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1061 }
1062
1063 /**
1064 * @brief Enable the Debug Module during SLEEP mode
1065 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1066 * @retval None
1067 */
LL_DBGMCU_EnableDBGSleepMode(void)1068 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1069 {
1070 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1071 }
1072
1073 /**
1074 * @brief Disable the Debug Module during SLEEP mode
1075 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1076 * @retval None
1077 */
LL_DBGMCU_DisableDBGSleepMode(void)1078 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1079 {
1080 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1081 }
1082
1083 /**
1084 * @brief Enable the Debug Module during STOP mode
1085 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1086 * @retval None
1087 */
LL_DBGMCU_EnableDBGStopMode(void)1088 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1089 {
1090 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1091 }
1092
1093 /**
1094 * @brief Disable the Debug Module during STOP mode
1095 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1096 * @retval None
1097 */
LL_DBGMCU_DisableDBGStopMode(void)1098 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1099 {
1100 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1101 }
1102
1103 /**
1104 * @brief Enable the Debug Module during STANDBY mode
1105 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1106 * @retval None
1107 */
LL_DBGMCU_EnableDBGStandbyMode(void)1108 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1109 {
1110 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1111 }
1112
1113 /**
1114 * @brief Disable the Debug Module during STANDBY mode
1115 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1116 * @retval None
1117 */
LL_DBGMCU_DisableDBGStandbyMode(void)1118 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1119 {
1120 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1121 }
1122
1123 /**
1124 * @brief Set Trace pin assignment control
1125 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1126 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1127 * @param PinAssignment This parameter can be one of the following values:
1128 * @arg @ref LL_DBGMCU_TRACE_NONE
1129 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1130 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1131 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1132 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1133 * @retval None
1134 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1135 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1136 {
1137 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1138 }
1139
1140 /**
1141 * @brief Get Trace pin assignment control
1142 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1143 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1144 * @retval Returned value can be one of the following values:
1145 * @arg @ref LL_DBGMCU_TRACE_NONE
1146 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1147 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1148 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1149 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1150 */
LL_DBGMCU_GetTracePinAssignment(void)1151 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1152 {
1153 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1154 }
1155
1156 /**
1157 * @brief Freeze APB1 peripherals (group1 peripherals)
1158 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1159 * @param Periphs This parameter can be a combination of the following values:
1160 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1161 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1162 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1163 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1164 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1165 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1166 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1167 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1168 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1169 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1170 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1171 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1172 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1173 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1174 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1175 *
1176 * (*) value not defined in all devices.
1177 * @retval None
1178 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1179 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1180 {
1181 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1182 }
1183
1184 /**
1185 * @brief Freeze APB1 peripherals (group2 peripherals)
1186 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1187 * @param Periphs This parameter can be a combination of the following values:
1188 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1189 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1190 *
1191 * (*) value not defined in all devices.
1192 * @retval None
1193 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1194 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1195 {
1196 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1197 }
1198
1199 /**
1200 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1201 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1202 * @param Periphs This parameter can be a combination of the following values:
1203 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1204 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1205 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1206 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1207 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1208 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1209 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1210 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1211 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1212 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1213 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1214 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1215 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1216 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1217 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1218 *
1219 * (*) value not defined in all devices.
1220 * @retval None
1221 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1222 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1223 {
1224 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1225 }
1226
1227 /**
1228 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1229 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1230 * @param Periphs This parameter can be a combination of the following values:
1231 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1232 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1233 *
1234 * (*) value not defined in all devices.
1235 * @retval None
1236 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1237 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1238 {
1239 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1240 }
1241
1242 /**
1243 * @brief Freeze APB2 peripherals
1244 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1245 * @param Periphs This parameter can be a combination of the following values:
1246 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1247 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1248 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1249 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1250 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1251 *
1252 * (*) value not defined in all devices.
1253 * @retval None
1254 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1255 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1256 {
1257 SET_BIT(DBGMCU->APB2FZ, Periphs);
1258 }
1259
1260 /**
1261 * @brief Unfreeze APB2 peripherals
1262 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1263 * @param Periphs This parameter can be a combination of the following values:
1264 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1265 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1266 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1267 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1268 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1269 *
1270 * (*) value not defined in all devices.
1271 * @retval None
1272 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1273 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1274 {
1275 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1276 }
1277
1278 /**
1279 * @}
1280 */
1281
1282 #if defined(VREFBUF)
1283 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1284 * @{
1285 */
1286
1287 /**
1288 * @brief Enable Internal voltage reference
1289 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1290 * @retval None
1291 */
LL_VREFBUF_Enable(void)1292 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1293 {
1294 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1295 }
1296
1297 /**
1298 * @brief Disable Internal voltage reference
1299 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1300 * @retval None
1301 */
LL_VREFBUF_Disable(void)1302 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1303 {
1304 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1305 }
1306
1307 /**
1308 * @brief Enable high impedance (VREF+pin is high impedance)
1309 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1310 * @retval None
1311 */
LL_VREFBUF_EnableHIZ(void)1312 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1313 {
1314 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1315 }
1316
1317 /**
1318 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1319 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1320 * @retval None
1321 */
LL_VREFBUF_DisableHIZ(void)1322 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1323 {
1324 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1325 }
1326
1327 /**
1328 * @brief Set the Voltage reference scale
1329 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1330 * @param Scale This parameter can be one of the following values:
1331 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1332 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1333 * @retval None
1334 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1335 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1336 {
1337 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1338 }
1339
1340 /**
1341 * @brief Get the Voltage reference scale
1342 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1343 * @retval Returned value can be one of the following values:
1344 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1345 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1346 */
LL_VREFBUF_GetVoltageScaling(void)1347 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1348 {
1349 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1350 }
1351
1352 /**
1353 * @brief Check if Voltage reference buffer is ready
1354 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1355 * @retval State of bit (1 or 0).
1356 */
LL_VREFBUF_IsVREFReady(void)1357 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1358 {
1359 return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
1360 }
1361
1362 /**
1363 * @brief Get the trimming code for VREFBUF calibration
1364 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1365 * @retval Between 0 and 0x3F
1366 */
LL_VREFBUF_GetTrimming(void)1367 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1368 {
1369 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1370 }
1371
1372 /**
1373 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1374 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1375 * @param Value Between 0 and 0x3F
1376 * @retval None
1377 */
LL_VREFBUF_SetTrimming(uint32_t Value)1378 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1379 {
1380 WRITE_REG(VREFBUF->CCR, Value);
1381 }
1382
1383 /**
1384 * @}
1385 */
1386 #endif /* VREFBUF */
1387
1388 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1389 * @{
1390 */
1391
1392 /**
1393 * @brief Set FLASH Latency
1394 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1395 * @param Latency This parameter can be one of the following values:
1396 * @arg @ref LL_FLASH_LATENCY_0
1397 * @arg @ref LL_FLASH_LATENCY_1
1398 * @arg @ref LL_FLASH_LATENCY_2
1399 * @arg @ref LL_FLASH_LATENCY_3
1400 * @arg @ref LL_FLASH_LATENCY_4
1401 * @arg @ref LL_FLASH_LATENCY_5 (*)
1402 * @arg @ref LL_FLASH_LATENCY_6 (*)
1403 * @arg @ref LL_FLASH_LATENCY_7 (*)
1404 * @arg @ref LL_FLASH_LATENCY_8 (*)
1405 * @arg @ref LL_FLASH_LATENCY_9 (*)
1406 * @arg @ref LL_FLASH_LATENCY_10 (*)
1407 * @arg @ref LL_FLASH_LATENCY_11 (*)
1408 * @arg @ref LL_FLASH_LATENCY_12 (*)
1409 * @arg @ref LL_FLASH_LATENCY_13 (*)
1410 * @arg @ref LL_FLASH_LATENCY_14 (*)
1411 * @arg @ref LL_FLASH_LATENCY_15 (*)
1412 *
1413 * (*) value not defined in all devices.
1414 * @retval None
1415 */
LL_FLASH_SetLatency(uint32_t Latency)1416 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1417 {
1418 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1419 }
1420
1421 /**
1422 * @brief Get FLASH Latency
1423 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1424 * @retval Returned value can be one of the following values:
1425 * @arg @ref LL_FLASH_LATENCY_0
1426 * @arg @ref LL_FLASH_LATENCY_1
1427 * @arg @ref LL_FLASH_LATENCY_2
1428 * @arg @ref LL_FLASH_LATENCY_3
1429 * @arg @ref LL_FLASH_LATENCY_4
1430 * @arg @ref LL_FLASH_LATENCY_5 (*)
1431 * @arg @ref LL_FLASH_LATENCY_6 (*)
1432 * @arg @ref LL_FLASH_LATENCY_7 (*)
1433 * @arg @ref LL_FLASH_LATENCY_8 (*)
1434 * @arg @ref LL_FLASH_LATENCY_9 (*)
1435 * @arg @ref LL_FLASH_LATENCY_10 (*)
1436 * @arg @ref LL_FLASH_LATENCY_11 (*)
1437 * @arg @ref LL_FLASH_LATENCY_12 (*)
1438 * @arg @ref LL_FLASH_LATENCY_13 (*)
1439 * @arg @ref LL_FLASH_LATENCY_14 (*)
1440 * @arg @ref LL_FLASH_LATENCY_15 (*)
1441 *
1442 * (*) value not defined in all devices.
1443 */
LL_FLASH_GetLatency(void)1444 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1445 {
1446 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1447 }
1448
1449 /**
1450 * @brief Enable Prefetch
1451 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1452 * @retval None
1453 */
LL_FLASH_EnablePrefetch(void)1454 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1455 {
1456 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1457 }
1458
1459 /**
1460 * @brief Disable Prefetch
1461 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1462 * @retval None
1463 */
LL_FLASH_DisablePrefetch(void)1464 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1465 {
1466 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1467 }
1468
1469 /**
1470 * @brief Check if Prefetch buffer is enabled
1471 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1472 * @retval State of bit (1 or 0).
1473 */
LL_FLASH_IsPrefetchEnabled(void)1474 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1475 {
1476 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1477 }
1478
1479 /**
1480 * @brief Enable Instruction cache
1481 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1482 * @retval None
1483 */
LL_FLASH_EnableInstCache(void)1484 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1485 {
1486 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1487 }
1488
1489 /**
1490 * @brief Disable Instruction cache
1491 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1492 * @retval None
1493 */
LL_FLASH_DisableInstCache(void)1494 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1495 {
1496 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1497 }
1498
1499 /**
1500 * @brief Enable Data cache
1501 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1502 * @retval None
1503 */
LL_FLASH_EnableDataCache(void)1504 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1505 {
1506 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1507 }
1508
1509 /**
1510 * @brief Disable Data cache
1511 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1512 * @retval None
1513 */
LL_FLASH_DisableDataCache(void)1514 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1515 {
1516 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1517 }
1518
1519 /**
1520 * @brief Enable Instruction cache reset
1521 * @note bit can be written only when the instruction cache is disabled
1522 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1523 * @retval None
1524 */
LL_FLASH_EnableInstCacheReset(void)1525 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1526 {
1527 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1528 }
1529
1530 /**
1531 * @brief Disable Instruction cache reset
1532 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1533 * @retval None
1534 */
LL_FLASH_DisableInstCacheReset(void)1535 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1536 {
1537 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1538 }
1539
1540 /**
1541 * @brief Enable Data cache reset
1542 * @note bit can be written only when the data cache is disabled
1543 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1544 * @retval None
1545 */
LL_FLASH_EnableDataCacheReset(void)1546 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1547 {
1548 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1549 }
1550
1551 /**
1552 * @brief Disable Data cache reset
1553 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1554 * @retval None
1555 */
LL_FLASH_DisableDataCacheReset(void)1556 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1557 {
1558 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1559 }
1560
1561 /**
1562 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1563 * @note Flash memory can be put in power-down mode only when the code is executed
1564 * from RAM
1565 * @note Flash must not be accessed when power down is enabled
1566 * @note Flash must not be put in power-down while a program or an erase operation
1567 * is on-going
1568 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1569 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1570 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1571 * @retval None
1572 */
LL_FLASH_EnableRunPowerDown(void)1573 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1574 {
1575 /* Following values must be written consecutively to unlock the RUN_PD bit in
1576 FLASH_ACR */
1577 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1578 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1579 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1580 }
1581
1582 /**
1583 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1584 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1585 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1586 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1587 * @retval None
1588 */
LL_FLASH_DisableRunPowerDown(void)1589 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1590 {
1591 /* Following values must be written consecutively to unlock the RUN_PD bit in
1592 FLASH_ACR */
1593 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1594 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1595 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1596 }
1597
1598 /**
1599 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1600 * @note Flash must not be put in power-down while a program or an erase operation
1601 * is on-going
1602 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1603 * @retval None
1604 */
LL_FLASH_EnableSleepPowerDown(void)1605 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1606 {
1607 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1608 }
1609
1610 /**
1611 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1612 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1613 * @retval None
1614 */
LL_FLASH_DisableSleepPowerDown(void)1615 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1616 {
1617 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1618 }
1619
1620 /**
1621 * @}
1622 */
1623
1624 /**
1625 * @}
1626 */
1627
1628 /**
1629 * @}
1630 */
1631
1632 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1633
1634 /**
1635 * @}
1636 */
1637
1638 #ifdef __cplusplus
1639 }
1640 #endif
1641
1642 #endif /* STM32L4xx_LL_SYSTEM_H */
1643
1644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1645
