Home
last modified time | relevance | path

Searched refs:KR (Results 1 – 14 of 14) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_iwdg.h121 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
129 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
189 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
196 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l1xx_ll_iwdg.h162 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
173 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
184 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
195 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_iwdg.h132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l4xx_ll_iwdg.h163 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
174 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
185 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
196 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_iwdg.h132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l0xx_ll_iwdg.h163 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
174 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
185 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
196 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ member
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h389 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ member
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h366 …__IO uint32_t KR; /*!< Key register, Address offset: 0x00… member
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h366 …__IO uint32_t KR; /*!< Key register, Address offset: 0x00… member
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h388 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ member
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h396 …__IO uint32_t KR; /*!< Key register, Address offset: 0x00… member
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h405 …__IO uint32_t KR; /*!< Key register, Address offset: 0x00… member
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h590 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ member