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Searched refs:IFCR (Results 1 – 19 of 19) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_dma.h1618 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
1629 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); in LL_DMA_ClearFlag_GI2()
1640 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); in LL_DMA_ClearFlag_GI3()
1651 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); in LL_DMA_ClearFlag_GI4()
1662 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); in LL_DMA_ClearFlag_GI5()
1674 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); in LL_DMA_ClearFlag_GI6()
1687 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); in LL_DMA_ClearFlag_GI7()
1699 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); in LL_DMA_ClearFlag_TC1()
1710 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); in LL_DMA_ClearFlag_TC2()
1721 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); in LL_DMA_ClearFlag_TC3()
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Dstm32l0xx_hal_dma.h571 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_dma.h1494 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
1505 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); in LL_DMA_ClearFlag_GI2()
1516 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); in LL_DMA_ClearFlag_GI3()
1527 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); in LL_DMA_ClearFlag_GI4()
1538 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); in LL_DMA_ClearFlag_GI5()
1549 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); in LL_DMA_ClearFlag_GI6()
1560 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); in LL_DMA_ClearFlag_GI7()
1571 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); in LL_DMA_ClearFlag_TC1()
1582 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); in LL_DMA_ClearFlag_TC2()
1593 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); in LL_DMA_ClearFlag_TC3()
[all …]
Dstm32l1xx_hal_dma.h448 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
534 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_dma.h1861 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
1872 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); in LL_DMA_ClearFlag_GI2()
1883 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); in LL_DMA_ClearFlag_GI3()
1894 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); in LL_DMA_ClearFlag_GI4()
1905 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); in LL_DMA_ClearFlag_GI5()
1916 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); in LL_DMA_ClearFlag_GI6()
1927 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); in LL_DMA_ClearFlag_GI7()
1938 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); in LL_DMA_ClearFlag_TC1()
1949 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); in LL_DMA_ClearFlag_TC2()
1960 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); in LL_DMA_ClearFlag_TC3()
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Dstm32l4xx_ll_dma2d.h1861 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); in LL_DMA2D_ClearFlag_CE()
1872 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); in LL_DMA2D_ClearFlag_CTC()
1883 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); in LL_DMA2D_ClearFlag_CAE()
1894 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); in LL_DMA2D_ClearFlag_TW()
1905 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); in LL_DMA2D_ClearFlag_TC()
1916 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); in LL_DMA2D_ClearFlag_TE()
Dstm32l4xx_hal_dma.h594 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
Dstm32l4xx_hal_dma2d.h452 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_dma.c293 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); in HAL_DMA_DeInit()
447 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); in HAL_DMA_Abort()
484 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); in HAL_DMA_Abort_IT()
551 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex)); in HAL_DMA_PollForTransfer()
586 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); in HAL_DMA_PollForTransfer()
595 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); in HAL_DMA_PollForTransfer()
625 hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); in HAL_DMA_IRQHandler()
650 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); in HAL_DMA_IRQHandler()
671 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); in HAL_DMA_IRQHandler()
871 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); in DMA_SetConfig()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_dma.c344 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_DeInit()
585 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_Abort()
642 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_Abort_IT()
659 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_Abort_IT()
727 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_PollForTransfer()
791 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU)); in HAL_DMA_PollForTransfer()
800 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_PollForTransfer()
830 hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU); in HAL_DMA_IRQHandler()
854 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_IRQHandler()
875 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); in HAL_DMA_IRQHandler()
[all …]
Dstm32l4xx_hal_dma2d.c389 hdma2d->Instance->IFCR = 0x3FU; in HAL_DMA2D_DeInit()
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h244 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h262 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h271 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h271 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h261 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h280 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h282 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04… member
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h432 …__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x0… member