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Searched refs:ICSR (Results 1 – 20 of 20) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_systemcontrol_l21.h367 ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTCLR; in hri_systemcontrol_set_ICSR_PENDSTCLR_bit()
374 tmp = ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_get_ICSR_PENDSTCLR_bit()
383 tmp = ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_write_ICSR_PENDSTCLR_bit()
386 ((Systemcontrol *)hw)->ICSR.reg = tmp; in hri_systemcontrol_write_ICSR_PENDSTCLR_bit()
393 ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTCLR; in hri_systemcontrol_clear_ICSR_PENDSTCLR_bit()
400 ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTCLR; in hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit()
407 ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTSET; in hri_systemcontrol_set_ICSR_PENDSTSET_bit()
414 tmp = ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_get_ICSR_PENDSTSET_bit()
423 tmp = ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_write_ICSR_PENDSTSET_bit()
426 ((Systemcontrol *)hw)->ICSR.reg = tmp; in hri_systemcontrol_write_ICSR_PENDSTSET_bit()
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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_rtc.c348 CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); in HAL_RTC_Init()
436 while(((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) in HAL_RTC_DeInit()
469 CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); in HAL_RTC_DeInit()
890 CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); in HAL_RTC_SetTime()
1054 CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); in HAL_RTC_SetDate()
1842 hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; in HAL_RTC_WaitForSynchro()
1851 while((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) in HAL_RTC_WaitForSynchro()
1918 if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) in RTC_EnterInitMode()
1921 SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); in RTC_EnterInitMode()
1925 while((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) in RTC_EnterInitMode()
Dstm32l4xx_hal_rtc_ex.c1152 if((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
1161 while((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
1268 while((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U)
1442 hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
1495 hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
/loramac-node-3.4.0/src/boards/mcu/saml21/hpl/core/
Dhpl_core_port.h66 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_rtc.h996 WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); in LL_RTC_EnableInitMode()
1008 WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); in LL_RTC_DisableInitMode()
3527 return (READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)); in LL_RTC_IsActiveFlag_RECALP()
3659 return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)); in LL_RTC_IsActiveFlag_INIT()
3670 return (READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)); in LL_RTC_IsActiveFlag_RS()
3681 …WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_IN… in LL_RTC_ClearFlag_RS()
3692 return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)); in LL_RTC_IsActiveFlag_INITS()
3703 return (READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)); in LL_RTC_IsActiveFlag_SHP()
3714 return (READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)); in LL_RTC_IsActiveFlag_WUTW()
3725 return (READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)); in LL_RTC_IsActiveFlag_ALRBW()
[all …]
Dstm32l4xx_hal_rtc_ex.h579 …__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_…
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm0.h337 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm0plus.h348 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc000.h343 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm3.h351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc300.h351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm4.h398 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm7.h413 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcore_cm0.h392 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm0plus.h406 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc000.h398 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm3.h420 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc300.h420 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm4.h488 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm7.h503 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member