1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_PAC_COMPONENT_ 30 #define _SAML21_PAC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PAC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_PAC Peripheral Access Controller */ 36 /*@{*/ 37 38 #define PAC_U2120 39 #define REV_PAC 0x110 40 41 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ 46 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ 47 uint32_t :8; /*!< bit: 24..31 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } PAC_WRCTRL_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ 54 #define PAC_WRCTRL_RESETVALUE _U(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */ 55 56 #define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ 57 #define PAC_WRCTRL_PERID_Msk (_U(0xFFFF) << PAC_WRCTRL_PERID_Pos) 58 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos)) 59 #define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ 60 #define PAC_WRCTRL_KEY_Msk (_U(0xFF) << PAC_WRCTRL_KEY_Pos) 61 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos)) 62 #define PAC_WRCTRL_KEY_OFF_Val _U(0x0) /**< \brief (PAC_WRCTRL) No action */ 63 #define PAC_WRCTRL_KEY_CLR_Val _U(0x1) /**< \brief (PAC_WRCTRL) Clear protection */ 64 #define PAC_WRCTRL_KEY_SET_Val _U(0x2) /**< \brief (PAC_WRCTRL) Set protection */ 65 #define PAC_WRCTRL_KEY_SETLCK_Val _U(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */ 66 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) 67 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) 68 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) 69 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) 70 #define PAC_WRCTRL_MASK _U(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */ 71 72 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 73 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 74 typedef union { 75 struct { 76 uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ 77 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 78 } bit; /*!< Structure used for bit access */ 79 uint8_t reg; /*!< Type used for register access */ 80 } PAC_EVCTRL_Type; 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 #define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ 84 #define PAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */ 85 86 #define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ 87 #define PAC_EVCTRL_ERREO (_U(0x1) << PAC_EVCTRL_ERREO_Pos) 88 #define PAC_EVCTRL_MASK _U(0x01) /**< \brief (PAC_EVCTRL) MASK Register */ 89 90 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { 93 struct { 94 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ 95 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 96 } bit; /*!< Structure used for bit access */ 97 uint8_t reg; /*!< Type used for register access */ 98 } PAC_INTENCLR_Type; 99 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 100 101 #define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ 102 #define PAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ 103 104 #define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ 105 #define PAC_INTENCLR_ERR (_U(0x1) << PAC_INTENCLR_ERR_Pos) 106 #define PAC_INTENCLR_MASK _U(0x01) /**< \brief (PAC_INTENCLR) MASK Register */ 107 108 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { 111 struct { 112 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ 113 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 114 } bit; /*!< Structure used for bit access */ 115 uint8_t reg; /*!< Type used for register access */ 116 } PAC_INTENSET_Type; 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 #define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ 120 #define PAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ 121 122 #define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ 123 #define PAC_INTENSET_ERR (_U(0x1) << PAC_INTENSET_ERR_Pos) 124 #define PAC_INTENSET_MASK _U(0x01) /**< \brief (PAC_INTENSET) MASK Register */ 125 126 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 128 typedef union { // __I to avoid read-modify-write on write-to-clear register 129 struct { 130 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ 131 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ 132 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ 133 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ 134 __I uint32_t H2LBRIDGES_:1; /*!< bit: 4 H2LBRIDGES */ 135 __I uint32_t :11; /*!< bit: 5..15 Reserved */ 136 __I uint32_t HPB0_:1; /*!< bit: 16 HPB0 */ 137 __I uint32_t HPB2_:1; /*!< bit: 17 HPB2 */ 138 __I uint32_t HPB3_:1; /*!< bit: 18 HPB3 */ 139 __I uint32_t HPB4_:1; /*!< bit: 19 HPB4 */ 140 __I uint32_t :1; /*!< bit: 20 Reserved */ 141 __I uint32_t LPRAMHS_:1; /*!< bit: 21 LPRAMHS */ 142 __I uint32_t LPRAMPICOP_:1; /*!< bit: 22 LPRAMPICOP */ 143 __I uint32_t LPRAMDMAC_:1; /*!< bit: 23 LPRAMDMAC */ 144 __I uint32_t L2HBRIDGES_:1; /*!< bit: 24 L2HBRIDGES */ 145 __I uint32_t HSRAMLP_:1; /*!< bit: 25 HSRAMLP */ 146 __I uint32_t :6; /*!< bit: 26..31 Reserved */ 147 } bit; /*!< Structure used for bit access */ 148 uint32_t reg; /*!< Type used for register access */ 149 } PAC_INTFLAGAHB_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 #define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ 153 #define PAC_INTFLAGAHB_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ 154 155 #define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ 156 #define PAC_INTFLAGAHB_FLASH (_U(0x1) << PAC_INTFLAGAHB_FLASH_Pos) 157 #define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ 158 #define PAC_INTFLAGAHB_HSRAMCM0P (_U(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos) 159 #define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ 160 #define PAC_INTFLAGAHB_HSRAMDSU (_U(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos) 161 #define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ 162 #define PAC_INTFLAGAHB_HPB1 (_U(0x1) << PAC_INTFLAGAHB_HPB1_Pos) 163 #define PAC_INTFLAGAHB_H2LBRIDGES_Pos 4 /**< \brief (PAC_INTFLAGAHB) H2LBRIDGES */ 164 #define PAC_INTFLAGAHB_H2LBRIDGES (_U(0x1) << PAC_INTFLAGAHB_H2LBRIDGES_Pos) 165 #define PAC_INTFLAGAHB_HPB0_Pos 16 /**< \brief (PAC_INTFLAGAHB) HPB0 */ 166 #define PAC_INTFLAGAHB_HPB0 (_U(0x1) << PAC_INTFLAGAHB_HPB0_Pos) 167 #define PAC_INTFLAGAHB_HPB2_Pos 17 /**< \brief (PAC_INTFLAGAHB) HPB2 */ 168 #define PAC_INTFLAGAHB_HPB2 (_U(0x1) << PAC_INTFLAGAHB_HPB2_Pos) 169 #define PAC_INTFLAGAHB_HPB3_Pos 18 /**< \brief (PAC_INTFLAGAHB) HPB3 */ 170 #define PAC_INTFLAGAHB_HPB3 (_U(0x1) << PAC_INTFLAGAHB_HPB3_Pos) 171 #define PAC_INTFLAGAHB_HPB4_Pos 19 /**< \brief (PAC_INTFLAGAHB) HPB4 */ 172 #define PAC_INTFLAGAHB_HPB4 (_U(0x1) << PAC_INTFLAGAHB_HPB4_Pos) 173 #define PAC_INTFLAGAHB_LPRAMHS_Pos 21 /**< \brief (PAC_INTFLAGAHB) LPRAMHS */ 174 #define PAC_INTFLAGAHB_LPRAMHS (_U(0x1) << PAC_INTFLAGAHB_LPRAMHS_Pos) 175 #define PAC_INTFLAGAHB_LPRAMPICOP_Pos 22 /**< \brief (PAC_INTFLAGAHB) LPRAMPICOP */ 176 #define PAC_INTFLAGAHB_LPRAMPICOP (_U(0x1) << PAC_INTFLAGAHB_LPRAMPICOP_Pos) 177 #define PAC_INTFLAGAHB_LPRAMDMAC_Pos 23 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ 178 #define PAC_INTFLAGAHB_LPRAMDMAC (_U(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos) 179 #define PAC_INTFLAGAHB_L2HBRIDGES_Pos 24 /**< \brief (PAC_INTFLAGAHB) L2HBRIDGES */ 180 #define PAC_INTFLAGAHB_L2HBRIDGES (_U(0x1) << PAC_INTFLAGAHB_L2HBRIDGES_Pos) 181 #define PAC_INTFLAGAHB_HSRAMLP_Pos 25 /**< \brief (PAC_INTFLAGAHB) HSRAMLP */ 182 #define PAC_INTFLAGAHB_HSRAMLP (_U(0x1) << PAC_INTFLAGAHB_HSRAMLP_Pos) 183 #define PAC_INTFLAGAHB_MASK _U(0x03EF001F) /**< \brief (PAC_INTFLAGAHB) MASK Register */ 184 185 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { // __I to avoid read-modify-write on write-to-clear register 188 struct { 189 __I uint32_t PM_:1; /*!< bit: 0 PM */ 190 __I uint32_t MCLK_:1; /*!< bit: 1 MCLK */ 191 __I uint32_t RSTC_:1; /*!< bit: 2 RSTC */ 192 __I uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL */ 193 __I uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL */ 194 __I uint32_t SUPC_:1; /*!< bit: 5 SUPC */ 195 __I uint32_t GCLK_:1; /*!< bit: 6 GCLK */ 196 __I uint32_t WDT_:1; /*!< bit: 7 WDT */ 197 __I uint32_t RTC_:1; /*!< bit: 8 RTC */ 198 __I uint32_t EIC_:1; /*!< bit: 9 EIC */ 199 __I uint32_t PORT_:1; /*!< bit: 10 PORT */ 200 __I uint32_t TAL_:1; /*!< bit: 11 TAL */ 201 __I uint32_t :20; /*!< bit: 12..31 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint32_t reg; /*!< Type used for register access */ 204 } PAC_INTFLAGA_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ 208 #define PAC_INTFLAGA_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ 209 210 #define PAC_INTFLAGA_PM_Pos 0 /**< \brief (PAC_INTFLAGA) PM */ 211 #define PAC_INTFLAGA_PM (_U(0x1) << PAC_INTFLAGA_PM_Pos) 212 #define PAC_INTFLAGA_MCLK_Pos 1 /**< \brief (PAC_INTFLAGA) MCLK */ 213 #define PAC_INTFLAGA_MCLK (_U(0x1) << PAC_INTFLAGA_MCLK_Pos) 214 #define PAC_INTFLAGA_RSTC_Pos 2 /**< \brief (PAC_INTFLAGA) RSTC */ 215 #define PAC_INTFLAGA_RSTC (_U(0x1) << PAC_INTFLAGA_RSTC_Pos) 216 #define PAC_INTFLAGA_OSCCTRL_Pos 3 /**< \brief (PAC_INTFLAGA) OSCCTRL */ 217 #define PAC_INTFLAGA_OSCCTRL (_U(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) 218 #define PAC_INTFLAGA_OSC32KCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ 219 #define PAC_INTFLAGA_OSC32KCTRL (_U(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) 220 #define PAC_INTFLAGA_SUPC_Pos 5 /**< \brief (PAC_INTFLAGA) SUPC */ 221 #define PAC_INTFLAGA_SUPC (_U(0x1) << PAC_INTFLAGA_SUPC_Pos) 222 #define PAC_INTFLAGA_GCLK_Pos 6 /**< \brief (PAC_INTFLAGA) GCLK */ 223 #define PAC_INTFLAGA_GCLK (_U(0x1) << PAC_INTFLAGA_GCLK_Pos) 224 #define PAC_INTFLAGA_WDT_Pos 7 /**< \brief (PAC_INTFLAGA) WDT */ 225 #define PAC_INTFLAGA_WDT (_U(0x1) << PAC_INTFLAGA_WDT_Pos) 226 #define PAC_INTFLAGA_RTC_Pos 8 /**< \brief (PAC_INTFLAGA) RTC */ 227 #define PAC_INTFLAGA_RTC (_U(0x1) << PAC_INTFLAGA_RTC_Pos) 228 #define PAC_INTFLAGA_EIC_Pos 9 /**< \brief (PAC_INTFLAGA) EIC */ 229 #define PAC_INTFLAGA_EIC (_U(0x1) << PAC_INTFLAGA_EIC_Pos) 230 #define PAC_INTFLAGA_PORT_Pos 10 /**< \brief (PAC_INTFLAGA) PORT */ 231 #define PAC_INTFLAGA_PORT (_U(0x1) << PAC_INTFLAGA_PORT_Pos) 232 #define PAC_INTFLAGA_TAL_Pos 11 /**< \brief (PAC_INTFLAGA) TAL */ 233 #define PAC_INTFLAGA_TAL (_U(0x1) << PAC_INTFLAGA_TAL_Pos) 234 #define PAC_INTFLAGA_MASK _U(0x00000FFF) /**< \brief (PAC_INTFLAGA) MASK Register */ 235 236 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 238 typedef union { // __I to avoid read-modify-write on write-to-clear register 239 struct { 240 __I uint32_t USB_:1; /*!< bit: 0 USB */ 241 __I uint32_t DSU_:1; /*!< bit: 1 DSU */ 242 __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ 243 __I uint32_t MTB_:1; /*!< bit: 3 MTB */ 244 __I uint32_t :28; /*!< bit: 4..31 Reserved */ 245 } bit; /*!< Structure used for bit access */ 246 uint32_t reg; /*!< Type used for register access */ 247 } PAC_INTFLAGB_Type; 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 #define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ 251 #define PAC_INTFLAGB_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ 252 253 #define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */ 254 #define PAC_INTFLAGB_USB (_U(0x1) << PAC_INTFLAGB_USB_Pos) 255 #define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ 256 #define PAC_INTFLAGB_DSU (_U(0x1) << PAC_INTFLAGB_DSU_Pos) 257 #define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ 258 #define PAC_INTFLAGB_NVMCTRL (_U(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) 259 #define PAC_INTFLAGB_MTB_Pos 3 /**< \brief (PAC_INTFLAGB) MTB */ 260 #define PAC_INTFLAGB_MTB (_U(0x1) << PAC_INTFLAGB_MTB_Pos) 261 #define PAC_INTFLAGB_MASK _U(0x0000000F) /**< \brief (PAC_INTFLAGB) MASK Register */ 262 263 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 265 typedef union { // __I to avoid read-modify-write on write-to-clear register 266 struct { 267 __I uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 */ 268 __I uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 */ 269 __I uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 */ 270 __I uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 */ 271 __I uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 */ 272 __I uint32_t TCC0_:1; /*!< bit: 5 TCC0 */ 273 __I uint32_t TCC1_:1; /*!< bit: 6 TCC1 */ 274 __I uint32_t TCC2_:1; /*!< bit: 7 TCC2 */ 275 __I uint32_t TC0_:1; /*!< bit: 8 TC0 */ 276 __I uint32_t TC1_:1; /*!< bit: 9 TC1 */ 277 __I uint32_t TC2_:1; /*!< bit: 10 TC2 */ 278 __I uint32_t TC3_:1; /*!< bit: 11 TC3 */ 279 __I uint32_t DAC_:1; /*!< bit: 12 DAC */ 280 __I uint32_t AES_:1; /*!< bit: 13 AES */ 281 __I uint32_t TRNG_:1; /*!< bit: 14 TRNG */ 282 __I uint32_t :17; /*!< bit: 15..31 Reserved */ 283 } bit; /*!< Structure used for bit access */ 284 uint32_t reg; /*!< Type used for register access */ 285 } PAC_INTFLAGC_Type; 286 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 287 288 #define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ 289 #define PAC_INTFLAGC_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ 290 291 #define PAC_INTFLAGC_SERCOM0_Pos 0 /**< \brief (PAC_INTFLAGC) SERCOM0 */ 292 #define PAC_INTFLAGC_SERCOM0 (_U(0x1) << PAC_INTFLAGC_SERCOM0_Pos) 293 #define PAC_INTFLAGC_SERCOM1_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM1 */ 294 #define PAC_INTFLAGC_SERCOM1 (_U(0x1) << PAC_INTFLAGC_SERCOM1_Pos) 295 #define PAC_INTFLAGC_SERCOM2_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM2 */ 296 #define PAC_INTFLAGC_SERCOM2 (_U(0x1) << PAC_INTFLAGC_SERCOM2_Pos) 297 #define PAC_INTFLAGC_SERCOM3_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM3 */ 298 #define PAC_INTFLAGC_SERCOM3 (_U(0x1) << PAC_INTFLAGC_SERCOM3_Pos) 299 #define PAC_INTFLAGC_SERCOM4_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM4 */ 300 #define PAC_INTFLAGC_SERCOM4 (_U(0x1) << PAC_INTFLAGC_SERCOM4_Pos) 301 #define PAC_INTFLAGC_TCC0_Pos 5 /**< \brief (PAC_INTFLAGC) TCC0 */ 302 #define PAC_INTFLAGC_TCC0 (_U(0x1) << PAC_INTFLAGC_TCC0_Pos) 303 #define PAC_INTFLAGC_TCC1_Pos 6 /**< \brief (PAC_INTFLAGC) TCC1 */ 304 #define PAC_INTFLAGC_TCC1 (_U(0x1) << PAC_INTFLAGC_TCC1_Pos) 305 #define PAC_INTFLAGC_TCC2_Pos 7 /**< \brief (PAC_INTFLAGC) TCC2 */ 306 #define PAC_INTFLAGC_TCC2 (_U(0x1) << PAC_INTFLAGC_TCC2_Pos) 307 #define PAC_INTFLAGC_TC0_Pos 8 /**< \brief (PAC_INTFLAGC) TC0 */ 308 #define PAC_INTFLAGC_TC0 (_U(0x1) << PAC_INTFLAGC_TC0_Pos) 309 #define PAC_INTFLAGC_TC1_Pos 9 /**< \brief (PAC_INTFLAGC) TC1 */ 310 #define PAC_INTFLAGC_TC1 (_U(0x1) << PAC_INTFLAGC_TC1_Pos) 311 #define PAC_INTFLAGC_TC2_Pos 10 /**< \brief (PAC_INTFLAGC) TC2 */ 312 #define PAC_INTFLAGC_TC2 (_U(0x1) << PAC_INTFLAGC_TC2_Pos) 313 #define PAC_INTFLAGC_TC3_Pos 11 /**< \brief (PAC_INTFLAGC) TC3 */ 314 #define PAC_INTFLAGC_TC3 (_U(0x1) << PAC_INTFLAGC_TC3_Pos) 315 #define PAC_INTFLAGC_DAC_Pos 12 /**< \brief (PAC_INTFLAGC) DAC */ 316 #define PAC_INTFLAGC_DAC (_U(0x1) << PAC_INTFLAGC_DAC_Pos) 317 #define PAC_INTFLAGC_AES_Pos 13 /**< \brief (PAC_INTFLAGC) AES */ 318 #define PAC_INTFLAGC_AES (_U(0x1) << PAC_INTFLAGC_AES_Pos) 319 #define PAC_INTFLAGC_TRNG_Pos 14 /**< \brief (PAC_INTFLAGC) TRNG */ 320 #define PAC_INTFLAGC_TRNG (_U(0x1) << PAC_INTFLAGC_TRNG_Pos) 321 #define PAC_INTFLAGC_MASK _U(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */ 322 323 /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ 324 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 325 typedef union { // __I to avoid read-modify-write on write-to-clear register 326 struct { 327 __I uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ 328 __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ 329 __I uint32_t TC4_:1; /*!< bit: 2 TC4 */ 330 __I uint32_t ADC_:1; /*!< bit: 3 ADC */ 331 __I uint32_t AC_:1; /*!< bit: 4 AC */ 332 __I uint32_t PTC_:1; /*!< bit: 5 PTC */ 333 __I uint32_t OPAMP_:1; /*!< bit: 6 OPAMP */ 334 __I uint32_t CCL_:1; /*!< bit: 7 CCL */ 335 __I uint32_t :24; /*!< bit: 8..31 Reserved */ 336 } bit; /*!< Structure used for bit access */ 337 uint32_t reg; /*!< Type used for register access */ 338 } PAC_INTFLAGD_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */ 342 #define PAC_INTFLAGD_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */ 343 344 #define PAC_INTFLAGD_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGD) EVSYS */ 345 #define PAC_INTFLAGD_EVSYS (_U(0x1) << PAC_INTFLAGD_EVSYS_Pos) 346 #define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */ 347 #define PAC_INTFLAGD_SERCOM5 (_U(0x1) << PAC_INTFLAGD_SERCOM5_Pos) 348 #define PAC_INTFLAGD_TC4_Pos 2 /**< \brief (PAC_INTFLAGD) TC4 */ 349 #define PAC_INTFLAGD_TC4 (_U(0x1) << PAC_INTFLAGD_TC4_Pos) 350 #define PAC_INTFLAGD_ADC_Pos 3 /**< \brief (PAC_INTFLAGD) ADC */ 351 #define PAC_INTFLAGD_ADC (_U(0x1) << PAC_INTFLAGD_ADC_Pos) 352 #define PAC_INTFLAGD_AC_Pos 4 /**< \brief (PAC_INTFLAGD) AC */ 353 #define PAC_INTFLAGD_AC (_U(0x1) << PAC_INTFLAGD_AC_Pos) 354 #define PAC_INTFLAGD_PTC_Pos 5 /**< \brief (PAC_INTFLAGD) PTC */ 355 #define PAC_INTFLAGD_PTC (_U(0x1) << PAC_INTFLAGD_PTC_Pos) 356 #define PAC_INTFLAGD_OPAMP_Pos 6 /**< \brief (PAC_INTFLAGD) OPAMP */ 357 #define PAC_INTFLAGD_OPAMP (_U(0x1) << PAC_INTFLAGD_OPAMP_Pos) 358 #define PAC_INTFLAGD_CCL_Pos 7 /**< \brief (PAC_INTFLAGD) CCL */ 359 #define PAC_INTFLAGD_CCL (_U(0x1) << PAC_INTFLAGD_CCL_Pos) 360 #define PAC_INTFLAGD_MASK _U(0x000000FF) /**< \brief (PAC_INTFLAGD) MASK Register */ 361 362 /* -------- PAC_INTFLAGE : (PAC Offset: 0x24) (R/W 32) Peripheral interrupt flag status - Bridge E -------- */ 363 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 364 typedef union { // __I to avoid read-modify-write on write-to-clear register 365 struct { 366 __I uint32_t PAC_:1; /*!< bit: 0 PAC */ 367 __I uint32_t DMAC_:1; /*!< bit: 1 DMAC */ 368 __I uint32_t :30; /*!< bit: 2..31 Reserved */ 369 } bit; /*!< Structure used for bit access */ 370 uint32_t reg; /*!< Type used for register access */ 371 } PAC_INTFLAGE_Type; 372 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 373 374 #define PAC_INTFLAGE_OFFSET 0x24 /**< \brief (PAC_INTFLAGE offset) Peripheral interrupt flag status - Bridge E */ 375 #define PAC_INTFLAGE_RESETVALUE _U(0x00000000) /**< \brief (PAC_INTFLAGE reset_value) Peripheral interrupt flag status - Bridge E */ 376 377 #define PAC_INTFLAGE_PAC_Pos 0 /**< \brief (PAC_INTFLAGE) PAC */ 378 #define PAC_INTFLAGE_PAC (_U(0x1) << PAC_INTFLAGE_PAC_Pos) 379 #define PAC_INTFLAGE_DMAC_Pos 1 /**< \brief (PAC_INTFLAGE) DMAC */ 380 #define PAC_INTFLAGE_DMAC (_U(0x1) << PAC_INTFLAGE_DMAC_Pos) 381 #define PAC_INTFLAGE_MASK _U(0x00000003) /**< \brief (PAC_INTFLAGE) MASK Register */ 382 383 /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ 384 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 385 typedef union { 386 struct { 387 uint32_t PM_:1; /*!< bit: 0 PM APB Protect Enable */ 388 uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Protect Enable */ 389 uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Protect Enable */ 390 uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Protect Enable */ 391 uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Protect Enable */ 392 uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Protect Enable */ 393 uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Protect Enable */ 394 uint32_t WDT_:1; /*!< bit: 7 WDT APB Protect Enable */ 395 uint32_t RTC_:1; /*!< bit: 8 RTC APB Protect Enable */ 396 uint32_t EIC_:1; /*!< bit: 9 EIC APB Protect Enable */ 397 uint32_t PORT_:1; /*!< bit: 10 PORT APB Protect Enable */ 398 uint32_t TAL_:1; /*!< bit: 11 TAL APB Protect Enable */ 399 uint32_t :20; /*!< bit: 12..31 Reserved */ 400 } bit; /*!< Structure used for bit access */ 401 uint32_t reg; /*!< Type used for register access */ 402 } PAC_STATUSA_Type; 403 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 404 405 #define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ 406 #define PAC_STATUSA_RESETVALUE _U(0x00003000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ 407 408 #define PAC_STATUSA_PM_Pos 0 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ 409 #define PAC_STATUSA_PM (_U(0x1) << PAC_STATUSA_PM_Pos) 410 #define PAC_STATUSA_MCLK_Pos 1 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ 411 #define PAC_STATUSA_MCLK (_U(0x1) << PAC_STATUSA_MCLK_Pos) 412 #define PAC_STATUSA_RSTC_Pos 2 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ 413 #define PAC_STATUSA_RSTC (_U(0x1) << PAC_STATUSA_RSTC_Pos) 414 #define PAC_STATUSA_OSCCTRL_Pos 3 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ 415 #define PAC_STATUSA_OSCCTRL (_U(0x1) << PAC_STATUSA_OSCCTRL_Pos) 416 #define PAC_STATUSA_OSC32KCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ 417 #define PAC_STATUSA_OSC32KCTRL (_U(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) 418 #define PAC_STATUSA_SUPC_Pos 5 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ 419 #define PAC_STATUSA_SUPC (_U(0x1) << PAC_STATUSA_SUPC_Pos) 420 #define PAC_STATUSA_GCLK_Pos 6 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ 421 #define PAC_STATUSA_GCLK (_U(0x1) << PAC_STATUSA_GCLK_Pos) 422 #define PAC_STATUSA_WDT_Pos 7 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ 423 #define PAC_STATUSA_WDT (_U(0x1) << PAC_STATUSA_WDT_Pos) 424 #define PAC_STATUSA_RTC_Pos 8 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ 425 #define PAC_STATUSA_RTC (_U(0x1) << PAC_STATUSA_RTC_Pos) 426 #define PAC_STATUSA_EIC_Pos 9 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ 427 #define PAC_STATUSA_EIC (_U(0x1) << PAC_STATUSA_EIC_Pos) 428 #define PAC_STATUSA_PORT_Pos 10 /**< \brief (PAC_STATUSA) PORT APB Protect Enable */ 429 #define PAC_STATUSA_PORT (_U(0x1) << PAC_STATUSA_PORT_Pos) 430 #define PAC_STATUSA_TAL_Pos 11 /**< \brief (PAC_STATUSA) TAL APB Protect Enable */ 431 #define PAC_STATUSA_TAL (_U(0x1) << PAC_STATUSA_TAL_Pos) 432 #define PAC_STATUSA_MASK _U(0x00000FFF) /**< \brief (PAC_STATUSA) MASK Register */ 433 434 /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ 435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 436 typedef union { 437 struct { 438 uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ 439 uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ 440 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ 441 uint32_t MTB_:1; /*!< bit: 3 MTB APB Protect Enable */ 442 uint32_t :28; /*!< bit: 4..31 Reserved */ 443 } bit; /*!< Structure used for bit access */ 444 uint32_t reg; /*!< Type used for register access */ 445 } PAC_STATUSB_Type; 446 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 447 448 #define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ 449 #define PAC_STATUSB_RESETVALUE _U(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ 450 451 #define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */ 452 #define PAC_STATUSB_USB (_U(0x1) << PAC_STATUSB_USB_Pos) 453 #define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ 454 #define PAC_STATUSB_DSU (_U(0x1) << PAC_STATUSB_DSU_Pos) 455 #define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ 456 #define PAC_STATUSB_NVMCTRL (_U(0x1) << PAC_STATUSB_NVMCTRL_Pos) 457 #define PAC_STATUSB_MTB_Pos 3 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ 458 #define PAC_STATUSB_MTB (_U(0x1) << PAC_STATUSB_MTB_Pos) 459 #define PAC_STATUSB_MASK _U(0x0000000F) /**< \brief (PAC_STATUSB) MASK Register */ 460 461 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 463 typedef union { 464 struct { 465 uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Protect Enable */ 466 uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Protect Enable */ 467 uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Protect Enable */ 468 uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Protect Enable */ 469 uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Protect Enable */ 470 uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Protect Enable */ 471 uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Protect Enable */ 472 uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Protect Enable */ 473 uint32_t TC0_:1; /*!< bit: 8 TC0 APB Protect Enable */ 474 uint32_t TC1_:1; /*!< bit: 9 TC1 APB Protect Enable */ 475 uint32_t TC2_:1; /*!< bit: 10 TC2 APB Protect Enable */ 476 uint32_t TC3_:1; /*!< bit: 11 TC3 APB Protect Enable */ 477 uint32_t DAC_:1; /*!< bit: 12 DAC APB Protect Enable */ 478 uint32_t AES_:1; /*!< bit: 13 AES APB Protect Enable */ 479 uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Protect Enable */ 480 uint32_t :17; /*!< bit: 15..31 Reserved */ 481 } bit; /*!< Structure used for bit access */ 482 uint32_t reg; /*!< Type used for register access */ 483 } PAC_STATUSC_Type; 484 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 485 486 #define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ 487 #define PAC_STATUSC_RESETVALUE _U(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ 488 489 #define PAC_STATUSC_SERCOM0_Pos 0 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ 490 #define PAC_STATUSC_SERCOM0 (_U(0x1) << PAC_STATUSC_SERCOM0_Pos) 491 #define PAC_STATUSC_SERCOM1_Pos 1 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ 492 #define PAC_STATUSC_SERCOM1 (_U(0x1) << PAC_STATUSC_SERCOM1_Pos) 493 #define PAC_STATUSC_SERCOM2_Pos 2 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ 494 #define PAC_STATUSC_SERCOM2 (_U(0x1) << PAC_STATUSC_SERCOM2_Pos) 495 #define PAC_STATUSC_SERCOM3_Pos 3 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ 496 #define PAC_STATUSC_SERCOM3 (_U(0x1) << PAC_STATUSC_SERCOM3_Pos) 497 #define PAC_STATUSC_SERCOM4_Pos 4 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */ 498 #define PAC_STATUSC_SERCOM4 (_U(0x1) << PAC_STATUSC_SERCOM4_Pos) 499 #define PAC_STATUSC_TCC0_Pos 5 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ 500 #define PAC_STATUSC_TCC0 (_U(0x1) << PAC_STATUSC_TCC0_Pos) 501 #define PAC_STATUSC_TCC1_Pos 6 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ 502 #define PAC_STATUSC_TCC1 (_U(0x1) << PAC_STATUSC_TCC1_Pos) 503 #define PAC_STATUSC_TCC2_Pos 7 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ 504 #define PAC_STATUSC_TCC2 (_U(0x1) << PAC_STATUSC_TCC2_Pos) 505 #define PAC_STATUSC_TC0_Pos 8 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ 506 #define PAC_STATUSC_TC0 (_U(0x1) << PAC_STATUSC_TC0_Pos) 507 #define PAC_STATUSC_TC1_Pos 9 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ 508 #define PAC_STATUSC_TC1 (_U(0x1) << PAC_STATUSC_TC1_Pos) 509 #define PAC_STATUSC_TC2_Pos 10 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ 510 #define PAC_STATUSC_TC2 (_U(0x1) << PAC_STATUSC_TC2_Pos) 511 #define PAC_STATUSC_TC3_Pos 11 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ 512 #define PAC_STATUSC_TC3 (_U(0x1) << PAC_STATUSC_TC3_Pos) 513 #define PAC_STATUSC_DAC_Pos 12 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */ 514 #define PAC_STATUSC_DAC (_U(0x1) << PAC_STATUSC_DAC_Pos) 515 #define PAC_STATUSC_AES_Pos 13 /**< \brief (PAC_STATUSC) AES APB Protect Enable */ 516 #define PAC_STATUSC_AES (_U(0x1) << PAC_STATUSC_AES_Pos) 517 #define PAC_STATUSC_TRNG_Pos 14 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */ 518 #define PAC_STATUSC_TRNG (_U(0x1) << PAC_STATUSC_TRNG_Pos) 519 #define PAC_STATUSC_MASK _U(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */ 520 521 /* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef union { 524 struct { 525 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ 526 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ 527 uint32_t TC4_:1; /*!< bit: 2 TC4 APB Protect Enable */ 528 uint32_t ADC_:1; /*!< bit: 3 ADC APB Protect Enable */ 529 uint32_t AC_:1; /*!< bit: 4 AC APB Protect Enable */ 530 uint32_t PTC_:1; /*!< bit: 5 PTC APB Protect Enable */ 531 uint32_t OPAMP_:1; /*!< bit: 6 OPAMP APB Protect Enable */ 532 uint32_t CCL_:1; /*!< bit: 7 CCL APB Protect Enable */ 533 uint32_t :24; /*!< bit: 8..31 Reserved */ 534 } bit; /*!< Structure used for bit access */ 535 uint32_t reg; /*!< Type used for register access */ 536 } PAC_STATUSD_Type; 537 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 538 539 #define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */ 540 #define PAC_STATUSD_RESETVALUE _U(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */ 541 542 #define PAC_STATUSD_EVSYS_Pos 0 /**< \brief (PAC_STATUSD) EVSYS APB Protect Enable */ 543 #define PAC_STATUSD_EVSYS (_U(0x1) << PAC_STATUSD_EVSYS_Pos) 544 #define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */ 545 #define PAC_STATUSD_SERCOM5 (_U(0x1) << PAC_STATUSD_SERCOM5_Pos) 546 #define PAC_STATUSD_TC4_Pos 2 /**< \brief (PAC_STATUSD) TC4 APB Protect Enable */ 547 #define PAC_STATUSD_TC4 (_U(0x1) << PAC_STATUSD_TC4_Pos) 548 #define PAC_STATUSD_ADC_Pos 3 /**< \brief (PAC_STATUSD) ADC APB Protect Enable */ 549 #define PAC_STATUSD_ADC (_U(0x1) << PAC_STATUSD_ADC_Pos) 550 #define PAC_STATUSD_AC_Pos 4 /**< \brief (PAC_STATUSD) AC APB Protect Enable */ 551 #define PAC_STATUSD_AC (_U(0x1) << PAC_STATUSD_AC_Pos) 552 #define PAC_STATUSD_PTC_Pos 5 /**< \brief (PAC_STATUSD) PTC APB Protect Enable */ 553 #define PAC_STATUSD_PTC (_U(0x1) << PAC_STATUSD_PTC_Pos) 554 #define PAC_STATUSD_OPAMP_Pos 6 /**< \brief (PAC_STATUSD) OPAMP APB Protect Enable */ 555 #define PAC_STATUSD_OPAMP (_U(0x1) << PAC_STATUSD_OPAMP_Pos) 556 #define PAC_STATUSD_CCL_Pos 7 /**< \brief (PAC_STATUSD) CCL APB Protect Enable */ 557 #define PAC_STATUSD_CCL (_U(0x1) << PAC_STATUSD_CCL_Pos) 558 #define PAC_STATUSD_MASK _U(0x000000FF) /**< \brief (PAC_STATUSD) MASK Register */ 559 560 /* -------- PAC_STATUSE : (PAC Offset: 0x44) (R/ 32) Peripheral write protection status - Bridge E -------- */ 561 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 562 typedef union { 563 struct { 564 uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ 565 uint32_t DMAC_:1; /*!< bit: 1 DMAC APB Protect Enable */ 566 uint32_t :30; /*!< bit: 2..31 Reserved */ 567 } bit; /*!< Structure used for bit access */ 568 uint32_t reg; /*!< Type used for register access */ 569 } PAC_STATUSE_Type; 570 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 571 572 #define PAC_STATUSE_OFFSET 0x44 /**< \brief (PAC_STATUSE offset) Peripheral write protection status - Bridge E */ 573 #define PAC_STATUSE_RESETVALUE _U(0x00000000) /**< \brief (PAC_STATUSE reset_value) Peripheral write protection status - Bridge E */ 574 575 #define PAC_STATUSE_PAC_Pos 0 /**< \brief (PAC_STATUSE) PAC APB Protect Enable */ 576 #define PAC_STATUSE_PAC (_U(0x1) << PAC_STATUSE_PAC_Pos) 577 #define PAC_STATUSE_DMAC_Pos 1 /**< \brief (PAC_STATUSE) DMAC APB Protect Enable */ 578 #define PAC_STATUSE_DMAC (_U(0x1) << PAC_STATUSE_DMAC_Pos) 579 #define PAC_STATUSE_MASK _U(0x00000003) /**< \brief (PAC_STATUSE) MASK Register */ 580 581 /** \brief PAC hardware registers */ 582 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 583 typedef struct { 584 __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ 585 __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ 586 RoReg8 Reserved1[0x3]; 587 __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ 588 __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ 589 RoReg8 Reserved2[0x6]; 590 __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 591 __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 592 __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 593 __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 594 __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ 595 __IO PAC_INTFLAGE_Type INTFLAGE; /**< \brief Offset: 0x24 (R/W 32) Peripheral interrupt flag status - Bridge E */ 596 RoReg8 Reserved3[0xC]; 597 __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 598 __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 599 __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 600 __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ 601 __I PAC_STATUSE_Type STATUSE; /**< \brief Offset: 0x44 (R/ 32) Peripheral write protection status - Bridge E */ 602 } Pac; 603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 /*@}*/ 606 607 #endif /* _SAML21_PAC_COMPONENT_ */ 608
