Searched refs:GENCTRL (Results 1 – 2 of 2) sorted by relevance
139 ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; in hri_gclk_set_GENCTRL_GENEN_bit()146 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()155 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()158 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()165 ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; in hri_gclk_clear_GENCTRL_GENEN_bit()172 ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; in hri_gclk_toggle_GENCTRL_GENEN_bit()179 ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; in hri_gclk_set_GENCTRL_IDC_bit()186 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()195 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()198 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()[all …]
78 …uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control x Synchronization Bus… member240 …__IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Genera… member
