Searched refs:GCLK_PCHCTRL_CHEN_Pos (Results 1 – 7 of 7) sorted by relevance
| /loramac-node-3.4.0/src/boards/SAMR34/ |
| D | uart-board.c | 39 …TRL_reg( GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in UartMcuInit()
40 …TRL_reg( GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in UartMcuInit()
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| D | i2c-board.c | 49 CONF_GCLK_SERCOM1_CORE_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in I2cMcuInit()
51 CONF_GCLK_SERCOM1_SLOW_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in I2cMcuInit()
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| D | spi-board.c | 34 …TRL_reg( GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in SpiInit()
35 …TRL_reg( GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) ); in SpiInit()
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| D | board.c | 79 …hri_gclk_write_PCHCTRL_reg( GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) … in BoardInitMcu()
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| /loramac-node-3.4.0/src/boards/mcu/saml21/hpl/oscctrl/ |
| D | hpl_oscctrl.c | 110 …hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK… in _oscctrl_init_referenced_generators()
139 …hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK… in _oscctrl_init_referenced_generators()
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| /loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/ |
| D | gclk.h | 227 #define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */ macro
228 #define GCLK_PCHCTRL_CHEN (_U(0x1) << GCLK_PCHCTRL_CHEN_Pos)
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| /loramac-node-3.4.0/src/boards/mcu/saml21/hri/ |
| D | hri_gclk_l21.h | 527 tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; in hri_gclk_get_PCHCTRL_CHEN_bit()
537 tmp |= value << GCLK_PCHCTRL_CHEN_Pos; in hri_gclk_write_PCHCTRL_CHEN_bit()
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