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Searched refs:GCLK_GENCTRL_DIVSEL_Pos (Results 1 – 3 of 3) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/hpl/gclk/
Dhpl_gclk.c61 | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
73 | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
85 | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
97 | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
109 | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
121 | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
133 | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
145 | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
157 | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) in _gclk_init_generators()
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dgclk.h182 #define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */ macro
183 #define GCLK_GENCTRL_DIVSEL (_U(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_gclk_l21.h307 tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; in hri_gclk_get_GENCTRL_DIVSEL_bit()
317 tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; in hri_gclk_write_GENCTRL_DIVSEL_bit()