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Searched refs:GCLK_GENCTRL_DIVSEL (Results 1 – 2 of 2) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_gclk_l21.h299 ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; in hri_gclk_set_GENCTRL_DIVSEL_bit()
307 tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; in hri_gclk_get_GENCTRL_DIVSEL_bit()
316 tmp &= ~GCLK_GENCTRL_DIVSEL; in hri_gclk_write_GENCTRL_DIVSEL_bit()
325 ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; in hri_gclk_clear_GENCTRL_DIVSEL_bit()
332 ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; in hri_gclk_toggle_GENCTRL_DIVSEL_bit()
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dgclk.h183 #define GCLK_GENCTRL_DIVSEL (_U(0x1) << GCLK_GENCTRL_DIVSEL_Pos) macro