1 /** 2 * \file 3 * 4 * \brief Component description for NVMCTRL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_NVMCTRL_COMPONENT_ 30 #define _SAML21_NVMCTRL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR NVMCTRL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_NVMCTRL Non-Volatile Memory Controller */ 36 /*@{*/ 37 38 #define NVMCTRL_U2207 39 #define REV_NVMCTRL 0x302 40 41 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 46 uint16_t :1; /*!< bit: 7 Reserved */ 47 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 48 } bit; /*!< Structure used for bit access */ 49 uint16_t reg; /*!< Type used for register access */ 50 } NVMCTRL_CTRLA_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ 54 #define NVMCTRL_CTRLA_RESETVALUE _U(0x0000) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ 55 56 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ 57 #define NVMCTRL_CTRLA_CMD_Msk (_U(0x7F) << NVMCTRL_CTRLA_CMD_Pos) 58 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) 59 #define NVMCTRL_CTRLA_CMD_ER_Val _U(0x2) /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ 60 #define NVMCTRL_CTRLA_CMD_WP_Val _U(0x4) /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 61 #define NVMCTRL_CTRLA_CMD_EAR_Val _U(0x5) /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 62 #define NVMCTRL_CTRLA_CMD_WAP_Val _U(0x6) /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 63 #define NVMCTRL_CTRLA_CMD_SF_Val _U(0xA) /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ 64 #define NVMCTRL_CTRLA_CMD_WL_Val _U(0xF) /**< \brief (NVMCTRL_CTRLA) Write lockbits */ 65 #define NVMCTRL_CTRLA_CMD_RWWEEER_Val _U(0x1A) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */ 66 #define NVMCTRL_CTRLA_CMD_RWWEEWP_Val _U(0x1C) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 67 #define NVMCTRL_CTRLA_CMD_LR_Val _U(0x40) /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ 68 #define NVMCTRL_CTRLA_CMD_UR_Val _U(0x41) /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 69 #define NVMCTRL_CTRLA_CMD_SPRM_Val _U(0x42) /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ 70 #define NVMCTRL_CTRLA_CMD_CPRM_Val _U(0x43) /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ 71 #define NVMCTRL_CTRLA_CMD_PBC_Val _U(0x44) /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ 72 #define NVMCTRL_CTRLA_CMD_SSB_Val _U(0x45) /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ 73 #define NVMCTRL_CTRLA_CMD_INVALL_Val _U(0x46) /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ 74 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) 75 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) 76 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) 77 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) 78 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) 79 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) 80 #define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos) 81 #define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos) 82 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) 83 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) 84 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 85 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 86 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) 87 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) 88 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) 89 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ 90 #define NVMCTRL_CTRLA_CMDEX_Msk (_U(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos) 91 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) 92 #define NVMCTRL_CTRLA_CMDEX_KEY_Val _U(0xA5) /**< \brief (NVMCTRL_CTRLA) Execution Key */ 93 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) 94 #define NVMCTRL_CTRLA_MASK _U(0xFF7F) /**< \brief (NVMCTRL_CTRLA) MASK Register */ 95 96 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t :1; /*!< bit: 0 Reserved */ 101 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ 102 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 103 uint32_t MANW:1; /*!< bit: 7 Manual Write */ 104 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ 105 uint32_t :1; /*!< bit: 10 Reserved */ 106 uint32_t FWUP:1; /*!< bit: 11 fast wake-up */ 107 uint32_t :4; /*!< bit: 12..15 Reserved */ 108 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ 109 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ 110 uint32_t :13; /*!< bit: 19..31 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } NVMCTRL_CTRLB_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ 117 #define NVMCTRL_CTRLB_RESETVALUE _U(0x00000080) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ 118 119 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ 120 #define NVMCTRL_CTRLB_RWS_Msk (_U(0xF) << NVMCTRL_CTRLB_RWS_Pos) 121 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) 122 #define NVMCTRL_CTRLB_RWS_SINGLE_Val _U(0x0) /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ 123 #define NVMCTRL_CTRLB_RWS_HALF_Val _U(0x1) /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ 124 #define NVMCTRL_CTRLB_RWS_DUAL_Val _U(0x2) /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ 125 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) 126 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) 127 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) 128 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ 129 #define NVMCTRL_CTRLB_MANW (_U(0x1) << NVMCTRL_CTRLB_MANW_Pos) 130 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ 131 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (_U(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos) 132 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)) 133 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U(0x0) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ 134 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U(0x1) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ 135 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U(0x3) /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ 136 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 137 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 138 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 139 #define NVMCTRL_CTRLB_FWUP_Pos 11 /**< \brief (NVMCTRL_CTRLB) fast wake-up */ 140 #define NVMCTRL_CTRLB_FWUP (_U(0x1) << NVMCTRL_CTRLB_FWUP_Pos) 141 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ 142 #define NVMCTRL_CTRLB_READMODE_Msk (_U(0x3) << NVMCTRL_CTRLB_READMODE_Pos) 143 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)) 144 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U(0x0) /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ 145 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U(0x1) /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ 146 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U(0x2) /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ 147 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) 148 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) 149 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) 150 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ 151 #define NVMCTRL_CTRLB_CACHEDIS (_U(0x1) << NVMCTRL_CTRLB_CACHEDIS_Pos) 152 #define NVMCTRL_CTRLB_MASK _U(0x00070B9E) /**< \brief (NVMCTRL_CTRLB) MASK Register */ 153 154 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { 157 struct { 158 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 159 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 160 uint32_t :1; /*!< bit: 19 Reserved */ 161 uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } NVMCTRL_PARAM_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ 168 #define NVMCTRL_PARAM_RESETVALUE _U(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ 169 170 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ 171 #define NVMCTRL_PARAM_NVMP_Msk (_U(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) 172 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) 173 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ 174 #define NVMCTRL_PARAM_PSZ_Msk (_U(0x7) << NVMCTRL_PARAM_PSZ_Pos) 175 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) 176 #define NVMCTRL_PARAM_PSZ_8_Val _U(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */ 177 #define NVMCTRL_PARAM_PSZ_16_Val _U(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */ 178 #define NVMCTRL_PARAM_PSZ_32_Val _U(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */ 179 #define NVMCTRL_PARAM_PSZ_64_Val _U(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */ 180 #define NVMCTRL_PARAM_PSZ_128_Val _U(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */ 181 #define NVMCTRL_PARAM_PSZ_256_Val _U(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */ 182 #define NVMCTRL_PARAM_PSZ_512_Val _U(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */ 183 #define NVMCTRL_PARAM_PSZ_1024_Val _U(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */ 184 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) 185 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) 186 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) 187 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) 188 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) 189 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) 190 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) 191 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) 192 #define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */ 193 #define NVMCTRL_PARAM_RWWEEP_Msk (_U(0xFFF) << NVMCTRL_PARAM_RWWEEP_Pos) 194 #define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos)) 195 #define NVMCTRL_PARAM_MASK _U(0xFFF7FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */ 196 197 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 202 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 203 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 204 } bit; /*!< Structure used for bit access */ 205 uint8_t reg; /*!< Type used for register access */ 206 } NVMCTRL_INTENCLR_Type; 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 208 209 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ 210 #define NVMCTRL_INTENCLR_RESETVALUE _U(0x00) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 211 212 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ 213 #define NVMCTRL_INTENCLR_READY (_U(0x1) << NVMCTRL_INTENCLR_READY_Pos) 214 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ 215 #define NVMCTRL_INTENCLR_ERROR (_U(0x1) << NVMCTRL_INTENCLR_ERROR_Pos) 216 #define NVMCTRL_INTENCLR_MASK _U(0x03) /**< \brief (NVMCTRL_INTENCLR) MASK Register */ 217 218 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { 221 struct { 222 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 223 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 224 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 225 } bit; /*!< Structure used for bit access */ 226 uint8_t reg; /*!< Type used for register access */ 227 } NVMCTRL_INTENSET_Type; 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ 231 #define NVMCTRL_INTENSET_RESETVALUE _U(0x00) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ 232 233 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ 234 #define NVMCTRL_INTENSET_READY (_U(0x1) << NVMCTRL_INTENSET_READY_Pos) 235 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ 236 #define NVMCTRL_INTENSET_ERROR (_U(0x1) << NVMCTRL_INTENSET_ERROR_Pos) 237 #define NVMCTRL_INTENSET_MASK _U(0x03) /**< \brief (NVMCTRL_INTENSET) MASK Register */ 238 239 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { // __I to avoid read-modify-write on write-to-clear register 242 struct { 243 __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ 244 __I uint8_t ERROR:1; /*!< bit: 1 Error */ 245 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 246 } bit; /*!< Structure used for bit access */ 247 uint8_t reg; /*!< Type used for register access */ 248 } NVMCTRL_INTFLAG_Type; 249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 250 251 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 252 #define NVMCTRL_INTFLAG_RESETVALUE _U(0x00) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 253 254 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ 255 #define NVMCTRL_INTFLAG_READY (_U(0x1) << NVMCTRL_INTFLAG_READY_Pos) 256 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ 257 #define NVMCTRL_INTFLAG_ERROR (_U(0x1) << NVMCTRL_INTFLAG_ERROR_Pos) 258 #define NVMCTRL_INTFLAG_MASK _U(0x03) /**< \brief (NVMCTRL_INTFLAG) MASK Register */ 259 260 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ 261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 262 typedef union { 263 struct { 264 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ 265 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ 266 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ 267 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ 268 uint16_t NVME:1; /*!< bit: 4 NVM Error */ 269 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 270 uint16_t SB:1; /*!< bit: 8 Security Bit Status */ 271 uint16_t :7; /*!< bit: 9..15 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 uint16_t reg; /*!< Type used for register access */ 274 } NVMCTRL_STATUS_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ 278 #define NVMCTRL_STATUS_RESETVALUE _U(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */ 279 280 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ 281 #define NVMCTRL_STATUS_PRM (_U(0x1) << NVMCTRL_STATUS_PRM_Pos) 282 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ 283 #define NVMCTRL_STATUS_LOAD (_U(0x1) << NVMCTRL_STATUS_LOAD_Pos) 284 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ 285 #define NVMCTRL_STATUS_PROGE (_U(0x1) << NVMCTRL_STATUS_PROGE_Pos) 286 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ 287 #define NVMCTRL_STATUS_LOCKE (_U(0x1) << NVMCTRL_STATUS_LOCKE_Pos) 288 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ 289 #define NVMCTRL_STATUS_NVME (_U(0x1) << NVMCTRL_STATUS_NVME_Pos) 290 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ 291 #define NVMCTRL_STATUS_SB (_U(0x1) << NVMCTRL_STATUS_SB_Pos) 292 #define NVMCTRL_STATUS_MASK _U(0x011F) /**< \brief (NVMCTRL_STATUS) MASK Register */ 293 294 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ 295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 296 typedef union { 297 struct { 298 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ 299 uint32_t :10; /*!< bit: 22..31 Reserved */ 300 } bit; /*!< Structure used for bit access */ 301 uint32_t reg; /*!< Type used for register access */ 302 } NVMCTRL_ADDR_Type; 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ 306 #define NVMCTRL_ADDR_RESETVALUE _U(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */ 307 308 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ 309 #define NVMCTRL_ADDR_ADDR_Msk (_U(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos) 310 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) 311 #define NVMCTRL_ADDR_MASK _U(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */ 312 313 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ 314 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 315 typedef union { 316 struct { 317 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ 318 } bit; /*!< Structure used for bit access */ 319 uint16_t reg; /*!< Type used for register access */ 320 } NVMCTRL_LOCK_Type; 321 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 322 323 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ 324 325 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ 326 #define NVMCTRL_LOCK_LOCK_Msk (_U(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos) 327 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) 328 #define NVMCTRL_LOCK_MASK _U(0xFFFF) /**< \brief (NVMCTRL_LOCK) MASK Register */ 329 330 /** \brief NVMCTRL APB hardware registers */ 331 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 332 typedef struct { 333 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 334 RoReg8 Reserved1[0x2]; 335 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ 336 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ 337 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 338 RoReg8 Reserved2[0x3]; 339 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ 340 RoReg8 Reserved3[0x3]; 341 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ 342 RoReg8 Reserved4[0x3]; 343 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ 344 RoReg8 Reserved5[0x2]; 345 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ 346 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ 347 } Nvmctrl; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #ifdef __GNUC__ 351 #define SECTION_NVMCTRL_CAL __attribute__ ((section(".flash"))) 352 #elif defined(__ICCARM__) 353 #define SECTION_NVMCTRL_CAL @".flash" 354 #endif 355 356 #ifdef __GNUC__ 357 #define SECTION_NVMCTRL_LOCKBIT __attribute__ ((section(".flash"))) 358 #elif defined(__ICCARM__) 359 #define SECTION_NVMCTRL_LOCKBIT @".flash" 360 #endif 361 362 #ifdef __GNUC__ 363 #define SECTION_NVMCTRL_OTP1 __attribute__ ((section(".flash"))) 364 #elif defined(__ICCARM__) 365 #define SECTION_NVMCTRL_OTP1 @".flash" 366 #endif 367 368 #ifdef __GNUC__ 369 #define SECTION_NVMCTRL_OTP2 __attribute__ ((section(".flash"))) 370 #elif defined(__ICCARM__) 371 #define SECTION_NVMCTRL_OTP2 @".flash" 372 #endif 373 374 #ifdef __GNUC__ 375 #define SECTION_NVMCTRL_OTP3 __attribute__ ((section(".flash"))) 376 #elif defined(__ICCARM__) 377 #define SECTION_NVMCTRL_OTP3 @".flash" 378 #endif 379 380 #ifdef __GNUC__ 381 #define SECTION_NVMCTRL_OTP4 __attribute__ ((section(".flash"))) 382 #elif defined(__ICCARM__) 383 #define SECTION_NVMCTRL_OTP4 @".flash" 384 #endif 385 386 #ifdef __GNUC__ 387 #define SECTION_NVMCTRL_OTP5 __attribute__ ((section(".flash"))) 388 #elif defined(__ICCARM__) 389 #define SECTION_NVMCTRL_OTP5 @".flash" 390 #endif 391 392 #ifdef __GNUC__ 393 #define SECTION_NVMCTRL_TEMP_LOG __attribute__ ((section(".flash"))) 394 #elif defined(__ICCARM__) 395 #define SECTION_NVMCTRL_TEMP_LOG @".flash" 396 #endif 397 398 #ifdef __GNUC__ 399 #define SECTION_NVMCTRL_USER __attribute__ ((section(".flash"))) 400 #elif defined(__ICCARM__) 401 #define SECTION_NVMCTRL_USER @".flash" 402 #endif 403 404 /*@}*/ 405 406 /* ************************************************************************** */ 407 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 408 /* ************************************************************************** */ 409 /** \addtogroup fuses_api Peripheral Software API */ 410 /*@{*/ 411 412 413 #define ADC_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5 414 #define ADC_FUSES_BIASCOMP_Pos 3 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */ 415 #define ADC_FUSES_BIASCOMP_Msk (_U(0x7) << ADC_FUSES_BIASCOMP_Pos) 416 #define ADC_FUSES_BIASCOMP(value) (ADC_FUSES_BIASCOMP_Msk & ((value) << ADC_FUSES_BIASCOMP_Pos)) 417 418 #define ADC_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5 419 #define ADC_FUSES_BIASREFBUF_Pos 0 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */ 420 #define ADC_FUSES_BIASREFBUF_Msk (_U(0x7) << ADC_FUSES_BIASREFBUF_Pos) 421 #define ADC_FUSES_BIASREFBUF(value) (ADC_FUSES_BIASREFBUF_Msk & ((value) << ADC_FUSES_BIASREFBUF_Pos)) 422 423 #define FUSES_BOD12_DIS_ADDR NVMCTRL_USER 424 #define FUSES_BOD12_DIS_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Disable */ 425 #define FUSES_BOD12_DIS_Msk (_U(0x1) << FUSES_BOD12_DIS_Pos) 426 427 #define FUSES_BOD12_HYST_ADDR (NVMCTRL_USER + 4) 428 #define FUSES_BOD12_HYST_Pos 10 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */ 429 #define FUSES_BOD12_HYST_Msk (_U(0x1) << FUSES_BOD12_HYST_Pos) 430 431 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER 432 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ 433 #define FUSES_BOD33USERLEVEL_Msk (_U(0x3F) << FUSES_BOD33USERLEVEL_Pos) 434 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)) 435 436 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER 437 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ 438 #define FUSES_BOD33_ACTION_Msk (_U(0x3) << FUSES_BOD33_ACTION_Pos) 439 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)) 440 441 #define FUSES_BOD33_DIS_ADDR NVMCTRL_USER 442 #define FUSES_BOD33_DIS_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Disable */ 443 #define FUSES_BOD33_DIS_Msk (_U(0x1) << FUSES_BOD33_DIS_Pos) 444 445 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) 446 #define FUSES_BOD33_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ 447 #define FUSES_BOD33_HYST_Msk (_U(0x1) << FUSES_BOD33_HYST_Pos) 448 449 #define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 450 #define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ 451 #define FUSES_HOT_ADC_VAL_Msk (_U(0xFFF) << FUSES_HOT_ADC_VAL_Pos) 452 #define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)) 453 454 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 455 #define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ 456 #define FUSES_HOT_INT1V_VAL_Msk (_U(0xFF) << FUSES_HOT_INT1V_VAL_Pos) 457 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)) 458 459 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 460 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ 461 #define FUSES_HOT_TEMP_VAL_DEC_Msk (_U(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos) 462 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)) 463 464 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 465 #define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ 466 #define FUSES_HOT_TEMP_VAL_INT_Msk (_U(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos) 467 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)) 468 469 #define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 470 #define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ 471 #define FUSES_ROOM_ADC_VAL_Msk (_U(0xFFF) << FUSES_ROOM_ADC_VAL_Pos) 472 #define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)) 473 474 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG 475 #define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ 476 #define FUSES_ROOM_INT1V_VAL_Msk (_U(0xFF) << FUSES_ROOM_INT1V_VAL_Pos) 477 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)) 478 479 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 480 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ 481 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos) 482 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)) 483 484 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 485 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ 486 #define FUSES_ROOM_TEMP_VAL_INT_Msk (_U(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos) 487 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)) 488 489 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER 490 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ 491 #define NVMCTRL_FUSES_BOOTPROT_Msk (_U(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos) 492 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)) 493 494 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER 495 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ 496 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos) 497 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)) 498 499 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) 500 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ 501 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos) 502 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)) 503 504 #define USB_FUSES_TRANSN_ADDR NVMCTRL_OTP5 505 #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP5) USB pad Transn calibration */ 506 #define USB_FUSES_TRANSN_Msk (_U(0x1F) << USB_FUSES_TRANSN_Pos) 507 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)) 508 509 #define USB_FUSES_TRANSP_ADDR NVMCTRL_OTP5 510 #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP5) USB pad Transp calibration */ 511 #define USB_FUSES_TRANSP_Msk (_U(0x1F) << USB_FUSES_TRANSP_Pos) 512 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)) 513 514 #define USB_FUSES_TRIM_ADDR NVMCTRL_OTP5 515 #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP5) USB pad Trim calibration */ 516 #define USB_FUSES_TRIM_Msk (_U(0x7) << USB_FUSES_TRIM_Pos) 517 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)) 518 519 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER 520 #define WDT_FUSES_ALWAYSON_Pos 27 /**< \brief (NVMCTRL_USER) WDT Always On */ 521 #define WDT_FUSES_ALWAYSON_Msk (_U(0x1) << WDT_FUSES_ALWAYSON_Pos) 522 523 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER 524 #define WDT_FUSES_ENABLE_Pos 26 /**< \brief (NVMCTRL_USER) WDT Enable */ 525 #define WDT_FUSES_ENABLE_Msk (_U(0x1) << WDT_FUSES_ENABLE_Pos) 526 527 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) 528 #define WDT_FUSES_EWOFFSET_Pos 4 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ 529 #define WDT_FUSES_EWOFFSET_Msk (_U(0xF) << WDT_FUSES_EWOFFSET_Pos) 530 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) 531 532 #define WDT_FUSES_PER_ADDR NVMCTRL_USER 533 #define WDT_FUSES_PER_Pos 28 /**< \brief (NVMCTRL_USER) WDT Period */ 534 #define WDT_FUSES_PER_Msk (_U(0xF) << WDT_FUSES_PER_Pos) 535 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) 536 537 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) 538 #define WDT_FUSES_WEN_Pos 8 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ 539 #define WDT_FUSES_WEN_Msk (_U(0x1) << WDT_FUSES_WEN_Pos) 540 541 #define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4) 542 #define WDT_FUSES_WINDOW_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window */ 543 #define WDT_FUSES_WINDOW_Msk (_U(0xF) << WDT_FUSES_WINDOW_Pos) 544 #define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos)) 545 546 /*@}*/ 547 548 #endif /* _SAML21_NVMCTRL_COMPONENT_ */ 549
