1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Copyright (c) 2019 Centaur Analytics, Inc
5 * Copyright (c) 2023 Google Inc
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #include <zephyr/kernel.h>
11 #include <zephyr/device.h>
12
13 #define DT_DRV_COMPAT st_stm32_flash_controller
14
15 #include <string.h>
16 #include <zephyr/drivers/flash.h>
17 #include <zephyr/drivers/flash/stm32_flash_api_extensions.h>
18 #include <zephyr/init.h>
19 #include <soc.h>
20 #include <stm32_ll_bus.h>
21 #include <stm32_ll_rcc.h>
22 #include <zephyr/logging/log.h>
23
24 #include "flash_stm32.h"
25
26 LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
27
28 /* Let's wait for double the max erase time to be sure that the operation is
29 * completed.
30 */
31 #define STM32_FLASH_TIMEOUT \
32 (2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
33
34 static const struct flash_parameters flash_stm32_parameters = {
35 .write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
36 /* Some SoCs (L0/L1) use an EEPROM under the hood. Distinguish
37 * between them based on the presence of the PECR register. */
38 #if defined(FLASH_PECR_ERASE)
39 .erase_value = 0,
40 #else
41 .erase_value = 0xff,
42 #endif
43 };
44
45 static int flash_stm32_write_protection(const struct device *dev, bool enable);
46
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)47 bool __weak flash_stm32_valid_range(const struct device *dev, off_t offset,
48 uint32_t len, bool write)
49 {
50 if (write && !flash_stm32_valid_write(offset, len)) {
51 return false;
52 }
53 return flash_stm32_range_exists(dev, offset, len);
54 }
55
flash_stm32_check_configuration(void)56 int __weak flash_stm32_check_configuration(void)
57 {
58 return 0;
59 }
60
61
62 #if !defined(CONFIG_SOC_SERIES_STM32WBX)
flash_stm32_check_status(const struct device * dev)63 static int flash_stm32_check_status(const struct device *dev)
64 {
65
66 if (FLASH_STM32_REGS(dev)->FLASH_STM32_SR & FLASH_STM32_SR_ERRORS) {
67 LOG_DBG("Status: 0x%08lx",
68 (unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
69 FLASH_STM32_SR_ERRORS);
70 /* Clear errors to unblock usage of the flash */
71 FLASH_STM32_REGS(dev)->FLASH_STM32_SR = FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
72 FLASH_STM32_SR_ERRORS;
73 return -EIO;
74 }
75
76 return 0;
77 }
78 #endif /* CONFIG_SOC_SERIES_STM32WBX */
79
flash_stm32_wait_flash_idle(const struct device * dev)80 int flash_stm32_wait_flash_idle(const struct device *dev)
81 {
82 int64_t timeout_time = k_uptime_get() + STM32_FLASH_TIMEOUT;
83 int rc;
84 uint32_t busy_flags;
85
86 rc = flash_stm32_check_status(dev);
87 if (rc < 0) {
88 return -EIO;
89 }
90
91 busy_flags = FLASH_STM32_SR_BUSY;
92
93 /* Some Series can't modify FLASH_CR reg while CFGBSY is set. Wait as well */
94 #if defined(FLASH_STM32_SR_CFGBSY)
95 busy_flags |= FLASH_STM32_SR_CFGBSY;
96 #endif
97
98 while ((FLASH_STM32_REGS(dev)->FLASH_STM32_SR & busy_flags)) {
99 if (k_uptime_get() > timeout_time) {
100 LOG_ERR("Timeout! val: %d", STM32_FLASH_TIMEOUT);
101 return -EIO;
102 }
103 }
104
105 return 0;
106 }
107
flash_stm32_flush_caches(const struct device * dev,off_t offset,size_t len)108 static void flash_stm32_flush_caches(const struct device *dev,
109 off_t offset, size_t len)
110 {
111 #if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
112 defined(CONFIG_SOC_SERIES_STM32G0X) || defined(CONFIG_SOC_SERIES_STM32L5X) || \
113 defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32H5X)
114 ARG_UNUSED(dev);
115 ARG_UNUSED(offset);
116 ARG_UNUSED(len);
117 #elif defined(CONFIG_SOC_SERIES_STM32F4X) || \
118 defined(CONFIG_SOC_SERIES_STM32L4X) || \
119 defined(CONFIG_SOC_SERIES_STM32WBX) || \
120 defined(CONFIG_SOC_SERIES_STM32G4X)
121 ARG_UNUSED(offset);
122 ARG_UNUSED(len);
123
124 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
125
126 if (regs->ACR & FLASH_ACR_DCEN) {
127 regs->ACR &= ~FLASH_ACR_DCEN;
128 regs->ACR |= FLASH_ACR_DCRST;
129 regs->ACR &= ~FLASH_ACR_DCRST;
130 regs->ACR |= FLASH_ACR_DCEN;
131 }
132 #elif defined(CONFIG_SOC_SERIES_STM32F7X)
133 SCB_InvalidateDCache_by_Addr((uint32_t *)(FLASH_STM32_BASE_ADDRESS
134 + offset), len);
135 #endif
136 }
137
flash_stm32_read(const struct device * dev,off_t offset,void * data,size_t len)138 static int flash_stm32_read(const struct device *dev, off_t offset,
139 void *data,
140 size_t len)
141 {
142 if (!flash_stm32_valid_range(dev, offset, len, false)) {
143 LOG_ERR("Read range invalid. Offset: %ld, len: %zu",
144 (long int) offset, len);
145 return -EINVAL;
146 }
147
148 if (!len) {
149 return 0;
150 }
151
152 LOG_DBG("Read offset: %ld, len: %zu", (long int) offset, len);
153
154 memcpy(data, (uint8_t *) FLASH_STM32_BASE_ADDRESS + offset, len);
155
156 return 0;
157 }
158
flash_stm32_erase(const struct device * dev,off_t offset,size_t len)159 static int flash_stm32_erase(const struct device *dev, off_t offset,
160 size_t len)
161 {
162 int rc;
163
164 if (!flash_stm32_valid_range(dev, offset, len, true)) {
165 LOG_ERR("Erase range invalid. Offset: %ld, len: %zu",
166 (long int) offset, len);
167 return -EINVAL;
168 }
169
170 if (!len) {
171 return 0;
172 }
173
174 flash_stm32_sem_take(dev);
175
176 LOG_DBG("Erase offset: %ld, len: %zu", (long int) offset, len);
177
178 rc = flash_stm32_write_protection(dev, false);
179 if (rc == 0) {
180 rc = flash_stm32_block_erase_loop(dev, offset, len);
181 }
182
183 flash_stm32_flush_caches(dev, offset, len);
184
185 int rc2 = flash_stm32_write_protection(dev, true);
186
187 if (!rc) {
188 rc = rc2;
189 }
190
191 flash_stm32_sem_give(dev);
192
193 return rc;
194 }
195
flash_stm32_write(const struct device * dev,off_t offset,const void * data,size_t len)196 static int flash_stm32_write(const struct device *dev, off_t offset,
197 const void *data, size_t len)
198 {
199 int rc;
200
201 if (!flash_stm32_valid_range(dev, offset, len, true)) {
202 LOG_ERR("Write range invalid. Offset: %ld, len: %zu",
203 (long int) offset, len);
204 return -EINVAL;
205 }
206
207 if (!len) {
208 return 0;
209 }
210
211 flash_stm32_sem_take(dev);
212
213 LOG_DBG("Write offset: %ld, len: %zu", (long int) offset, len);
214
215 rc = flash_stm32_write_protection(dev, false);
216 if (rc == 0) {
217 rc = flash_stm32_write_range(dev, offset, data, len);
218 }
219
220 int rc2 = flash_stm32_write_protection(dev, true);
221
222 if (!rc) {
223 rc = rc2;
224 }
225
226 flash_stm32_sem_give(dev);
227
228 return rc;
229 }
230
flash_stm32_write_protection(const struct device * dev,bool enable)231 static int flash_stm32_write_protection(const struct device *dev, bool enable)
232 {
233 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
234
235 int rc = 0;
236
237 if (enable) {
238 rc = flash_stm32_wait_flash_idle(dev);
239 if (rc) {
240 flash_stm32_sem_give(dev);
241 return rc;
242 }
243 }
244
245 #if defined(FLASH_SECURITY_NS)
246 if (enable) {
247 regs->NSCR |= FLASH_STM32_NSLOCK;
248 } else {
249 if (regs->NSCR & FLASH_STM32_NSLOCK) {
250 regs->NSKEYR = FLASH_KEY1;
251 regs->NSKEYR = FLASH_KEY2;
252 }
253 }
254 #elif defined(FLASH_CR_LOCK)
255 if (enable) {
256 regs->CR |= FLASH_CR_LOCK;
257 } else {
258 if (regs->CR & FLASH_CR_LOCK) {
259 regs->KEYR = FLASH_KEY1;
260 regs->KEYR = FLASH_KEY2;
261 }
262 }
263 #else
264 if (enable) {
265 regs->PECR |= FLASH_PECR_PRGLOCK;
266 regs->PECR |= FLASH_PECR_PELOCK;
267 } else {
268 if (regs->PECR & FLASH_PECR_PRGLOCK) {
269 LOG_DBG("Disabling write protection");
270 regs->PEKEYR = FLASH_PEKEY1;
271 regs->PEKEYR = FLASH_PEKEY2;
272 regs->PRGKEYR = FLASH_PRGKEY1;
273 regs->PRGKEYR = FLASH_PRGKEY2;
274 }
275 if (FLASH->PECR & FLASH_PECR_PRGLOCK) {
276 LOG_ERR("Unlock failed");
277 rc = -EIO;
278 }
279 }
280 #endif /* FLASH_SECURITY_NS */
281
282 if (enable) {
283 LOG_DBG("Enable write protection");
284 } else {
285 LOG_DBG("Disable write protection");
286 }
287
288 return rc;
289 }
290
flash_stm32_option_bytes_lock(const struct device * dev,bool enable)291 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
292 {
293 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
294
295 #if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */
296 if (enable) {
297 regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
298 } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
299 regs->OPTKEYR = FLASH_OPT_KEY1;
300 regs->OPTKEYR = FLASH_OPT_KEY2;
301 }
302 #else
303 int rc;
304
305 /* Unlock CR/PECR/NSCR register if needed. */
306 if (!enable) {
307 rc = flash_stm32_write_protection(dev, false);
308 if (rc) {
309 return rc;
310 }
311 }
312 #if defined(FLASH_CR_OPTWRE) /* F0, F1 and F3 */
313 if (enable) {
314 regs->CR &= ~FLASH_CR_OPTWRE;
315 } else if (!(regs->CR & FLASH_CR_OPTWRE)) {
316 regs->OPTKEYR = FLASH_OPTKEY1;
317 regs->OPTKEYR = FLASH_OPTKEY2;
318 }
319 #elif defined(FLASH_CR_OPTLOCK) /* G0, G4, L4, WB and WL */
320 if (enable) {
321 regs->CR |= FLASH_CR_OPTLOCK;
322 } else if (regs->CR & FLASH_CR_OPTLOCK) {
323 regs->OPTKEYR = FLASH_OPTKEY1;
324 regs->OPTKEYR = FLASH_OPTKEY2;
325 }
326 #elif defined(FLASH_PECR_OPTLOCK) /* L0 and L1 */
327 if (enable) {
328 regs->PECR |= FLASH_PECR_OPTLOCK;
329 } else if (regs->PECR & FLASH_PECR_OPTLOCK) {
330 regs->OPTKEYR = FLASH_OPTKEY1;
331 regs->OPTKEYR = FLASH_OPTKEY2;
332 }
333 #elif defined(FLASH_NSCR_OPTLOCK) /* L5 and U5 */
334 if (enable) {
335 regs->NSCR |= FLASH_NSCR_OPTLOCK;
336 } else if (regs->NSCR & FLASH_NSCR_OPTLOCK) {
337 regs->OPTKEYR = FLASH_OPTKEY1;
338 regs->OPTKEYR = FLASH_OPTKEY2;
339 }
340 #elif defined(FLASH_NSCR1_OPTLOCK) /* WBA */
341 if (enable) {
342 regs->NSCR1 |= FLASH_NSCR1_OPTLOCK;
343 } else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) {
344 regs->OPTKEYR = FLASH_OPTKEY1;
345 regs->OPTKEYR = FLASH_OPTKEY2;
346 }
347 #endif
348 /* Lock CR/PECR/NSCR register if needed. */
349 if (enable) {
350 rc = flash_stm32_write_protection(dev, true);
351 if (rc) {
352 return rc;
353 }
354 }
355 #endif
356
357 if (enable) {
358 LOG_DBG("Option bytes locked");
359 } else {
360 LOG_DBG("Option bytes unlocked");
361 }
362
363 return 0;
364 }
365
366 #if defined(CONFIG_FLASH_EX_OP_ENABLED) && defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS)
flash_stm32_control_register_disable(const struct device * dev)367 int flash_stm32_control_register_disable(const struct device *dev)
368 {
369 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
370
371 #if defined(FLASH_CR_LOCK) /* F0, F1, F2, F3, F4, F7, L4, G0, G4, WB, WL */
372 /*
373 * Access to control register can be disabled by writing wrong key to
374 * the key register. Option register will remain disabled until reset.
375 * Writing wrong key causes a bus fault, so we need to set FAULTMASK to
376 * disable faults, and clear bus fault pending bit before enabling them
377 * again.
378 */
379 regs->CR |= FLASH_CR_LOCK;
380
381 __set_FAULTMASK(1);
382 regs->KEYR = 0xffffffff;
383
384 /* Clear Bus Fault pending bit */
385 SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
386 __set_FAULTMASK(0);
387
388 return 0;
389 #else
390 ARG_UNUSED(regs);
391
392 return -ENOTSUP;
393 #endif
394 }
395
flash_stm32_option_bytes_disable(const struct device * dev)396 int flash_stm32_option_bytes_disable(const struct device *dev)
397 {
398 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
399
400 #if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */
401 /*
402 * Access to option register can be disabled by writing wrong key to
403 * the key register. Option register will remain disabled until reset.
404 * Writing wrong key causes a bus fault, so we need to set FAULTMASK to
405 * disable faults, and clear bus fault pending bit before enabling them
406 * again.
407 */
408 regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
409
410 __set_FAULTMASK(1);
411 regs->OPTKEYR = 0xffffffff;
412
413 /* Clear Bus Fault pending bit */
414 SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
415 __set_FAULTMASK(0);
416
417 return 0;
418 #else
419 ARG_UNUSED(regs);
420
421 return -ENOTSUP;
422 #endif
423 }
424 #endif /* CONFIG_FLASH_STM32_BLOCK_REGISTERS */
425
426 static const struct flash_parameters *
flash_stm32_get_parameters(const struct device * dev)427 flash_stm32_get_parameters(const struct device *dev)
428 {
429 ARG_UNUSED(dev);
430
431 return &flash_stm32_parameters;
432 }
433
434 static struct flash_stm32_priv flash_data = {
435 .regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0),
436 /* Getting clocks information from device tree description depending
437 * on the presence of 'clocks' property.
438 */
439 #if DT_INST_NODE_HAS_PROP(0, clocks)
440 .pclken = {
441 .enr = DT_INST_CLOCKS_CELL(0, bits),
442 .bus = DT_INST_CLOCKS_CELL(0, bus),
443 }
444 #endif
445 };
446
447 static DEVICE_API(flash, flash_stm32_api) = {
448 .erase = flash_stm32_erase,
449 .write = flash_stm32_write,
450 .read = flash_stm32_read,
451 .get_parameters = flash_stm32_get_parameters,
452 #ifdef CONFIG_FLASH_PAGE_LAYOUT
453 .page_layout = flash_stm32_page_layout,
454 #endif
455 #ifdef CONFIG_FLASH_EX_OP_ENABLED
456 .ex_op = flash_stm32_ex_op,
457 #endif
458 };
459
stm32_flash_init(const struct device * dev)460 static int stm32_flash_init(const struct device *dev)
461 {
462 int rc;
463 /* Below is applicable to F0, F1, F3, G0, G4, L1, L4, L5, U5 & WB55 series.
464 * For F2, F4, F7 series, this is not applicable.
465 */
466 #if DT_INST_NODE_HAS_PROP(0, clocks)
467 struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
468 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
469
470 /*
471 * On STM32 F0, F1, F3 & L1 series, flash interface clock source is
472 * always HSI, so statically enable HSI here.
473 */
474 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
475 defined(CONFIG_SOC_SERIES_STM32F1X) || \
476 defined(CONFIG_SOC_SERIES_STM32F3X) || \
477 defined(CONFIG_SOC_SERIES_STM32L1X)
478 LL_RCC_HSI_Enable();
479
480 while (!LL_RCC_HSI_IsReady()) {
481 }
482 #endif
483
484 if (!device_is_ready(clk)) {
485 LOG_ERR("clock control device not ready");
486 return -ENODEV;
487 }
488
489 /* enable clock */
490 if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
491 LOG_ERR("Failed to enable clock");
492 return -EIO;
493 }
494 #endif
495
496 #ifdef CONFIG_SOC_SERIES_STM32WBX
497 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
498 #endif /* CONFIG_SOC_SERIES_STM32WBX */
499
500 flash_stm32_sem_init(dev);
501
502 LOG_DBG("Flash @0x%x initialized. BS: %zu",
503 FLASH_STM32_BASE_ADDRESS,
504 flash_stm32_parameters.write_block_size);
505
506 /* Check Flash configuration */
507 rc = flash_stm32_check_configuration();
508 if (rc < 0) {
509 return rc;
510 }
511
512 #if ((CONFIG_FLASH_LOG_LEVEL >= LOG_LEVEL_DBG) && CONFIG_FLASH_PAGE_LAYOUT)
513 const struct flash_pages_layout *layout;
514 size_t layout_size;
515
516 flash_stm32_page_layout(dev, &layout, &layout_size);
517 for (size_t i = 0; i < layout_size; i++) {
518 LOG_DBG("Block %zu: bs: %zu count: %zu", i,
519 layout[i].pages_size, layout[i].pages_count);
520 }
521 #endif
522
523 return 0;
524 }
525
526 DEVICE_DT_INST_DEFINE(0, stm32_flash_init, NULL,
527 &flash_data, NULL, POST_KERNEL,
528 CONFIG_FLASH_INIT_PRIORITY, &flash_stm32_api);
529
