1 /** 2 * \file 3 * 4 * \brief Instance description for DMAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_DMAC_INSTANCE_ 30 #define _SAML21_DMAC_INSTANCE_ 31 32 /* ========== Register definition for DMAC peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_DMAC_CTRL (0x44000400) /**< \brief (DMAC) Control */ 35 #define REG_DMAC_CRCCTRL (0x44000402) /**< \brief (DMAC) CRC Control */ 36 #define REG_DMAC_CRCDATAIN (0x44000404) /**< \brief (DMAC) CRC Data Input */ 37 #define REG_DMAC_CRCCHKSUM (0x44000408) /**< \brief (DMAC) CRC Checksum */ 38 #define REG_DMAC_CRCSTATUS (0x4400040C) /**< \brief (DMAC) CRC Status */ 39 #define REG_DMAC_DBGCTRL (0x4400040D) /**< \brief (DMAC) Debug Control */ 40 #define REG_DMAC_QOSCTRL (0x4400040E) /**< \brief (DMAC) QOS Control */ 41 #define REG_DMAC_SWTRIGCTRL (0x44000410) /**< \brief (DMAC) Software Trigger Control */ 42 #define REG_DMAC_PRICTRL0 (0x44000414) /**< \brief (DMAC) Priority Control 0 */ 43 #define REG_DMAC_INTPEND (0x44000420) /**< \brief (DMAC) Interrupt Pending */ 44 #define REG_DMAC_INTSTATUS (0x44000424) /**< \brief (DMAC) Interrupt Status */ 45 #define REG_DMAC_BUSYCH (0x44000428) /**< \brief (DMAC) Busy Channels */ 46 #define REG_DMAC_PENDCH (0x4400042C) /**< \brief (DMAC) Pending Channels */ 47 #define REG_DMAC_ACTIVE (0x44000430) /**< \brief (DMAC) Active Channel and Levels */ 48 #define REG_DMAC_BASEADDR (0x44000434) /**< \brief (DMAC) Descriptor Memory Section Base Address */ 49 #define REG_DMAC_WRBADDR (0x44000438) /**< \brief (DMAC) Write-Back Memory Section Base Address */ 50 #define REG_DMAC_CHID (0x4400043F) /**< \brief (DMAC) Channel ID */ 51 #define REG_DMAC_CHCTRLA (0x44000440) /**< \brief (DMAC) Channel Control A */ 52 #define REG_DMAC_CHCTRLB (0x44000444) /**< \brief (DMAC) Channel Control B */ 53 #define REG_DMAC_CHINTENCLR (0x4400044C) /**< \brief (DMAC) Channel Interrupt Enable Clear */ 54 #define REG_DMAC_CHINTENSET (0x4400044D) /**< \brief (DMAC) Channel Interrupt Enable Set */ 55 #define REG_DMAC_CHINTFLAG (0x4400044E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ 56 #define REG_DMAC_CHSTATUS (0x4400044F) /**< \brief (DMAC) Channel Status */ 57 #else 58 #define REG_DMAC_CTRL (*(RwReg16*)0x44000400UL) /**< \brief (DMAC) Control */ 59 #define REG_DMAC_CRCCTRL (*(RwReg16*)0x44000402UL) /**< \brief (DMAC) CRC Control */ 60 #define REG_DMAC_CRCDATAIN (*(RwReg *)0x44000404UL) /**< \brief (DMAC) CRC Data Input */ 61 #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x44000408UL) /**< \brief (DMAC) CRC Checksum */ 62 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4400040CUL) /**< \brief (DMAC) CRC Status */ 63 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4400040DUL) /**< \brief (DMAC) Debug Control */ 64 #define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4400040EUL) /**< \brief (DMAC) QOS Control */ 65 #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x44000410UL) /**< \brief (DMAC) Software Trigger Control */ 66 #define REG_DMAC_PRICTRL0 (*(RwReg *)0x44000414UL) /**< \brief (DMAC) Priority Control 0 */ 67 #define REG_DMAC_INTPEND (*(RwReg16*)0x44000420UL) /**< \brief (DMAC) Interrupt Pending */ 68 #define REG_DMAC_INTSTATUS (*(RoReg *)0x44000424UL) /**< \brief (DMAC) Interrupt Status */ 69 #define REG_DMAC_BUSYCH (*(RoReg *)0x44000428UL) /**< \brief (DMAC) Busy Channels */ 70 #define REG_DMAC_PENDCH (*(RoReg *)0x4400042CUL) /**< \brief (DMAC) Pending Channels */ 71 #define REG_DMAC_ACTIVE (*(RoReg *)0x44000430UL) /**< \brief (DMAC) Active Channel and Levels */ 72 #define REG_DMAC_BASEADDR (*(RwReg *)0x44000434UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */ 73 #define REG_DMAC_WRBADDR (*(RwReg *)0x44000438UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */ 74 #define REG_DMAC_CHID (*(RwReg8 *)0x4400043FUL) /**< \brief (DMAC) Channel ID */ 75 #define REG_DMAC_CHCTRLA (*(RwReg8 *)0x44000440UL) /**< \brief (DMAC) Channel Control A */ 76 #define REG_DMAC_CHCTRLB (*(RwReg *)0x44000444UL) /**< \brief (DMAC) Channel Control B */ 77 #define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4400044CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */ 78 #define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4400044DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */ 79 #define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4400044EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ 80 #define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4400044FUL) /**< \brief (DMAC) Channel Status */ 81 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 /* ========== Instance parameters for DMAC peripheral ========== */ 84 #define DMAC_CH_BITS 4 // Number of bits to select channel 85 #define DMAC_CH_NUM 16 // Number of channels 86 #define DMAC_CLK_AHB_ID 11 // AHB clock index 87 #define DMAC_EVIN_NUM 8 // Number of input events 88 #define DMAC_EVOUT_NUM 8 // Number of output events 89 #define DMAC_LVL_BITS 2 // Number of bit to select level priority 90 #define DMAC_LVL_NUM 4 // Enable priority level number 91 #define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value 92 #define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value 93 #define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value 94 #define DMAC_TRIG_BITS 6 // Number of bits to select trigger source 95 #define DMAC_TRIG_NUM 46 // Number of peripheral triggers 96 97 #endif /* _SAML21_DMAC_INSTANCE_ */ 98
