Searched refs:DMACPUSEL0 (Results 1 – 2 of 2) sorted by relevance
773 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH0_Msk; in hri_tal_set_DMACPUSEL0_CH0_bit()780 tmp = ((Tal *)hw)->DMACPUSEL0.reg; in hri_tal_get_DMACPUSEL0_CH0_bit()789 tmp = ((Tal *)hw)->DMACPUSEL0.reg; in hri_tal_write_DMACPUSEL0_CH0_bit()792 ((Tal *)hw)->DMACPUSEL0.reg = tmp; in hri_tal_write_DMACPUSEL0_CH0_bit()799 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH0_Msk; in hri_tal_clear_DMACPUSEL0_CH0_bit()806 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH0_Msk; in hri_tal_toggle_DMACPUSEL0_CH0_bit()813 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH1_Msk; in hri_tal_set_DMACPUSEL0_CH1_bit()820 tmp = ((Tal *)hw)->DMACPUSEL0.reg; in hri_tal_get_DMACPUSEL0_CH1_bit()829 tmp = ((Tal *)hw)->DMACPUSEL0.reg; in hri_tal_write_DMACPUSEL0_CH1_bit()832 ((Tal *)hw)->DMACPUSEL0.reg = tmp; in hri_tal_write_DMACPUSEL0_CH1_bit()[all …]
870 …__IO TAL_DMACPUSEL0_Type DMACPUSEL0; /**< \brief Offset: 0x40 (R/W 32) DMA Channel Interrup… member
