Searched refs:DCR (Results 1 – 15 of 15) sorted by relevance
| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/ |
| D | stm32l1xx_hal_tim.c | 3341 htim->Instance->DCR = BurstBaseAddress | BurstLength; in HAL_TIM_DMABurst_WriteStart()
3550 htim->Instance->DCR = BurstBaseAddress | BurstLength; in HAL_TIM_DMABurst_ReadStart()
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| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/ |
| D | stm32l0xx_hal_tim.c | 3323 htim->Instance->DCR = BurstBaseAddress | BurstLength; in HAL_TIM_DMABurst_WriteStart()
3526 htim->Instance->DCR = BurstBaseAddress | BurstLength; in HAL_TIM_DMABurst_ReadStart()
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| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/ |
| D | stm32l1xx_ll_tim.h | 2459 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); in LL_TIM_ConfigDMABurst()
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| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/ |
| D | stm32l0xx_ll_tim.h | 2455 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); in LL_TIM_ConfigDMABurst()
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| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_hal_tim.c | 3952 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_WriteStart()
4205 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_ReadStart()
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| D | stm32l4xx_hal_qspi.c | 393 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
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| /loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/ |
| D | stm32l4xx_ll_tim.h | 3800 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); in LL_TIM_ConfigDMABurst()
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| /loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/ |
| D | stm32l081xx.h | 504 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/NucleoL073/cmsis/ |
| D | stm32l073xx.h | 545 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/SKiM980A/cmsis/ |
| D | stm32l151xba.h | 503 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/SKiM880B/cmsis/ |
| D | stm32l151xba.h | 503 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/ |
| D | stm32l072xx.h | 531 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/NAMote72/cmsis/ |
| D | stm32l152xc.h | 571 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/NucleoL152/cmsis/ |
| D | stm32l152xe.h | 586 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /loramac-node-3.4.0/src/boards/NucleoL476/cmsis/ |
| D | stm32l476xx.h | 683 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
930 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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