1 /** 2 * \file 3 * 4 * \brief Component description for DAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_DAC_COMPONENT_ 30 #define _SAML21_DAC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DAC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_DAC Digital-to-Analog Converter */ 36 /*@{*/ 37 38 #define DAC_U2244 39 #define REV_DAC 0x112 40 41 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ 47 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } DAC_CTRLA_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ 54 #define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ 55 56 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ 57 #define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) 58 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ 59 #define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) 60 #define DAC_CTRLA_MASK _U(0x03) /**< \brief (DAC_CTRLA) MASK Register */ 61 62 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ 67 uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ 68 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 69 } bit; /*!< Structure used for bit access */ 70 uint8_t reg; /*!< Type used for register access */ 71 } DAC_CTRLB_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 #define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ 75 #define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ 76 77 #define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ 78 #define DAC_CTRLB_DIFF (_U(0x1) << DAC_CTRLB_DIFF_Pos) 79 #define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ 80 #define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) 81 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) 82 #define DAC_CTRLB_REFSEL_VREFPU_Val _U(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ 83 #define DAC_CTRLB_REFSEL_VDDANA_Val _U(0x1) /**< \brief (DAC_CTRLB) Analog supply */ 84 #define DAC_CTRLB_REFSEL_VREFPB_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ 85 #define DAC_CTRLB_REFSEL_INTREF_Val _U(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ 86 #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) 87 #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) 88 #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) 89 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) 90 #define DAC_CTRLB_MASK _U(0x07) /**< \brief (DAC_CTRLB) MASK Register */ 91 92 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { 95 struct { 96 uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ 97 uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ 98 uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ 99 uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ 100 uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ 101 uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ 102 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 103 } bit; /*!< Structure used for bit access */ 104 struct { 105 uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ 106 uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ 107 uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ 108 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 109 } vec; /*!< Structure used for vec access */ 110 uint8_t reg; /*!< Type used for register access */ 111 } DAC_EVCTRL_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 114 #define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ 115 #define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ 116 117 #define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ 118 #define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) 119 #define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ 120 #define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) 121 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ 122 #define DAC_EVCTRL_STARTEI_Msk (_U(0x3) << DAC_EVCTRL_STARTEI_Pos) 123 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) 124 #define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ 125 #define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) 126 #define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ 127 #define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) 128 #define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ 129 #define DAC_EVCTRL_EMPTYEO_Msk (_U(0x3) << DAC_EVCTRL_EMPTYEO_Pos) 130 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) 131 #define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ 132 #define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) 133 #define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ 134 #define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) 135 #define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ 136 #define DAC_EVCTRL_INVEI_Msk (_U(0x3) << DAC_EVCTRL_INVEI_Pos) 137 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) 138 #define DAC_EVCTRL_MASK _U(0x3F) /**< \brief (DAC_EVCTRL) MASK Register */ 139 140 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 141 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 142 typedef union { 143 struct { 144 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ 145 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ 146 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 147 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 148 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 struct { 151 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ 152 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 153 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 154 } vec; /*!< Structure used for vec access */ 155 uint8_t reg; /*!< Type used for register access */ 156 } DAC_INTENCLR_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ 160 #define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ 161 162 #define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ 163 #define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) 164 #define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ 165 #define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) 166 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ 167 #define DAC_INTENCLR_UNDERRUN_Msk (_U(0x3) << DAC_INTENCLR_UNDERRUN_Pos) 168 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) 169 #define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ 170 #define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) 171 #define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ 172 #define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) 173 #define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ 174 #define DAC_INTENCLR_EMPTY_Msk (_U(0x3) << DAC_INTENCLR_EMPTY_Pos) 175 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) 176 #define DAC_INTENCLR_MASK _U(0x0F) /**< \brief (DAC_INTENCLR) MASK Register */ 177 178 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ 183 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ 184 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 185 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 186 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 187 } bit; /*!< Structure used for bit access */ 188 struct { 189 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ 190 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 191 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 192 } vec; /*!< Structure used for vec access */ 193 uint8_t reg; /*!< Type used for register access */ 194 } DAC_INTENSET_Type; 195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 196 197 #define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ 198 #define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ 199 200 #define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ 201 #define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) 202 #define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ 203 #define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) 204 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ 205 #define DAC_INTENSET_UNDERRUN_Msk (_U(0x3) << DAC_INTENSET_UNDERRUN_Pos) 206 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) 207 #define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ 208 #define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) 209 #define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ 210 #define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) 211 #define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ 212 #define DAC_INTENSET_EMPTY_Msk (_U(0x3) << DAC_INTENSET_EMPTY_Pos) 213 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) 214 #define DAC_INTENSET_MASK _U(0x0F) /**< \brief (DAC_INTENSET) MASK Register */ 215 216 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { // __I to avoid read-modify-write on write-to-clear register 219 struct { 220 __I uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ 221 __I uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ 222 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ 223 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ 224 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ 225 } bit; /*!< Structure used for bit access */ 226 struct { 227 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ 228 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ 229 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ 230 } vec; /*!< Structure used for vec access */ 231 uint8_t reg; /*!< Type used for register access */ 232 } DAC_INTFLAG_Type; 233 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 234 235 #define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ 236 #define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 237 238 #define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ 239 #define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) 240 #define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ 241 #define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) 242 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ 243 #define DAC_INTFLAG_UNDERRUN_Msk (_U(0x3) << DAC_INTFLAG_UNDERRUN_Pos) 244 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) 245 #define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ 246 #define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) 247 #define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ 248 #define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) 249 #define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ 250 #define DAC_INTFLAG_EMPTY_Msk (_U(0x3) << DAC_INTFLAG_EMPTY_Pos) 251 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) 252 #define DAC_INTFLAG_MASK _U(0x0F) /**< \brief (DAC_INTFLAG) MASK Register */ 253 254 /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 256 typedef union { 257 struct { 258 uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ 259 uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ 260 uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ 261 uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ 262 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 263 } bit; /*!< Structure used for bit access */ 264 struct { 265 uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ 266 uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ 267 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 268 } vec; /*!< Structure used for vec access */ 269 uint8_t reg; /*!< Type used for register access */ 270 } DAC_STATUS_Type; 271 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 272 273 #define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ 274 #define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ 275 276 #define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ 277 #define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) 278 #define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ 279 #define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) 280 #define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ 281 #define DAC_STATUS_READY_Msk (_U(0x3) << DAC_STATUS_READY_Pos) 282 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) 283 #define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ 284 #define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) 285 #define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ 286 #define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) 287 #define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ 288 #define DAC_STATUS_EOC_Msk (_U(0x3) << DAC_STATUS_EOC_Pos) 289 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) 290 #define DAC_STATUS_MASK _U(0x0F) /**< \brief (DAC_STATUS) MASK Register */ 291 292 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 297 uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ 298 uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ 299 uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ 300 uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ 301 uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ 302 uint32_t :26; /*!< bit: 6..31 Reserved */ 303 } bit; /*!< Structure used for bit access */ 304 struct { 305 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 306 uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ 307 uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ 308 uint32_t :26; /*!< bit: 6..31 Reserved */ 309 } vec; /*!< Structure used for vec access */ 310 uint32_t reg; /*!< Type used for register access */ 311 } DAC_SYNCBUSY_Type; 312 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 313 314 #define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ 315 #define DAC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ 316 317 #define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ 318 #define DAC_SYNCBUSY_SWRST (_U(0x1) << DAC_SYNCBUSY_SWRST_Pos) 319 #define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ 320 #define DAC_SYNCBUSY_ENABLE (_U(0x1) << DAC_SYNCBUSY_ENABLE_Pos) 321 #define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ 322 #define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) 323 #define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ 324 #define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) 325 #define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ 326 #define DAC_SYNCBUSY_DATA_Msk (_U(0x3) << DAC_SYNCBUSY_DATA_Pos) 327 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) 328 #define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ 329 #define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) 330 #define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ 331 #define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) 332 #define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ 333 #define DAC_SYNCBUSY_DATABUF_Msk (_U(0x3) << DAC_SYNCBUSY_DATABUF_Pos) 334 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) 335 #define DAC_SYNCBUSY_MASK _U(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ 336 337 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef union { 340 struct { 341 uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ 342 uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ 343 uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ 344 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 345 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 346 uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ 347 uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ 348 uint16_t :4; /*!< bit: 12..15 Reserved */ 349 } bit; /*!< Structure used for bit access */ 350 uint16_t reg; /*!< Type used for register access */ 351 } DAC_DACCTRL_Type; 352 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 353 354 #define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ 355 #define DAC_DACCTRL_RESETVALUE _U(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ 356 357 #define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ 358 #define DAC_DACCTRL_LEFTADJ (_U(0x1) << DAC_DACCTRL_LEFTADJ_Pos) 359 #define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ 360 #define DAC_DACCTRL_ENABLE (_U(0x1) << DAC_DACCTRL_ENABLE_Pos) 361 #define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ 362 #define DAC_DACCTRL_CCTRL_Msk (_U(0x3) << DAC_DACCTRL_CCTRL_Pos) 363 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) 364 #define DAC_DACCTRL_CCTRL_CC12M_Val _U(0x0) /**< \brief (DAC_DACCTRL) 1MHz<GCLK_DAC<12MHz */ 365 #define DAC_DACCTRL_CCTRL_CC1M_Val _U(0x1) /**< \brief (DAC_DACCTRL) 100kHz<GCLK_DAC<1MHz */ 366 #define DAC_DACCTRL_CCTRL_CC100K_Val _U(0x2) /**< \brief (DAC_DACCTRL) 10kHz<GCLK_DAC<100kHz */ 367 #define DAC_DACCTRL_CCTRL_CC10K_Val _U(0x3) /**< \brief (DAC_DACCTRL) GCLK_DAC<100kHz */ 368 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) 369 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) 370 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) 371 #define DAC_DACCTRL_CCTRL_CC10K (DAC_DACCTRL_CCTRL_CC10K_Val << DAC_DACCTRL_CCTRL_Pos) 372 #define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ 373 #define DAC_DACCTRL_RUNSTDBY (_U(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) 374 #define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ 375 #define DAC_DACCTRL_DITHER (_U(0x1) << DAC_DACCTRL_DITHER_Pos) 376 #define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ 377 #define DAC_DACCTRL_REFRESH_Msk (_U(0xF) << DAC_DACCTRL_REFRESH_Pos) 378 #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) 379 #define DAC_DACCTRL_MASK _U(0x0FCF) /**< \brief (DAC_DACCTRL) MASK Register */ 380 381 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ 382 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 383 typedef union { 384 struct { 385 uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ 386 } bit; /*!< Structure used for bit access */ 387 uint16_t reg; /*!< Type used for register access */ 388 } DAC_DATA_Type; 389 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 390 391 #define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ 392 #define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ 393 394 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ 395 #define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) 396 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) 397 #define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ 398 399 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ 400 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 401 typedef union { 402 struct { 403 uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ 404 } bit; /*!< Structure used for bit access */ 405 uint16_t reg; /*!< Type used for register access */ 406 } DAC_DATABUF_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ 410 #define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ 411 412 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ 413 #define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) 414 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) 415 #define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ 416 417 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ 418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 419 typedef union { 420 struct { 421 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 422 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 423 } bit; /*!< Structure used for bit access */ 424 uint8_t reg; /*!< Type used for register access */ 425 } DAC_DBGCTRL_Type; 426 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 427 428 #define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ 429 #define DAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ 430 431 #define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ 432 #define DAC_DBGCTRL_DBGRUN (_U(0x1) << DAC_DBGCTRL_DBGRUN_Pos) 433 #define DAC_DBGCTRL_MASK _U(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ 434 435 /** \brief DAC hardware registers */ 436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 437 typedef struct { 438 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 439 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 440 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 441 RoReg8 Reserved1[0x1]; 442 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 443 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 444 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 445 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ 446 __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 447 __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ 448 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ 449 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ 450 __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ 451 } Dac; 452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 453 454 /*@}*/ 455 456 #endif /* _SAML21_DAC_COMPONENT_ */ 457
