Searched refs:CTRLB (Results 1 – 17 of 17) sorted by relevance
348 ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; in hri_nvmctrl_set_CTRLB_MANW_bit()355 tmp = ((Nvmctrl *)hw)->CTRLB.reg; in hri_nvmctrl_get_CTRLB_MANW_bit()364 tmp = ((Nvmctrl *)hw)->CTRLB.reg; in hri_nvmctrl_write_CTRLB_MANW_bit()367 ((Nvmctrl *)hw)->CTRLB.reg = tmp; in hri_nvmctrl_write_CTRLB_MANW_bit()374 ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; in hri_nvmctrl_clear_CTRLB_MANW_bit()381 ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; in hri_nvmctrl_toggle_CTRLB_MANW_bit()388 ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP; in hri_nvmctrl_set_CTRLB_FWUP_bit()395 tmp = ((Nvmctrl *)hw)->CTRLB.reg; in hri_nvmctrl_get_CTRLB_FWUP_bit()404 tmp = ((Nvmctrl *)hw)->CTRLB.reg; in hri_nvmctrl_write_CTRLB_FWUP_bit()407 ((Nvmctrl *)hw)->CTRLB.reg = tmp; in hri_nvmctrl_write_CTRLB_FWUP_bit()[all …]
953 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; in hri_sercomspi_set_CTRLB_PLOADEN_bit()960 tmp = ((Sercom *)hw)->SPI.CTRLB.reg; in hri_sercomspi_get_CTRLB_PLOADEN_bit()969 tmp = ((Sercom *)hw)->SPI.CTRLB.reg; in hri_sercomspi_write_CTRLB_PLOADEN_bit()972 ((Sercom *)hw)->SPI.CTRLB.reg = tmp; in hri_sercomspi_write_CTRLB_PLOADEN_bit()979 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; in hri_sercomspi_clear_CTRLB_PLOADEN_bit()986 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; in hri_sercomspi_toggle_CTRLB_PLOADEN_bit()993 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; in hri_sercomspi_set_CTRLB_SSDE_bit()1000 tmp = ((Sercom *)hw)->SPI.CTRLB.reg; in hri_sercomspi_get_CTRLB_SSDE_bit()1009 tmp = ((Sercom *)hw)->SPI.CTRLB.reg; in hri_sercomspi_write_CTRLB_SSDE_bit()1012 ((Sercom *)hw)->SPI.CTRLB.reg = tmp; in hri_sercomspi_write_CTRLB_SSDE_bit()[all …]
723 ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; in hri_aes_set_CTRLB_START_bit()730 tmp = ((Aes *)hw)->CTRLB.reg; in hri_aes_get_CTRLB_START_bit()739 tmp = ((Aes *)hw)->CTRLB.reg; in hri_aes_write_CTRLB_START_bit()742 ((Aes *)hw)->CTRLB.reg = tmp; in hri_aes_write_CTRLB_START_bit()749 ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; in hri_aes_clear_CTRLB_START_bit()756 ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; in hri_aes_toggle_CTRLB_START_bit()763 ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; in hri_aes_set_CTRLB_NEWMSG_bit()770 tmp = ((Aes *)hw)->CTRLB.reg; in hri_aes_get_CTRLB_NEWMSG_bit()779 tmp = ((Aes *)hw)->CTRLB.reg; in hri_aes_write_CTRLB_NEWMSG_bit()782 ((Aes *)hw)->CTRLB.reg = tmp; in hri_aes_write_CTRLB_NEWMSG_bit()[all …]
428 ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; in hri_dac_set_CTRLB_DIFF_bit()435 tmp = ((Dac *)hw)->CTRLB.reg; in hri_dac_get_CTRLB_DIFF_bit()444 tmp = ((Dac *)hw)->CTRLB.reg; in hri_dac_write_CTRLB_DIFF_bit()447 ((Dac *)hw)->CTRLB.reg = tmp; in hri_dac_write_CTRLB_DIFF_bit()454 ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; in hri_dac_clear_CTRLB_DIFF_bit()461 ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; in hri_dac_toggle_CTRLB_DIFF_bit()468 ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); in hri_dac_set_CTRLB_REFSEL_bf()475 tmp = ((Dac *)hw)->CTRLB.reg; in hri_dac_get_CTRLB_REFSEL_bf()484 tmp = ((Dac *)hw)->CTRLB.reg; in hri_dac_write_CTRLB_REFSEL_bf()487 ((Dac *)hw)->CTRLB.reg = tmp; in hri_dac_write_CTRLB_REFSEL_bf()[all …]
2451 ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; in hri_usbhost_set_CTRLB_RESUME_bit()2458 tmp = ((Usb *)hw)->HOST.CTRLB.reg; in hri_usbhost_get_CTRLB_RESUME_bit()2467 tmp = ((Usb *)hw)->HOST.CTRLB.reg; in hri_usbhost_write_CTRLB_RESUME_bit()2470 ((Usb *)hw)->HOST.CTRLB.reg = tmp; in hri_usbhost_write_CTRLB_RESUME_bit()2477 ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; in hri_usbhost_clear_CTRLB_RESUME_bit()2484 ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; in hri_usbhost_toggle_CTRLB_RESUME_bit()2491 ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; in hri_usbhost_set_CTRLB_AUTORESUME_bit()2498 tmp = ((Usb *)hw)->HOST.CTRLB.reg; in hri_usbhost_get_CTRLB_AUTORESUME_bit()2507 tmp = ((Usb *)hw)->HOST.CTRLB.reg; in hri_usbhost_write_CTRLB_AUTORESUME_bit()2510 ((Usb *)hw)->HOST.CTRLB.reg = tmp; in hri_usbhost_write_CTRLB_AUTORESUME_bit()[all …]
468 ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); in hri_adc_set_CTRLB_PRESCALER_bf()475 tmp = ((Adc *)hw)->CTRLB.reg; in hri_adc_get_CTRLB_PRESCALER_bf()484 tmp = ((Adc *)hw)->CTRLB.reg; in hri_adc_write_CTRLB_PRESCALER_bf()487 ((Adc *)hw)->CTRLB.reg = tmp; in hri_adc_write_CTRLB_PRESCALER_bf()494 ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); in hri_adc_clear_CTRLB_PRESCALER_bf()501 ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); in hri_adc_toggle_CTRLB_PRESCALER_bf()508 tmp = ((Adc *)hw)->CTRLB.reg; in hri_adc_read_CTRLB_PRESCALER_bf()516 ((Adc *)hw)->CTRLB.reg |= mask; in hri_adc_set_CTRLB_reg()523 tmp = ((Adc *)hw)->CTRLB.reg; in hri_adc_get_CTRLB_reg()531 ((Adc *)hw)->CTRLB.reg = data; in hri_adc_write_CTRLB_reg()[all …]
268 ((Ac *)hw)->CTRLB.reg = data; in hri_ac_write_CTRLB_reg()
1084 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ member1108 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ member1346 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ member1370 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ member1390 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ member1414 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ member
302 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ member
439 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ member
335 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ member
565 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ member
696 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ member
1696 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ member1727 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ member
505 uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ member
247 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ member
237 NVMCTRL->CTRLB.bit.MANW = 1; in Reset_Handler()
