1 /** 2 * \file 3 * 4 * \brief Instance description for CCL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_CCL_INSTANCE_ 30 #define _SAML21_CCL_INSTANCE_ 31 32 /* ========== Register definition for CCL peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_CCL_CTRL (0x43001C00) /**< \brief (CCL) Control */ 35 #define REG_CCL_SEQCTRL0 (0x43001C04) /**< \brief (CCL) SEQ Control x 0 */ 36 #define REG_CCL_SEQCTRL1 (0x43001C05) /**< \brief (CCL) SEQ Control x 1 */ 37 #define REG_CCL_LUTCTRL0 (0x43001C08) /**< \brief (CCL) LUT Control x 0 */ 38 #define REG_CCL_LUTCTRL1 (0x43001C0C) /**< \brief (CCL) LUT Control x 1 */ 39 #define REG_CCL_LUTCTRL2 (0x43001C10) /**< \brief (CCL) LUT Control x 2 */ 40 #define REG_CCL_LUTCTRL3 (0x43001C14) /**< \brief (CCL) LUT Control x 3 */ 41 #else 42 #define REG_CCL_CTRL (*(RwReg8 *)0x43001C00UL) /**< \brief (CCL) Control */ 43 #define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x43001C04UL) /**< \brief (CCL) SEQ Control x 0 */ 44 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05UL) /**< \brief (CCL) SEQ Control x 1 */ 45 #define REG_CCL_LUTCTRL0 (*(RwReg *)0x43001C08UL) /**< \brief (CCL) LUT Control x 0 */ 46 #define REG_CCL_LUTCTRL1 (*(RwReg *)0x43001C0CUL) /**< \brief (CCL) LUT Control x 1 */ 47 #define REG_CCL_LUTCTRL2 (*(RwReg *)0x43001C10UL) /**< \brief (CCL) LUT Control x 2 */ 48 #define REG_CCL_LUTCTRL3 (*(RwReg *)0x43001C14UL) /**< \brief (CCL) LUT Control x 3 */ 49 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 /* ========== Instance parameters for CCL peripheral ========== */ 52 #define CCL_GCLK_ID 34 // GCLK index for CCL 53 #define CCL_IO_NUM 12 // Numer of input pins 54 #define CCL_LUT_NUM 4 // Number of LUT in a CCL 55 #define CCL_SEQ_NUM 2 // Number of SEQ in a CCL 56 57 #endif /* _SAML21_CCL_INSTANCE_ */ 58
