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Searched refs:AHBENR (Results 1 – 17 of 17) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_rcc_ex.h180 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
182 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
185 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
195 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
197 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
202 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
204 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
208 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
209 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
221 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
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Dstm32l1xx_hal_rcc.h661 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
663 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
668 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
670 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
675 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
677 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
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Dstm32l1xx_ll_bus.h235 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
237 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
278 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
318 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dsystem_stm32l1xx.c330 RCC->AHBENR = 0x000080D8; in SystemInit_ExtMemCtl()
333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); in SystemInit_ExtMemCtl()
385 RCC->AHBENR = 0x400080D8; in SystemInit_ExtMemCtl()
388 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32l151xba.h395 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dsystem_stm32l1xx.c330 RCC->AHBENR = 0x000080D8; in SystemInit_ExtMemCtl()
333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); in SystemInit_ExtMemCtl()
385 RCC->AHBENR = 0x400080D8; in SystemInit_ExtMemCtl()
388 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32l152xe.h448 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dsystem_stm32l1xx.c330 RCC->AHBENR = 0x000080D8; in SystemInit_ExtMemCtl()
333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); in SystemInit_ExtMemCtl()
385 RCC->AHBENR = 0x400080D8; in SystemInit_ExtMemCtl()
388 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32l151xba.h395 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dsystem_stm32l1xx.c330 RCC->AHBENR = 0x000080D8; in SystemInit_ExtMemCtl()
333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); in SystemInit_ExtMemCtl()
385 RCC->AHBENR = 0x400080D8; in SystemInit_ExtMemCtl()
388 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); in SystemInit_ExtMemCtl()
Dstm32l152xc.h439 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_rcc.h692 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
694 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
700 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
708 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
715 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
716 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
717 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
812 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
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Dstm32l0xx_ll_bus.h243 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
245 tmpreg = READ_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
270 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); in LL_AHB1_GRP1_IsEnabledClock()
294 CLEAR_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_DisableClock()
Dstm32l0xx_hal_rcc_ex.h600 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
602 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
605 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
607 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != RESET)
608 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == RESET)
615 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
617 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
620 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
622 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != RESET)
623 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == RESET)
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/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h421 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h452 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h438 …__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Ad… member