1 /**
2 * \file
3 *
4 * \brief SAM SERCOM
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_SERCOM_COMPONENT_
44 #ifndef _HRI_SERCOM_L21_H_INCLUDED_
45 #define _HRI_SERCOM_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
55 #define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define SERCOM_CRITICAL_SECTION_ENTER()
59 #define SERCOM_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_sercomi2cm_status_reg_t;
63 typedef uint16_t hri_sercomi2cs_status_reg_t;
64 typedef uint16_t hri_sercomspi_status_reg_t;
65 typedef uint16_t hri_sercomusart_baud_reg_t;
66 typedef uint16_t hri_sercomusart_data_reg_t;
67 typedef uint16_t hri_sercomusart_status_reg_t;
68 typedef uint32_t hri_sercomi2cm_addr_reg_t;
69 typedef uint32_t hri_sercomi2cm_baud_reg_t;
70 typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
71 typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
72 typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
73 typedef uint32_t hri_sercomi2cs_addr_reg_t;
74 typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
75 typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
76 typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
77 typedef uint32_t hri_sercomspi_addr_reg_t;
78 typedef uint32_t hri_sercomspi_ctrla_reg_t;
79 typedef uint32_t hri_sercomspi_ctrlb_reg_t;
80 typedef uint32_t hri_sercomspi_data_reg_t;
81 typedef uint32_t hri_sercomspi_syncbusy_reg_t;
82 typedef uint32_t hri_sercomusart_ctrla_reg_t;
83 typedef uint32_t hri_sercomusart_ctrlb_reg_t;
84 typedef uint32_t hri_sercomusart_syncbusy_reg_t;
85 typedef uint8_t hri_sercomi2cm_data_reg_t;
86 typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t;
87 typedef uint8_t hri_sercomi2cm_intenset_reg_t;
88 typedef uint8_t hri_sercomi2cm_intflag_reg_t;
89 typedef uint8_t hri_sercomi2cs_data_reg_t;
90 typedef uint8_t hri_sercomi2cs_intenset_reg_t;
91 typedef uint8_t hri_sercomi2cs_intflag_reg_t;
92 typedef uint8_t hri_sercomspi_baud_reg_t;
93 typedef uint8_t hri_sercomspi_dbgctrl_reg_t;
94 typedef uint8_t hri_sercomspi_intenset_reg_t;
95 typedef uint8_t hri_sercomspi_intflag_reg_t;
96 typedef uint8_t hri_sercomusart_dbgctrl_reg_t;
97 typedef uint8_t hri_sercomusart_intenset_reg_t;
98 typedef uint8_t hri_sercomusart_intflag_reg_t;
99 typedef uint8_t hri_sercomusart_rxpl_reg_t;
100
hri_sercomi2cm_wait_for_sync(const void * const hw,hri_sercomi2cm_syncbusy_reg_t reg)101 static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
102 {
103 while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
104 };
105 }
106
hri_sercomi2cm_is_syncing(const void * const hw,hri_sercomi2cm_syncbusy_reg_t reg)107 static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
108 {
109 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
110 }
111
hri_sercomi2cs_wait_for_sync(const void * const hw,hri_sercomi2cs_syncbusy_reg_t reg)112 static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
113 {
114 while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
115 };
116 }
117
hri_sercomi2cs_is_syncing(const void * const hw,hri_sercomi2cs_syncbusy_reg_t reg)118 static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
119 {
120 return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
121 }
122
hri_sercomspi_wait_for_sync(const void * const hw,hri_sercomspi_syncbusy_reg_t reg)123 static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
124 {
125 while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
126 };
127 }
128
hri_sercomspi_is_syncing(const void * const hw,hri_sercomspi_syncbusy_reg_t reg)129 static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
130 {
131 return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
132 }
133
hri_sercomusart_wait_for_sync(const void * const hw,hri_sercomusart_syncbusy_reg_t reg)134 static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
135 {
136 while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
137 };
138 }
139
hri_sercomusart_is_syncing(const void * const hw,hri_sercomusart_syncbusy_reg_t reg)140 static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
141 {
142 return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
143 }
144
hri_sercomspi_set_INTEN_DRE_bit(const void * const hw)145 static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
146 {
147 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
148 }
149
hri_sercomspi_get_INTEN_DRE_bit(const void * const hw)150 static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
151 {
152 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
153 }
154
hri_sercomspi_write_INTEN_DRE_bit(const void * const hw,bool value)155 static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
156 {
157 if (value == 0x0) {
158 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
159 } else {
160 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
161 }
162 }
163
hri_sercomspi_clear_INTEN_DRE_bit(const void * const hw)164 static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
165 {
166 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
167 }
168
hri_sercomspi_set_INTEN_TXC_bit(const void * const hw)169 static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
170 {
171 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
172 }
173
hri_sercomspi_get_INTEN_TXC_bit(const void * const hw)174 static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
175 {
176 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
177 }
178
hri_sercomspi_write_INTEN_TXC_bit(const void * const hw,bool value)179 static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
180 {
181 if (value == 0x0) {
182 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
183 } else {
184 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
185 }
186 }
187
hri_sercomspi_clear_INTEN_TXC_bit(const void * const hw)188 static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
189 {
190 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
191 }
192
hri_sercomspi_set_INTEN_RXC_bit(const void * const hw)193 static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
194 {
195 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
196 }
197
hri_sercomspi_get_INTEN_RXC_bit(const void * const hw)198 static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
199 {
200 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
201 }
202
hri_sercomspi_write_INTEN_RXC_bit(const void * const hw,bool value)203 static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
204 {
205 if (value == 0x0) {
206 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
207 } else {
208 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
209 }
210 }
211
hri_sercomspi_clear_INTEN_RXC_bit(const void * const hw)212 static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
213 {
214 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
215 }
216
hri_sercomspi_set_INTEN_SSL_bit(const void * const hw)217 static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
218 {
219 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
220 }
221
hri_sercomspi_get_INTEN_SSL_bit(const void * const hw)222 static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
223 {
224 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
225 }
226
hri_sercomspi_write_INTEN_SSL_bit(const void * const hw,bool value)227 static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
228 {
229 if (value == 0x0) {
230 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
231 } else {
232 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
233 }
234 }
235
hri_sercomspi_clear_INTEN_SSL_bit(const void * const hw)236 static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
237 {
238 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
239 }
240
hri_sercomspi_set_INTEN_ERROR_bit(const void * const hw)241 static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
242 {
243 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
244 }
245
hri_sercomspi_get_INTEN_ERROR_bit(const void * const hw)246 static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
247 {
248 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
249 }
250
hri_sercomspi_write_INTEN_ERROR_bit(const void * const hw,bool value)251 static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
252 {
253 if (value == 0x0) {
254 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
255 } else {
256 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
257 }
258 }
259
hri_sercomspi_clear_INTEN_ERROR_bit(const void * const hw)260 static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
261 {
262 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
263 }
264
hri_sercomspi_set_INTEN_reg(const void * const hw,hri_sercomspi_intenset_reg_t mask)265 static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
266 {
267 ((Sercom *)hw)->SPI.INTENSET.reg = mask;
268 }
269
hri_sercomspi_get_INTEN_reg(const void * const hw,hri_sercomspi_intenset_reg_t mask)270 static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw,
271 hri_sercomspi_intenset_reg_t mask)
272 {
273 uint8_t tmp;
274 tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
275 tmp &= mask;
276 return tmp;
277 }
278
hri_sercomspi_read_INTEN_reg(const void * const hw)279 static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
280 {
281 return ((Sercom *)hw)->SPI.INTENSET.reg;
282 }
283
hri_sercomspi_write_INTEN_reg(const void * const hw,hri_sercomspi_intenset_reg_t data)284 static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
285 {
286 ((Sercom *)hw)->SPI.INTENSET.reg = data;
287 ((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
288 }
289
hri_sercomspi_clear_INTEN_reg(const void * const hw,hri_sercomspi_intenset_reg_t mask)290 static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
291 {
292 ((Sercom *)hw)->SPI.INTENCLR.reg = mask;
293 }
294
hri_sercomspi_get_INTFLAG_DRE_bit(const void * const hw)295 static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
296 {
297 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
298 }
299
hri_sercomspi_clear_INTFLAG_DRE_bit(const void * const hw)300 static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
301 {
302 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
303 }
304
hri_sercomspi_get_INTFLAG_TXC_bit(const void * const hw)305 static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
306 {
307 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
308 }
309
hri_sercomspi_clear_INTFLAG_TXC_bit(const void * const hw)310 static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
311 {
312 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
313 }
314
hri_sercomspi_get_INTFLAG_RXC_bit(const void * const hw)315 static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
316 {
317 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
318 }
319
hri_sercomspi_clear_INTFLAG_RXC_bit(const void * const hw)320 static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
321 {
322 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
323 }
324
hri_sercomspi_get_INTFLAG_SSL_bit(const void * const hw)325 static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
326 {
327 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
328 }
329
hri_sercomspi_clear_INTFLAG_SSL_bit(const void * const hw)330 static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
331 {
332 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
333 }
334
hri_sercomspi_get_INTFLAG_ERROR_bit(const void * const hw)335 static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
336 {
337 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
338 }
339
hri_sercomspi_clear_INTFLAG_ERROR_bit(const void * const hw)340 static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
341 {
342 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
343 }
344
hri_sercomspi_get_interrupt_DRE_bit(const void * const hw)345 static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
346 {
347 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
348 }
349
hri_sercomspi_clear_interrupt_DRE_bit(const void * const hw)350 static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
351 {
352 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
353 }
354
hri_sercomspi_get_interrupt_TXC_bit(const void * const hw)355 static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
356 {
357 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
358 }
359
hri_sercomspi_clear_interrupt_TXC_bit(const void * const hw)360 static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
361 {
362 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
363 }
364
hri_sercomspi_get_interrupt_RXC_bit(const void * const hw)365 static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
366 {
367 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
368 }
369
hri_sercomspi_clear_interrupt_RXC_bit(const void * const hw)370 static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
371 {
372 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
373 }
374
hri_sercomspi_get_interrupt_SSL_bit(const void * const hw)375 static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
376 {
377 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
378 }
379
hri_sercomspi_clear_interrupt_SSL_bit(const void * const hw)380 static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
381 {
382 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
383 }
384
hri_sercomspi_get_interrupt_ERROR_bit(const void * const hw)385 static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
386 {
387 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
388 }
389
hri_sercomspi_clear_interrupt_ERROR_bit(const void * const hw)390 static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
391 {
392 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
393 }
394
hri_sercomspi_get_INTFLAG_reg(const void * const hw,hri_sercomspi_intflag_reg_t mask)395 static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw,
396 hri_sercomspi_intflag_reg_t mask)
397 {
398 uint8_t tmp;
399 tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
400 tmp &= mask;
401 return tmp;
402 }
403
hri_sercomspi_read_INTFLAG_reg(const void * const hw)404 static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
405 {
406 return ((Sercom *)hw)->SPI.INTFLAG.reg;
407 }
408
hri_sercomspi_clear_INTFLAG_reg(const void * const hw,hri_sercomspi_intflag_reg_t mask)409 static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
410 {
411 ((Sercom *)hw)->SPI.INTFLAG.reg = mask;
412 }
413
hri_sercomspi_set_CTRLA_SWRST_bit(const void * const hw)414 static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
415 {
416 SERCOM_CRITICAL_SECTION_ENTER();
417 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
418 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
419 SERCOM_CRITICAL_SECTION_LEAVE();
420 }
421
hri_sercomspi_get_CTRLA_SWRST_bit(const void * const hw)422 static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
423 {
424 uint32_t tmp;
425 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
426 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
427 tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
428 return (bool)tmp;
429 }
430
hri_sercomspi_set_CTRLA_ENABLE_bit(const void * const hw)431 static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
432 {
433 SERCOM_CRITICAL_SECTION_ENTER();
434 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
435 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
436 SERCOM_CRITICAL_SECTION_LEAVE();
437 }
438
hri_sercomspi_get_CTRLA_ENABLE_bit(const void * const hw)439 static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
440 {
441 uint32_t tmp;
442 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
443 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
444 tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
445 return (bool)tmp;
446 }
447
hri_sercomspi_write_CTRLA_ENABLE_bit(const void * const hw,bool value)448 static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
449 {
450 uint32_t tmp;
451 SERCOM_CRITICAL_SECTION_ENTER();
452 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
453 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
454 tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
455 tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
456 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
457 SERCOM_CRITICAL_SECTION_LEAVE();
458 }
459
hri_sercomspi_clear_CTRLA_ENABLE_bit(const void * const hw)460 static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
461 {
462 SERCOM_CRITICAL_SECTION_ENTER();
463 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
464 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
465 SERCOM_CRITICAL_SECTION_LEAVE();
466 }
467
hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void * const hw)468 static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
469 {
470 SERCOM_CRITICAL_SECTION_ENTER();
471 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
472 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
473 SERCOM_CRITICAL_SECTION_LEAVE();
474 }
475
hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void * const hw)476 static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
477 {
478 SERCOM_CRITICAL_SECTION_ENTER();
479 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
480 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
481 SERCOM_CRITICAL_SECTION_LEAVE();
482 }
483
hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void * const hw)484 static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
485 {
486 uint32_t tmp;
487 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
488 tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
489 return (bool)tmp;
490 }
491
hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)492 static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
493 {
494 uint32_t tmp;
495 SERCOM_CRITICAL_SECTION_ENTER();
496 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
497 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
498 tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
499 tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
500 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
501 SERCOM_CRITICAL_SECTION_LEAVE();
502 }
503
hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void * const hw)504 static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
505 {
506 SERCOM_CRITICAL_SECTION_ENTER();
507 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
508 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
509 SERCOM_CRITICAL_SECTION_LEAVE();
510 }
511
hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)512 static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
513 {
514 SERCOM_CRITICAL_SECTION_ENTER();
515 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
516 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
517 SERCOM_CRITICAL_SECTION_LEAVE();
518 }
519
hri_sercomspi_set_CTRLA_IBON_bit(const void * const hw)520 static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
521 {
522 SERCOM_CRITICAL_SECTION_ENTER();
523 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
524 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
525 SERCOM_CRITICAL_SECTION_LEAVE();
526 }
527
hri_sercomspi_get_CTRLA_IBON_bit(const void * const hw)528 static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
529 {
530 uint32_t tmp;
531 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
532 tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
533 return (bool)tmp;
534 }
535
hri_sercomspi_write_CTRLA_IBON_bit(const void * const hw,bool value)536 static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
537 {
538 uint32_t tmp;
539 SERCOM_CRITICAL_SECTION_ENTER();
540 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
541 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
542 tmp &= ~SERCOM_SPI_CTRLA_IBON;
543 tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
544 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
545 SERCOM_CRITICAL_SECTION_LEAVE();
546 }
547
hri_sercomspi_clear_CTRLA_IBON_bit(const void * const hw)548 static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
549 {
550 SERCOM_CRITICAL_SECTION_ENTER();
551 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
552 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
553 SERCOM_CRITICAL_SECTION_LEAVE();
554 }
555
hri_sercomspi_toggle_CTRLA_IBON_bit(const void * const hw)556 static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
557 {
558 SERCOM_CRITICAL_SECTION_ENTER();
559 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
560 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
561 SERCOM_CRITICAL_SECTION_LEAVE();
562 }
563
hri_sercomspi_set_CTRLA_CPHA_bit(const void * const hw)564 static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
565 {
566 SERCOM_CRITICAL_SECTION_ENTER();
567 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
568 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
569 SERCOM_CRITICAL_SECTION_LEAVE();
570 }
571
hri_sercomspi_get_CTRLA_CPHA_bit(const void * const hw)572 static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
573 {
574 uint32_t tmp;
575 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
576 tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
577 return (bool)tmp;
578 }
579
hri_sercomspi_write_CTRLA_CPHA_bit(const void * const hw,bool value)580 static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
581 {
582 uint32_t tmp;
583 SERCOM_CRITICAL_SECTION_ENTER();
584 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
585 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
586 tmp &= ~SERCOM_SPI_CTRLA_CPHA;
587 tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
588 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
589 SERCOM_CRITICAL_SECTION_LEAVE();
590 }
591
hri_sercomspi_clear_CTRLA_CPHA_bit(const void * const hw)592 static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
593 {
594 SERCOM_CRITICAL_SECTION_ENTER();
595 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
596 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
597 SERCOM_CRITICAL_SECTION_LEAVE();
598 }
599
hri_sercomspi_toggle_CTRLA_CPHA_bit(const void * const hw)600 static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
601 {
602 SERCOM_CRITICAL_SECTION_ENTER();
603 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
604 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
605 SERCOM_CRITICAL_SECTION_LEAVE();
606 }
607
hri_sercomspi_set_CTRLA_CPOL_bit(const void * const hw)608 static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
609 {
610 SERCOM_CRITICAL_SECTION_ENTER();
611 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
612 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
613 SERCOM_CRITICAL_SECTION_LEAVE();
614 }
615
hri_sercomspi_get_CTRLA_CPOL_bit(const void * const hw)616 static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
617 {
618 uint32_t tmp;
619 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
620 tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
621 return (bool)tmp;
622 }
623
hri_sercomspi_write_CTRLA_CPOL_bit(const void * const hw,bool value)624 static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
625 {
626 uint32_t tmp;
627 SERCOM_CRITICAL_SECTION_ENTER();
628 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
629 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
630 tmp &= ~SERCOM_SPI_CTRLA_CPOL;
631 tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
632 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
633 SERCOM_CRITICAL_SECTION_LEAVE();
634 }
635
hri_sercomspi_clear_CTRLA_CPOL_bit(const void * const hw)636 static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
637 {
638 SERCOM_CRITICAL_SECTION_ENTER();
639 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
640 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
641 SERCOM_CRITICAL_SECTION_LEAVE();
642 }
643
hri_sercomspi_toggle_CTRLA_CPOL_bit(const void * const hw)644 static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
645 {
646 SERCOM_CRITICAL_SECTION_ENTER();
647 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
648 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
649 SERCOM_CRITICAL_SECTION_LEAVE();
650 }
651
hri_sercomspi_set_CTRLA_DORD_bit(const void * const hw)652 static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
653 {
654 SERCOM_CRITICAL_SECTION_ENTER();
655 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
656 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
657 SERCOM_CRITICAL_SECTION_LEAVE();
658 }
659
hri_sercomspi_get_CTRLA_DORD_bit(const void * const hw)660 static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
661 {
662 uint32_t tmp;
663 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
664 tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
665 return (bool)tmp;
666 }
667
hri_sercomspi_write_CTRLA_DORD_bit(const void * const hw,bool value)668 static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
669 {
670 uint32_t tmp;
671 SERCOM_CRITICAL_SECTION_ENTER();
672 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
673 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
674 tmp &= ~SERCOM_SPI_CTRLA_DORD;
675 tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
676 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
677 SERCOM_CRITICAL_SECTION_LEAVE();
678 }
679
hri_sercomspi_clear_CTRLA_DORD_bit(const void * const hw)680 static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
681 {
682 SERCOM_CRITICAL_SECTION_ENTER();
683 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
684 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
685 SERCOM_CRITICAL_SECTION_LEAVE();
686 }
687
hri_sercomspi_toggle_CTRLA_DORD_bit(const void * const hw)688 static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
689 {
690 SERCOM_CRITICAL_SECTION_ENTER();
691 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
692 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
693 SERCOM_CRITICAL_SECTION_LEAVE();
694 }
695
hri_sercomspi_set_CTRLA_MODE_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)696 static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
697 {
698 SERCOM_CRITICAL_SECTION_ENTER();
699 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
700 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
701 SERCOM_CRITICAL_SECTION_LEAVE();
702 }
703
hri_sercomspi_get_CTRLA_MODE_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)704 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw,
705 hri_sercomspi_ctrla_reg_t mask)
706 {
707 uint32_t tmp;
708 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
709 tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
710 return tmp;
711 }
712
hri_sercomspi_write_CTRLA_MODE_bf(const void * const hw,hri_sercomspi_ctrla_reg_t data)713 static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
714 {
715 uint32_t tmp;
716 SERCOM_CRITICAL_SECTION_ENTER();
717 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
718 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
719 tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
720 tmp |= SERCOM_SPI_CTRLA_MODE(data);
721 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
722 SERCOM_CRITICAL_SECTION_LEAVE();
723 }
724
hri_sercomspi_clear_CTRLA_MODE_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)725 static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
726 {
727 SERCOM_CRITICAL_SECTION_ENTER();
728 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
729 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
730 SERCOM_CRITICAL_SECTION_LEAVE();
731 }
732
hri_sercomspi_toggle_CTRLA_MODE_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)733 static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
734 {
735 SERCOM_CRITICAL_SECTION_ENTER();
736 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
737 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
738 SERCOM_CRITICAL_SECTION_LEAVE();
739 }
740
hri_sercomspi_read_CTRLA_MODE_bf(const void * const hw)741 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
742 {
743 uint32_t tmp;
744 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
745 tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
746 return tmp;
747 }
748
hri_sercomspi_set_CTRLA_DOPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)749 static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
750 {
751 SERCOM_CRITICAL_SECTION_ENTER();
752 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
753 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
754 SERCOM_CRITICAL_SECTION_LEAVE();
755 }
756
hri_sercomspi_get_CTRLA_DOPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)757 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw,
758 hri_sercomspi_ctrla_reg_t mask)
759 {
760 uint32_t tmp;
761 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
762 tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
763 return tmp;
764 }
765
hri_sercomspi_write_CTRLA_DOPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t data)766 static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
767 {
768 uint32_t tmp;
769 SERCOM_CRITICAL_SECTION_ENTER();
770 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
771 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
772 tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
773 tmp |= SERCOM_SPI_CTRLA_DOPO(data);
774 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
775 SERCOM_CRITICAL_SECTION_LEAVE();
776 }
777
hri_sercomspi_clear_CTRLA_DOPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)778 static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
779 {
780 SERCOM_CRITICAL_SECTION_ENTER();
781 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
782 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
783 SERCOM_CRITICAL_SECTION_LEAVE();
784 }
785
hri_sercomspi_toggle_CTRLA_DOPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)786 static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
787 {
788 SERCOM_CRITICAL_SECTION_ENTER();
789 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
790 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
791 SERCOM_CRITICAL_SECTION_LEAVE();
792 }
793
hri_sercomspi_read_CTRLA_DOPO_bf(const void * const hw)794 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
795 {
796 uint32_t tmp;
797 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
798 tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
799 return tmp;
800 }
801
hri_sercomspi_set_CTRLA_DIPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)802 static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
803 {
804 SERCOM_CRITICAL_SECTION_ENTER();
805 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
806 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
807 SERCOM_CRITICAL_SECTION_LEAVE();
808 }
809
hri_sercomspi_get_CTRLA_DIPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)810 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw,
811 hri_sercomspi_ctrla_reg_t mask)
812 {
813 uint32_t tmp;
814 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
815 tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
816 return tmp;
817 }
818
hri_sercomspi_write_CTRLA_DIPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t data)819 static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
820 {
821 uint32_t tmp;
822 SERCOM_CRITICAL_SECTION_ENTER();
823 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
824 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
825 tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
826 tmp |= SERCOM_SPI_CTRLA_DIPO(data);
827 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
828 SERCOM_CRITICAL_SECTION_LEAVE();
829 }
830
hri_sercomspi_clear_CTRLA_DIPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)831 static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
832 {
833 SERCOM_CRITICAL_SECTION_ENTER();
834 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
835 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
836 SERCOM_CRITICAL_SECTION_LEAVE();
837 }
838
hri_sercomspi_toggle_CTRLA_DIPO_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)839 static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
840 {
841 SERCOM_CRITICAL_SECTION_ENTER();
842 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
843 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
844 SERCOM_CRITICAL_SECTION_LEAVE();
845 }
846
hri_sercomspi_read_CTRLA_DIPO_bf(const void * const hw)847 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
848 {
849 uint32_t tmp;
850 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
851 tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
852 return tmp;
853 }
854
hri_sercomspi_set_CTRLA_FORM_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)855 static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
856 {
857 SERCOM_CRITICAL_SECTION_ENTER();
858 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
859 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
860 SERCOM_CRITICAL_SECTION_LEAVE();
861 }
862
hri_sercomspi_get_CTRLA_FORM_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)863 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw,
864 hri_sercomspi_ctrla_reg_t mask)
865 {
866 uint32_t tmp;
867 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
868 tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
869 return tmp;
870 }
871
hri_sercomspi_write_CTRLA_FORM_bf(const void * const hw,hri_sercomspi_ctrla_reg_t data)872 static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
873 {
874 uint32_t tmp;
875 SERCOM_CRITICAL_SECTION_ENTER();
876 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
877 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
878 tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
879 tmp |= SERCOM_SPI_CTRLA_FORM(data);
880 ((Sercom *)hw)->SPI.CTRLA.reg = tmp;
881 SERCOM_CRITICAL_SECTION_LEAVE();
882 }
883
hri_sercomspi_clear_CTRLA_FORM_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)884 static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
885 {
886 SERCOM_CRITICAL_SECTION_ENTER();
887 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
888 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
889 SERCOM_CRITICAL_SECTION_LEAVE();
890 }
891
hri_sercomspi_toggle_CTRLA_FORM_bf(const void * const hw,hri_sercomspi_ctrla_reg_t mask)892 static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
893 {
894 SERCOM_CRITICAL_SECTION_ENTER();
895 hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
896 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
897 SERCOM_CRITICAL_SECTION_LEAVE();
898 }
899
hri_sercomspi_read_CTRLA_FORM_bf(const void * const hw)900 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
901 {
902 uint32_t tmp;
903 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
904 tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
905 return tmp;
906 }
907
hri_sercomspi_set_CTRLA_reg(const void * const hw,hri_sercomspi_ctrla_reg_t mask)908 static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
909 {
910 SERCOM_CRITICAL_SECTION_ENTER();
911 ((Sercom *)hw)->SPI.CTRLA.reg |= mask;
912 SERCOM_CRITICAL_SECTION_LEAVE();
913 }
914
hri_sercomspi_get_CTRLA_reg(const void * const hw,hri_sercomspi_ctrla_reg_t mask)915 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw,
916 hri_sercomspi_ctrla_reg_t mask)
917 {
918 uint32_t tmp;
919 tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
920 tmp &= mask;
921 return tmp;
922 }
923
hri_sercomspi_write_CTRLA_reg(const void * const hw,hri_sercomspi_ctrla_reg_t data)924 static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
925 {
926 SERCOM_CRITICAL_SECTION_ENTER();
927 ((Sercom *)hw)->SPI.CTRLA.reg = data;
928 SERCOM_CRITICAL_SECTION_LEAVE();
929 }
930
hri_sercomspi_clear_CTRLA_reg(const void * const hw,hri_sercomspi_ctrla_reg_t mask)931 static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
932 {
933 SERCOM_CRITICAL_SECTION_ENTER();
934 ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
935 SERCOM_CRITICAL_SECTION_LEAVE();
936 }
937
hri_sercomspi_toggle_CTRLA_reg(const void * const hw,hri_sercomspi_ctrla_reg_t mask)938 static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
939 {
940 SERCOM_CRITICAL_SECTION_ENTER();
941 ((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
942 SERCOM_CRITICAL_SECTION_LEAVE();
943 }
944
hri_sercomspi_read_CTRLA_reg(const void * const hw)945 static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
946 {
947 return ((Sercom *)hw)->SPI.CTRLA.reg;
948 }
949
hri_sercomspi_set_CTRLB_PLOADEN_bit(const void * const hw)950 static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
951 {
952 SERCOM_CRITICAL_SECTION_ENTER();
953 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
954 SERCOM_CRITICAL_SECTION_LEAVE();
955 }
956
hri_sercomspi_get_CTRLB_PLOADEN_bit(const void * const hw)957 static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
958 {
959 uint32_t tmp;
960 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
961 tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
962 return (bool)tmp;
963 }
964
hri_sercomspi_write_CTRLB_PLOADEN_bit(const void * const hw,bool value)965 static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
966 {
967 uint32_t tmp;
968 SERCOM_CRITICAL_SECTION_ENTER();
969 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
970 tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
971 tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
972 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
973 SERCOM_CRITICAL_SECTION_LEAVE();
974 }
975
hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void * const hw)976 static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
977 {
978 SERCOM_CRITICAL_SECTION_ENTER();
979 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
980 SERCOM_CRITICAL_SECTION_LEAVE();
981 }
982
hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void * const hw)983 static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
984 {
985 SERCOM_CRITICAL_SECTION_ENTER();
986 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
987 SERCOM_CRITICAL_SECTION_LEAVE();
988 }
989
hri_sercomspi_set_CTRLB_SSDE_bit(const void * const hw)990 static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
991 {
992 SERCOM_CRITICAL_SECTION_ENTER();
993 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
994 SERCOM_CRITICAL_SECTION_LEAVE();
995 }
996
hri_sercomspi_get_CTRLB_SSDE_bit(const void * const hw)997 static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
998 {
999 uint32_t tmp;
1000 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1001 tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
1002 return (bool)tmp;
1003 }
1004
hri_sercomspi_write_CTRLB_SSDE_bit(const void * const hw,bool value)1005 static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
1006 {
1007 uint32_t tmp;
1008 SERCOM_CRITICAL_SECTION_ENTER();
1009 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1010 tmp &= ~SERCOM_SPI_CTRLB_SSDE;
1011 tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
1012 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
1013 SERCOM_CRITICAL_SECTION_LEAVE();
1014 }
1015
hri_sercomspi_clear_CTRLB_SSDE_bit(const void * const hw)1016 static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
1017 {
1018 SERCOM_CRITICAL_SECTION_ENTER();
1019 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
1020 SERCOM_CRITICAL_SECTION_LEAVE();
1021 }
1022
hri_sercomspi_toggle_CTRLB_SSDE_bit(const void * const hw)1023 static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
1024 {
1025 SERCOM_CRITICAL_SECTION_ENTER();
1026 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
1027 SERCOM_CRITICAL_SECTION_LEAVE();
1028 }
1029
hri_sercomspi_set_CTRLB_MSSEN_bit(const void * const hw)1030 static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
1031 {
1032 SERCOM_CRITICAL_SECTION_ENTER();
1033 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
1034 SERCOM_CRITICAL_SECTION_LEAVE();
1035 }
1036
hri_sercomspi_get_CTRLB_MSSEN_bit(const void * const hw)1037 static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
1038 {
1039 uint32_t tmp;
1040 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1041 tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
1042 return (bool)tmp;
1043 }
1044
hri_sercomspi_write_CTRLB_MSSEN_bit(const void * const hw,bool value)1045 static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
1046 {
1047 uint32_t tmp;
1048 SERCOM_CRITICAL_SECTION_ENTER();
1049 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1050 tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
1051 tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
1052 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
1053 SERCOM_CRITICAL_SECTION_LEAVE();
1054 }
1055
hri_sercomspi_clear_CTRLB_MSSEN_bit(const void * const hw)1056 static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
1057 {
1058 SERCOM_CRITICAL_SECTION_ENTER();
1059 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
1060 SERCOM_CRITICAL_SECTION_LEAVE();
1061 }
1062
hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void * const hw)1063 static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
1064 {
1065 SERCOM_CRITICAL_SECTION_ENTER();
1066 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
1067 SERCOM_CRITICAL_SECTION_LEAVE();
1068 }
1069
hri_sercomspi_set_CTRLB_RXEN_bit(const void * const hw)1070 static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
1071 {
1072 SERCOM_CRITICAL_SECTION_ENTER();
1073 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
1074 SERCOM_CRITICAL_SECTION_LEAVE();
1075 }
1076
hri_sercomspi_get_CTRLB_RXEN_bit(const void * const hw)1077 static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
1078 {
1079 uint32_t tmp;
1080 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1081 tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
1082 return (bool)tmp;
1083 }
1084
hri_sercomspi_write_CTRLB_RXEN_bit(const void * const hw,bool value)1085 static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
1086 {
1087 uint32_t tmp;
1088 SERCOM_CRITICAL_SECTION_ENTER();
1089 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1090 tmp &= ~SERCOM_SPI_CTRLB_RXEN;
1091 tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
1092 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
1093 SERCOM_CRITICAL_SECTION_LEAVE();
1094 }
1095
hri_sercomspi_clear_CTRLB_RXEN_bit(const void * const hw)1096 static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
1097 {
1098 SERCOM_CRITICAL_SECTION_ENTER();
1099 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
1100 SERCOM_CRITICAL_SECTION_LEAVE();
1101 }
1102
hri_sercomspi_toggle_CTRLB_RXEN_bit(const void * const hw)1103 static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
1104 {
1105 SERCOM_CRITICAL_SECTION_ENTER();
1106 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
1107 SERCOM_CRITICAL_SECTION_LEAVE();
1108 }
1109
hri_sercomspi_set_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1110 static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1111 {
1112 SERCOM_CRITICAL_SECTION_ENTER();
1113 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
1114 SERCOM_CRITICAL_SECTION_LEAVE();
1115 }
1116
hri_sercomspi_get_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1117 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw,
1118 hri_sercomspi_ctrlb_reg_t mask)
1119 {
1120 uint32_t tmp;
1121 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1122 tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
1123 return tmp;
1124 }
1125
hri_sercomspi_write_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t data)1126 static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
1127 {
1128 uint32_t tmp;
1129 SERCOM_CRITICAL_SECTION_ENTER();
1130 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1131 tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
1132 tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
1133 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
1134 SERCOM_CRITICAL_SECTION_LEAVE();
1135 }
1136
hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1137 static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1138 {
1139 SERCOM_CRITICAL_SECTION_ENTER();
1140 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
1141 SERCOM_CRITICAL_SECTION_LEAVE();
1142 }
1143
hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1144 static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1145 {
1146 SERCOM_CRITICAL_SECTION_ENTER();
1147 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
1148 SERCOM_CRITICAL_SECTION_LEAVE();
1149 }
1150
hri_sercomspi_read_CTRLB_CHSIZE_bf(const void * const hw)1151 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
1152 {
1153 uint32_t tmp;
1154 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1155 tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
1156 return tmp;
1157 }
1158
hri_sercomspi_set_CTRLB_AMODE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1159 static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1160 {
1161 SERCOM_CRITICAL_SECTION_ENTER();
1162 ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
1163 SERCOM_CRITICAL_SECTION_LEAVE();
1164 }
1165
hri_sercomspi_get_CTRLB_AMODE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1166 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw,
1167 hri_sercomspi_ctrlb_reg_t mask)
1168 {
1169 uint32_t tmp;
1170 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1171 tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
1172 return tmp;
1173 }
1174
hri_sercomspi_write_CTRLB_AMODE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t data)1175 static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
1176 {
1177 uint32_t tmp;
1178 SERCOM_CRITICAL_SECTION_ENTER();
1179 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1180 tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
1181 tmp |= SERCOM_SPI_CTRLB_AMODE(data);
1182 ((Sercom *)hw)->SPI.CTRLB.reg = tmp;
1183 SERCOM_CRITICAL_SECTION_LEAVE();
1184 }
1185
hri_sercomspi_clear_CTRLB_AMODE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1186 static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1187 {
1188 SERCOM_CRITICAL_SECTION_ENTER();
1189 ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
1190 SERCOM_CRITICAL_SECTION_LEAVE();
1191 }
1192
hri_sercomspi_toggle_CTRLB_AMODE_bf(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1193 static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1194 {
1195 SERCOM_CRITICAL_SECTION_ENTER();
1196 ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
1197 SERCOM_CRITICAL_SECTION_LEAVE();
1198 }
1199
hri_sercomspi_read_CTRLB_AMODE_bf(const void * const hw)1200 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
1201 {
1202 uint32_t tmp;
1203 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1204 tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
1205 return tmp;
1206 }
1207
hri_sercomspi_set_CTRLB_reg(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1208 static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1209 {
1210 SERCOM_CRITICAL_SECTION_ENTER();
1211 ((Sercom *)hw)->SPI.CTRLB.reg |= mask;
1212 SERCOM_CRITICAL_SECTION_LEAVE();
1213 }
1214
hri_sercomspi_get_CTRLB_reg(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1215 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw,
1216 hri_sercomspi_ctrlb_reg_t mask)
1217 {
1218 uint32_t tmp;
1219 tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
1220 tmp &= mask;
1221 return tmp;
1222 }
1223
hri_sercomspi_write_CTRLB_reg(const void * const hw,hri_sercomspi_ctrlb_reg_t data)1224 static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
1225 {
1226 SERCOM_CRITICAL_SECTION_ENTER();
1227 ((Sercom *)hw)->SPI.CTRLB.reg = data;
1228 SERCOM_CRITICAL_SECTION_LEAVE();
1229 }
1230
hri_sercomspi_clear_CTRLB_reg(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1231 static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1232 {
1233 SERCOM_CRITICAL_SECTION_ENTER();
1234 ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
1235 SERCOM_CRITICAL_SECTION_LEAVE();
1236 }
1237
hri_sercomspi_toggle_CTRLB_reg(const void * const hw,hri_sercomspi_ctrlb_reg_t mask)1238 static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
1239 {
1240 SERCOM_CRITICAL_SECTION_ENTER();
1241 ((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
1242 SERCOM_CRITICAL_SECTION_LEAVE();
1243 }
1244
hri_sercomspi_read_CTRLB_reg(const void * const hw)1245 static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
1246 {
1247 return ((Sercom *)hw)->SPI.CTRLB.reg;
1248 }
1249
hri_sercomspi_set_BAUD_BAUD_bf(const void * const hw,hri_sercomspi_baud_reg_t mask)1250 static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
1251 {
1252 SERCOM_CRITICAL_SECTION_ENTER();
1253 ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
1254 SERCOM_CRITICAL_SECTION_LEAVE();
1255 }
1256
hri_sercomspi_get_BAUD_BAUD_bf(const void * const hw,hri_sercomspi_baud_reg_t mask)1257 static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw,
1258 hri_sercomspi_baud_reg_t mask)
1259 {
1260 uint8_t tmp;
1261 tmp = ((Sercom *)hw)->SPI.BAUD.reg;
1262 tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
1263 return tmp;
1264 }
1265
hri_sercomspi_write_BAUD_BAUD_bf(const void * const hw,hri_sercomspi_baud_reg_t data)1266 static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
1267 {
1268 uint8_t tmp;
1269 SERCOM_CRITICAL_SECTION_ENTER();
1270 tmp = ((Sercom *)hw)->SPI.BAUD.reg;
1271 tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
1272 tmp |= SERCOM_SPI_BAUD_BAUD(data);
1273 ((Sercom *)hw)->SPI.BAUD.reg = tmp;
1274 SERCOM_CRITICAL_SECTION_LEAVE();
1275 }
1276
hri_sercomspi_clear_BAUD_BAUD_bf(const void * const hw,hri_sercomspi_baud_reg_t mask)1277 static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
1278 {
1279 SERCOM_CRITICAL_SECTION_ENTER();
1280 ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
1281 SERCOM_CRITICAL_SECTION_LEAVE();
1282 }
1283
hri_sercomspi_toggle_BAUD_BAUD_bf(const void * const hw,hri_sercomspi_baud_reg_t mask)1284 static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
1285 {
1286 SERCOM_CRITICAL_SECTION_ENTER();
1287 ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
1288 SERCOM_CRITICAL_SECTION_LEAVE();
1289 }
1290
hri_sercomspi_read_BAUD_BAUD_bf(const void * const hw)1291 static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
1292 {
1293 uint8_t tmp;
1294 tmp = ((Sercom *)hw)->SPI.BAUD.reg;
1295 tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
1296 return tmp;
1297 }
1298
hri_sercomspi_set_BAUD_reg(const void * const hw,hri_sercomspi_baud_reg_t mask)1299 static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
1300 {
1301 SERCOM_CRITICAL_SECTION_ENTER();
1302 ((Sercom *)hw)->SPI.BAUD.reg |= mask;
1303 SERCOM_CRITICAL_SECTION_LEAVE();
1304 }
1305
hri_sercomspi_get_BAUD_reg(const void * const hw,hri_sercomspi_baud_reg_t mask)1306 static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
1307 {
1308 uint8_t tmp;
1309 tmp = ((Sercom *)hw)->SPI.BAUD.reg;
1310 tmp &= mask;
1311 return tmp;
1312 }
1313
hri_sercomspi_write_BAUD_reg(const void * const hw,hri_sercomspi_baud_reg_t data)1314 static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
1315 {
1316 SERCOM_CRITICAL_SECTION_ENTER();
1317 ((Sercom *)hw)->SPI.BAUD.reg = data;
1318 SERCOM_CRITICAL_SECTION_LEAVE();
1319 }
1320
hri_sercomspi_clear_BAUD_reg(const void * const hw,hri_sercomspi_baud_reg_t mask)1321 static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
1322 {
1323 SERCOM_CRITICAL_SECTION_ENTER();
1324 ((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
1325 SERCOM_CRITICAL_SECTION_LEAVE();
1326 }
1327
hri_sercomspi_toggle_BAUD_reg(const void * const hw,hri_sercomspi_baud_reg_t mask)1328 static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
1329 {
1330 SERCOM_CRITICAL_SECTION_ENTER();
1331 ((Sercom *)hw)->SPI.BAUD.reg ^= mask;
1332 SERCOM_CRITICAL_SECTION_LEAVE();
1333 }
1334
hri_sercomspi_read_BAUD_reg(const void * const hw)1335 static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
1336 {
1337 return ((Sercom *)hw)->SPI.BAUD.reg;
1338 }
1339
hri_sercomspi_set_ADDR_ADDR_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1340 static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1341 {
1342 SERCOM_CRITICAL_SECTION_ENTER();
1343 ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
1344 SERCOM_CRITICAL_SECTION_LEAVE();
1345 }
1346
hri_sercomspi_get_ADDR_ADDR_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1347 static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw,
1348 hri_sercomspi_addr_reg_t mask)
1349 {
1350 uint32_t tmp;
1351 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1352 tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
1353 return tmp;
1354 }
1355
hri_sercomspi_write_ADDR_ADDR_bf(const void * const hw,hri_sercomspi_addr_reg_t data)1356 static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
1357 {
1358 uint32_t tmp;
1359 SERCOM_CRITICAL_SECTION_ENTER();
1360 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1361 tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
1362 tmp |= SERCOM_SPI_ADDR_ADDR(data);
1363 ((Sercom *)hw)->SPI.ADDR.reg = tmp;
1364 SERCOM_CRITICAL_SECTION_LEAVE();
1365 }
1366
hri_sercomspi_clear_ADDR_ADDR_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1367 static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1368 {
1369 SERCOM_CRITICAL_SECTION_ENTER();
1370 ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
1371 SERCOM_CRITICAL_SECTION_LEAVE();
1372 }
1373
hri_sercomspi_toggle_ADDR_ADDR_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1374 static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1375 {
1376 SERCOM_CRITICAL_SECTION_ENTER();
1377 ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
1378 SERCOM_CRITICAL_SECTION_LEAVE();
1379 }
1380
hri_sercomspi_read_ADDR_ADDR_bf(const void * const hw)1381 static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
1382 {
1383 uint32_t tmp;
1384 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1385 tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
1386 return tmp;
1387 }
1388
hri_sercomspi_set_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1389 static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1390 {
1391 SERCOM_CRITICAL_SECTION_ENTER();
1392 ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
1393 SERCOM_CRITICAL_SECTION_LEAVE();
1394 }
1395
hri_sercomspi_get_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1396 static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw,
1397 hri_sercomspi_addr_reg_t mask)
1398 {
1399 uint32_t tmp;
1400 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1401 tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
1402 return tmp;
1403 }
1404
hri_sercomspi_write_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomspi_addr_reg_t data)1405 static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
1406 {
1407 uint32_t tmp;
1408 SERCOM_CRITICAL_SECTION_ENTER();
1409 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1410 tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
1411 tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
1412 ((Sercom *)hw)->SPI.ADDR.reg = tmp;
1413 SERCOM_CRITICAL_SECTION_LEAVE();
1414 }
1415
hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1416 static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1417 {
1418 SERCOM_CRITICAL_SECTION_ENTER();
1419 ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
1420 SERCOM_CRITICAL_SECTION_LEAVE();
1421 }
1422
hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomspi_addr_reg_t mask)1423 static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
1424 {
1425 SERCOM_CRITICAL_SECTION_ENTER();
1426 ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
1427 SERCOM_CRITICAL_SECTION_LEAVE();
1428 }
1429
hri_sercomspi_read_ADDR_ADDRMASK_bf(const void * const hw)1430 static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
1431 {
1432 uint32_t tmp;
1433 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1434 tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
1435 return tmp;
1436 }
1437
hri_sercomspi_set_ADDR_reg(const void * const hw,hri_sercomspi_addr_reg_t mask)1438 static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
1439 {
1440 SERCOM_CRITICAL_SECTION_ENTER();
1441 ((Sercom *)hw)->SPI.ADDR.reg |= mask;
1442 SERCOM_CRITICAL_SECTION_LEAVE();
1443 }
1444
hri_sercomspi_get_ADDR_reg(const void * const hw,hri_sercomspi_addr_reg_t mask)1445 static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
1446 {
1447 uint32_t tmp;
1448 tmp = ((Sercom *)hw)->SPI.ADDR.reg;
1449 tmp &= mask;
1450 return tmp;
1451 }
1452
hri_sercomspi_write_ADDR_reg(const void * const hw,hri_sercomspi_addr_reg_t data)1453 static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
1454 {
1455 SERCOM_CRITICAL_SECTION_ENTER();
1456 ((Sercom *)hw)->SPI.ADDR.reg = data;
1457 SERCOM_CRITICAL_SECTION_LEAVE();
1458 }
1459
hri_sercomspi_clear_ADDR_reg(const void * const hw,hri_sercomspi_addr_reg_t mask)1460 static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
1461 {
1462 SERCOM_CRITICAL_SECTION_ENTER();
1463 ((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
1464 SERCOM_CRITICAL_SECTION_LEAVE();
1465 }
1466
hri_sercomspi_toggle_ADDR_reg(const void * const hw,hri_sercomspi_addr_reg_t mask)1467 static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
1468 {
1469 SERCOM_CRITICAL_SECTION_ENTER();
1470 ((Sercom *)hw)->SPI.ADDR.reg ^= mask;
1471 SERCOM_CRITICAL_SECTION_LEAVE();
1472 }
1473
hri_sercomspi_read_ADDR_reg(const void * const hw)1474 static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
1475 {
1476 return ((Sercom *)hw)->SPI.ADDR.reg;
1477 }
1478
hri_sercomspi_read_DATA_reg(const void * const hw)1479 static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
1480 {
1481 return ((Sercom *)hw)->SPI.DATA.reg;
1482 }
1483
hri_sercomspi_write_DATA_reg(const void * const hw,hri_sercomspi_data_reg_t data)1484 static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
1485 {
1486 SERCOM_CRITICAL_SECTION_ENTER();
1487 ((Sercom *)hw)->SPI.DATA.reg = data;
1488 SERCOM_CRITICAL_SECTION_LEAVE();
1489 }
1490
hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void * const hw)1491 static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
1492 {
1493 SERCOM_CRITICAL_SECTION_ENTER();
1494 ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
1495 SERCOM_CRITICAL_SECTION_LEAVE();
1496 }
1497
hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void * const hw)1498 static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
1499 {
1500 uint8_t tmp;
1501 tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
1502 tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
1503 return (bool)tmp;
1504 }
1505
hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void * const hw,bool value)1506 static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
1507 {
1508 uint8_t tmp;
1509 SERCOM_CRITICAL_SECTION_ENTER();
1510 tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
1511 tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
1512 tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
1513 ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
1514 SERCOM_CRITICAL_SECTION_LEAVE();
1515 }
1516
hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void * const hw)1517 static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
1518 {
1519 SERCOM_CRITICAL_SECTION_ENTER();
1520 ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
1521 SERCOM_CRITICAL_SECTION_LEAVE();
1522 }
1523
hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void * const hw)1524 static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
1525 {
1526 SERCOM_CRITICAL_SECTION_ENTER();
1527 ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
1528 SERCOM_CRITICAL_SECTION_LEAVE();
1529 }
1530
hri_sercomspi_set_DBGCTRL_reg(const void * const hw,hri_sercomspi_dbgctrl_reg_t mask)1531 static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
1532 {
1533 SERCOM_CRITICAL_SECTION_ENTER();
1534 ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
1535 SERCOM_CRITICAL_SECTION_LEAVE();
1536 }
1537
hri_sercomspi_get_DBGCTRL_reg(const void * const hw,hri_sercomspi_dbgctrl_reg_t mask)1538 static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw,
1539 hri_sercomspi_dbgctrl_reg_t mask)
1540 {
1541 uint8_t tmp;
1542 tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
1543 tmp &= mask;
1544 return tmp;
1545 }
1546
hri_sercomspi_write_DBGCTRL_reg(const void * const hw,hri_sercomspi_dbgctrl_reg_t data)1547 static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
1548 {
1549 SERCOM_CRITICAL_SECTION_ENTER();
1550 ((Sercom *)hw)->SPI.DBGCTRL.reg = data;
1551 SERCOM_CRITICAL_SECTION_LEAVE();
1552 }
1553
hri_sercomspi_clear_DBGCTRL_reg(const void * const hw,hri_sercomspi_dbgctrl_reg_t mask)1554 static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
1555 {
1556 SERCOM_CRITICAL_SECTION_ENTER();
1557 ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
1558 SERCOM_CRITICAL_SECTION_LEAVE();
1559 }
1560
hri_sercomspi_toggle_DBGCTRL_reg(const void * const hw,hri_sercomspi_dbgctrl_reg_t mask)1561 static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
1562 {
1563 SERCOM_CRITICAL_SECTION_ENTER();
1564 ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
1565 SERCOM_CRITICAL_SECTION_LEAVE();
1566 }
1567
hri_sercomspi_read_DBGCTRL_reg(const void * const hw)1568 static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
1569 {
1570 return ((Sercom *)hw)->SPI.DBGCTRL.reg;
1571 }
1572
hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void * const hw)1573 static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
1574 {
1575 return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
1576 }
1577
hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void * const hw)1578 static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
1579 {
1580 return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
1581 }
1582
hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void * const hw)1583 static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
1584 {
1585 return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
1586 }
1587
hri_sercomspi_get_SYNCBUSY_reg(const void * const hw,hri_sercomspi_syncbusy_reg_t mask)1588 static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw,
1589 hri_sercomspi_syncbusy_reg_t mask)
1590 {
1591 uint32_t tmp;
1592 tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
1593 tmp &= mask;
1594 return tmp;
1595 }
1596
hri_sercomspi_read_SYNCBUSY_reg(const void * const hw)1597 static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
1598 {
1599 return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
1600 }
1601
hri_sercomspi_get_STATUS_BUFOVF_bit(const void * const hw)1602 static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
1603 {
1604 return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
1605 }
1606
hri_sercomspi_clear_STATUS_BUFOVF_bit(const void * const hw)1607 static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
1608 {
1609 SERCOM_CRITICAL_SECTION_ENTER();
1610 ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
1611 SERCOM_CRITICAL_SECTION_LEAVE();
1612 }
1613
hri_sercomspi_get_STATUS_reg(const void * const hw,hri_sercomspi_status_reg_t mask)1614 static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw,
1615 hri_sercomspi_status_reg_t mask)
1616 {
1617 uint16_t tmp;
1618 tmp = ((Sercom *)hw)->SPI.STATUS.reg;
1619 tmp &= mask;
1620 return tmp;
1621 }
1622
hri_sercomspi_clear_STATUS_reg(const void * const hw,hri_sercomspi_status_reg_t mask)1623 static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
1624 {
1625 SERCOM_CRITICAL_SECTION_ENTER();
1626 ((Sercom *)hw)->SPI.STATUS.reg = mask;
1627 SERCOM_CRITICAL_SECTION_LEAVE();
1628 }
1629
hri_sercomspi_read_STATUS_reg(const void * const hw)1630 static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
1631 {
1632 return ((Sercom *)hw)->SPI.STATUS.reg;
1633 }
1634
hri_sercomi2cm_set_INTEN_MB_bit(const void * const hw)1635 static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
1636 {
1637 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
1638 }
1639
hri_sercomi2cm_get_INTEN_MB_bit(const void * const hw)1640 static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
1641 {
1642 return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
1643 }
1644
hri_sercomi2cm_write_INTEN_MB_bit(const void * const hw,bool value)1645 static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
1646 {
1647 if (value == 0x0) {
1648 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
1649 } else {
1650 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
1651 }
1652 }
1653
hri_sercomi2cm_clear_INTEN_MB_bit(const void * const hw)1654 static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
1655 {
1656 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
1657 }
1658
hri_sercomi2cm_set_INTEN_SB_bit(const void * const hw)1659 static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
1660 {
1661 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
1662 }
1663
hri_sercomi2cm_get_INTEN_SB_bit(const void * const hw)1664 static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
1665 {
1666 return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
1667 }
1668
hri_sercomi2cm_write_INTEN_SB_bit(const void * const hw,bool value)1669 static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
1670 {
1671 if (value == 0x0) {
1672 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
1673 } else {
1674 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
1675 }
1676 }
1677
hri_sercomi2cm_clear_INTEN_SB_bit(const void * const hw)1678 static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
1679 {
1680 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
1681 }
1682
hri_sercomi2cm_set_INTEN_ERROR_bit(const void * const hw)1683 static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
1684 {
1685 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
1686 }
1687
hri_sercomi2cm_get_INTEN_ERROR_bit(const void * const hw)1688 static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
1689 {
1690 return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
1691 }
1692
hri_sercomi2cm_write_INTEN_ERROR_bit(const void * const hw,bool value)1693 static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
1694 {
1695 if (value == 0x0) {
1696 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
1697 } else {
1698 ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
1699 }
1700 }
1701
hri_sercomi2cm_clear_INTEN_ERROR_bit(const void * const hw)1702 static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
1703 {
1704 ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
1705 }
1706
hri_sercomi2cm_set_INTEN_reg(const void * const hw,hri_sercomi2cm_intenset_reg_t mask)1707 static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
1708 {
1709 ((Sercom *)hw)->I2CM.INTENSET.reg = mask;
1710 }
1711
hri_sercomi2cm_get_INTEN_reg(const void * const hw,hri_sercomi2cm_intenset_reg_t mask)1712 static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw,
1713 hri_sercomi2cm_intenset_reg_t mask)
1714 {
1715 uint8_t tmp;
1716 tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
1717 tmp &= mask;
1718 return tmp;
1719 }
1720
hri_sercomi2cm_read_INTEN_reg(const void * const hw)1721 static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
1722 {
1723 return ((Sercom *)hw)->I2CM.INTENSET.reg;
1724 }
1725
hri_sercomi2cm_write_INTEN_reg(const void * const hw,hri_sercomi2cm_intenset_reg_t data)1726 static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
1727 {
1728 ((Sercom *)hw)->I2CM.INTENSET.reg = data;
1729 ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
1730 }
1731
hri_sercomi2cm_clear_INTEN_reg(const void * const hw,hri_sercomi2cm_intenset_reg_t mask)1732 static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
1733 {
1734 ((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
1735 }
1736
hri_sercomi2cm_get_INTFLAG_MB_bit(const void * const hw)1737 static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
1738 {
1739 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
1740 }
1741
hri_sercomi2cm_clear_INTFLAG_MB_bit(const void * const hw)1742 static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
1743 {
1744 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
1745 }
1746
hri_sercomi2cm_get_INTFLAG_SB_bit(const void * const hw)1747 static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
1748 {
1749 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
1750 }
1751
hri_sercomi2cm_clear_INTFLAG_SB_bit(const void * const hw)1752 static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
1753 {
1754 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
1755 }
1756
hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void * const hw)1757 static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
1758 {
1759 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
1760 }
1761
hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void * const hw)1762 static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
1763 {
1764 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
1765 }
1766
hri_sercomi2cm_get_interrupt_MB_bit(const void * const hw)1767 static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
1768 {
1769 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
1770 }
1771
hri_sercomi2cm_clear_interrupt_MB_bit(const void * const hw)1772 static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
1773 {
1774 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
1775 }
1776
hri_sercomi2cm_get_interrupt_SB_bit(const void * const hw)1777 static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
1778 {
1779 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
1780 }
1781
hri_sercomi2cm_clear_interrupt_SB_bit(const void * const hw)1782 static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
1783 {
1784 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
1785 }
1786
hri_sercomi2cm_get_interrupt_ERROR_bit(const void * const hw)1787 static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
1788 {
1789 return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
1790 }
1791
hri_sercomi2cm_clear_interrupt_ERROR_bit(const void * const hw)1792 static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
1793 {
1794 ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
1795 }
1796
hri_sercomi2cm_get_INTFLAG_reg(const void * const hw,hri_sercomi2cm_intflag_reg_t mask)1797 static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw,
1798 hri_sercomi2cm_intflag_reg_t mask)
1799 {
1800 uint8_t tmp;
1801 tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
1802 tmp &= mask;
1803 return tmp;
1804 }
1805
hri_sercomi2cm_read_INTFLAG_reg(const void * const hw)1806 static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
1807 {
1808 return ((Sercom *)hw)->I2CM.INTFLAG.reg;
1809 }
1810
hri_sercomi2cm_clear_INTFLAG_reg(const void * const hw,hri_sercomi2cm_intflag_reg_t mask)1811 static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
1812 {
1813 ((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
1814 }
1815
hri_sercomi2cm_set_STATUS_BUSERR_bit(const void * const hw)1816 static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
1817 {
1818 SERCOM_CRITICAL_SECTION_ENTER();
1819 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
1820 SERCOM_CRITICAL_SECTION_LEAVE();
1821 }
1822
hri_sercomi2cm_get_STATUS_BUSERR_bit(const void * const hw)1823 static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
1824 {
1825 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
1826 }
1827
hri_sercomi2cm_write_STATUS_BUSERR_bit(const void * const hw,bool value)1828 static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
1829 {
1830 uint16_t tmp;
1831 SERCOM_CRITICAL_SECTION_ENTER();
1832 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
1833 tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
1834 tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
1835 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
1836 SERCOM_CRITICAL_SECTION_LEAVE();
1837 }
1838
hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void * const hw)1839 static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
1840 {
1841 SERCOM_CRITICAL_SECTION_ENTER();
1842 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
1843 SERCOM_CRITICAL_SECTION_LEAVE();
1844 }
1845
hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void * const hw)1846 static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
1847 {
1848 SERCOM_CRITICAL_SECTION_ENTER();
1849 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
1850 SERCOM_CRITICAL_SECTION_LEAVE();
1851 }
1852
hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void * const hw)1853 static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
1854 {
1855 SERCOM_CRITICAL_SECTION_ENTER();
1856 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
1857 SERCOM_CRITICAL_SECTION_LEAVE();
1858 }
1859
hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void * const hw)1860 static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
1861 {
1862 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
1863 }
1864
hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void * const hw,bool value)1865 static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
1866 {
1867 uint16_t tmp;
1868 SERCOM_CRITICAL_SECTION_ENTER();
1869 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
1870 tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
1871 tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
1872 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
1873 SERCOM_CRITICAL_SECTION_LEAVE();
1874 }
1875
hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void * const hw)1876 static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
1877 {
1878 SERCOM_CRITICAL_SECTION_ENTER();
1879 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
1880 SERCOM_CRITICAL_SECTION_LEAVE();
1881 }
1882
hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void * const hw)1883 static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
1884 {
1885 SERCOM_CRITICAL_SECTION_ENTER();
1886 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
1887 SERCOM_CRITICAL_SECTION_LEAVE();
1888 }
1889
hri_sercomi2cm_set_STATUS_RXNACK_bit(const void * const hw)1890 static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
1891 {
1892 SERCOM_CRITICAL_SECTION_ENTER();
1893 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
1894 SERCOM_CRITICAL_SECTION_LEAVE();
1895 }
1896
hri_sercomi2cm_get_STATUS_RXNACK_bit(const void * const hw)1897 static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
1898 {
1899 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
1900 }
1901
hri_sercomi2cm_write_STATUS_RXNACK_bit(const void * const hw,bool value)1902 static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
1903 {
1904 uint16_t tmp;
1905 SERCOM_CRITICAL_SECTION_ENTER();
1906 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
1907 tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
1908 tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
1909 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
1910 SERCOM_CRITICAL_SECTION_LEAVE();
1911 }
1912
hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void * const hw)1913 static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
1914 {
1915 SERCOM_CRITICAL_SECTION_ENTER();
1916 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
1917 SERCOM_CRITICAL_SECTION_LEAVE();
1918 }
1919
hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void * const hw)1920 static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
1921 {
1922 SERCOM_CRITICAL_SECTION_ENTER();
1923 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
1924 SERCOM_CRITICAL_SECTION_LEAVE();
1925 }
1926
hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void * const hw)1927 static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
1928 {
1929 SERCOM_CRITICAL_SECTION_ENTER();
1930 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
1931 SERCOM_CRITICAL_SECTION_LEAVE();
1932 }
1933
hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void * const hw)1934 static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
1935 {
1936 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
1937 }
1938
hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void * const hw,bool value)1939 static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
1940 {
1941 uint16_t tmp;
1942 SERCOM_CRITICAL_SECTION_ENTER();
1943 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
1944 tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
1945 tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
1946 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
1947 SERCOM_CRITICAL_SECTION_LEAVE();
1948 }
1949
hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void * const hw)1950 static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
1951 {
1952 SERCOM_CRITICAL_SECTION_ENTER();
1953 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
1954 SERCOM_CRITICAL_SECTION_LEAVE();
1955 }
1956
hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void * const hw)1957 static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
1958 {
1959 SERCOM_CRITICAL_SECTION_ENTER();
1960 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
1961 SERCOM_CRITICAL_SECTION_LEAVE();
1962 }
1963
hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void * const hw)1964 static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
1965 {
1966 SERCOM_CRITICAL_SECTION_ENTER();
1967 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
1968 SERCOM_CRITICAL_SECTION_LEAVE();
1969 }
1970
hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void * const hw)1971 static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
1972 {
1973 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
1974 }
1975
hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void * const hw,bool value)1976 static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
1977 {
1978 uint16_t tmp;
1979 SERCOM_CRITICAL_SECTION_ENTER();
1980 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
1981 tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
1982 tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
1983 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
1984 SERCOM_CRITICAL_SECTION_LEAVE();
1985 }
1986
hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void * const hw)1987 static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
1988 {
1989 SERCOM_CRITICAL_SECTION_ENTER();
1990 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
1991 SERCOM_CRITICAL_SECTION_LEAVE();
1992 }
1993
hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void * const hw)1994 static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
1995 {
1996 SERCOM_CRITICAL_SECTION_ENTER();
1997 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
1998 SERCOM_CRITICAL_SECTION_LEAVE();
1999 }
2000
hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void * const hw)2001 static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
2002 {
2003 SERCOM_CRITICAL_SECTION_ENTER();
2004 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
2005 SERCOM_CRITICAL_SECTION_LEAVE();
2006 }
2007
hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void * const hw)2008 static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
2009 {
2010 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
2011 }
2012
hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void * const hw,bool value)2013 static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
2014 {
2015 uint16_t tmp;
2016 SERCOM_CRITICAL_SECTION_ENTER();
2017 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
2018 tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
2019 tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
2020 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
2021 SERCOM_CRITICAL_SECTION_LEAVE();
2022 }
2023
hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void * const hw)2024 static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
2025 {
2026 SERCOM_CRITICAL_SECTION_ENTER();
2027 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
2028 SERCOM_CRITICAL_SECTION_LEAVE();
2029 }
2030
hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void * const hw)2031 static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
2032 {
2033 SERCOM_CRITICAL_SECTION_ENTER();
2034 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
2035 SERCOM_CRITICAL_SECTION_LEAVE();
2036 }
2037
hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void * const hw)2038 static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
2039 {
2040 SERCOM_CRITICAL_SECTION_ENTER();
2041 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
2042 SERCOM_CRITICAL_SECTION_LEAVE();
2043 }
2044
hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void * const hw)2045 static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
2046 {
2047 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
2048 }
2049
hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void * const hw,bool value)2050 static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
2051 {
2052 uint16_t tmp;
2053 SERCOM_CRITICAL_SECTION_ENTER();
2054 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
2055 tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
2056 tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
2057 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
2058 SERCOM_CRITICAL_SECTION_LEAVE();
2059 }
2060
hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void * const hw)2061 static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
2062 {
2063 SERCOM_CRITICAL_SECTION_ENTER();
2064 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
2065 SERCOM_CRITICAL_SECTION_LEAVE();
2066 }
2067
hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void * const hw)2068 static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
2069 {
2070 SERCOM_CRITICAL_SECTION_ENTER();
2071 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
2072 SERCOM_CRITICAL_SECTION_LEAVE();
2073 }
2074
hri_sercomi2cm_set_STATUS_LENERR_bit(const void * const hw)2075 static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
2076 {
2077 SERCOM_CRITICAL_SECTION_ENTER();
2078 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
2079 SERCOM_CRITICAL_SECTION_LEAVE();
2080 }
2081
hri_sercomi2cm_get_STATUS_LENERR_bit(const void * const hw)2082 static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
2083 {
2084 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
2085 }
2086
hri_sercomi2cm_write_STATUS_LENERR_bit(const void * const hw,bool value)2087 static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
2088 {
2089 uint16_t tmp;
2090 SERCOM_CRITICAL_SECTION_ENTER();
2091 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
2092 tmp &= ~SERCOM_I2CM_STATUS_LENERR;
2093 tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
2094 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
2095 SERCOM_CRITICAL_SECTION_LEAVE();
2096 }
2097
hri_sercomi2cm_clear_STATUS_LENERR_bit(const void * const hw)2098 static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
2099 {
2100 SERCOM_CRITICAL_SECTION_ENTER();
2101 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
2102 SERCOM_CRITICAL_SECTION_LEAVE();
2103 }
2104
hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void * const hw)2105 static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
2106 {
2107 SERCOM_CRITICAL_SECTION_ENTER();
2108 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
2109 SERCOM_CRITICAL_SECTION_LEAVE();
2110 }
2111
hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void * const hw,hri_sercomi2cm_status_reg_t mask)2112 static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw,
2113 hri_sercomi2cm_status_reg_t mask)
2114 {
2115 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2116 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
2117 }
2118
hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void * const hw,hri_sercomi2cm_status_reg_t mask)2119 static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2120 {
2121 SERCOM_CRITICAL_SECTION_ENTER();
2122 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2123 ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
2124 SERCOM_CRITICAL_SECTION_LEAVE();
2125 }
2126
hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void * const hw)2127 static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
2128 {
2129 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2130 return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
2131 }
2132
hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void * const hw,hri_sercomi2cm_status_reg_t data)2133 static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
2134 {
2135 uint16_t tmp;
2136 SERCOM_CRITICAL_SECTION_ENTER();
2137 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2138 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
2139 tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
2140 tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
2141 ((Sercom *)hw)->I2CM.STATUS.reg = tmp;
2142 SERCOM_CRITICAL_SECTION_LEAVE();
2143 }
2144
hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void * const hw,hri_sercomi2cm_status_reg_t mask)2145 static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2146 {
2147 SERCOM_CRITICAL_SECTION_ENTER();
2148 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2149 ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
2150 SERCOM_CRITICAL_SECTION_LEAVE();
2151 }
2152
hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void * const hw,hri_sercomi2cm_status_reg_t mask)2153 static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2154 {
2155 SERCOM_CRITICAL_SECTION_ENTER();
2156 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2157 ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
2158 SERCOM_CRITICAL_SECTION_LEAVE();
2159 }
2160
hri_sercomi2cm_get_STATUS_reg(const void * const hw,hri_sercomi2cm_status_reg_t mask)2161 static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw,
2162 hri_sercomi2cm_status_reg_t mask)
2163 {
2164 uint16_t tmp;
2165 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2166 tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
2167 tmp &= mask;
2168 return tmp;
2169 }
2170
hri_sercomi2cm_set_STATUS_reg(const void * const hw,hri_sercomi2cm_status_reg_t mask)2171 static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2172 {
2173 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2174 ((Sercom *)hw)->I2CM.STATUS.reg |= mask;
2175 }
2176
hri_sercomi2cm_read_STATUS_reg(const void * const hw)2177 static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
2178 {
2179 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2180 return ((Sercom *)hw)->I2CM.STATUS.reg;
2181 }
2182
hri_sercomi2cm_write_STATUS_reg(const void * const hw,hri_sercomi2cm_status_reg_t data)2183 static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
2184 {
2185 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2186 ((Sercom *)hw)->I2CM.STATUS.reg = data;
2187 }
2188
hri_sercomi2cm_toggle_STATUS_reg(const void * const hw,hri_sercomi2cm_status_reg_t mask)2189 static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2190 {
2191 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2192 ((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
2193 }
2194
hri_sercomi2cm_clear_STATUS_reg(const void * const hw,hri_sercomi2cm_status_reg_t mask)2195 static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
2196 {
2197 SERCOM_CRITICAL_SECTION_ENTER();
2198 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2199 ((Sercom *)hw)->I2CM.STATUS.reg = mask;
2200 SERCOM_CRITICAL_SECTION_LEAVE();
2201 }
2202
hri_sercomi2cm_set_CTRLA_SWRST_bit(const void * const hw)2203 static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
2204 {
2205 SERCOM_CRITICAL_SECTION_ENTER();
2206 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
2207 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
2208 SERCOM_CRITICAL_SECTION_LEAVE();
2209 }
2210
hri_sercomi2cm_get_CTRLA_SWRST_bit(const void * const hw)2211 static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
2212 {
2213 uint32_t tmp;
2214 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
2215 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2216 tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
2217 return (bool)tmp;
2218 }
2219
hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void * const hw)2220 static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
2221 {
2222 SERCOM_CRITICAL_SECTION_ENTER();
2223 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
2224 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
2225 SERCOM_CRITICAL_SECTION_LEAVE();
2226 }
2227
hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void * const hw)2228 static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
2229 {
2230 uint32_t tmp;
2231 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
2232 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2233 tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
2234 return (bool)tmp;
2235 }
2236
hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void * const hw,bool value)2237 static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
2238 {
2239 uint32_t tmp;
2240 SERCOM_CRITICAL_SECTION_ENTER();
2241 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
2242 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2243 tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
2244 tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
2245 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2246 SERCOM_CRITICAL_SECTION_LEAVE();
2247 }
2248
hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void * const hw)2249 static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
2250 {
2251 SERCOM_CRITICAL_SECTION_ENTER();
2252 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
2253 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
2254 SERCOM_CRITICAL_SECTION_LEAVE();
2255 }
2256
hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void * const hw)2257 static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
2258 {
2259 SERCOM_CRITICAL_SECTION_ENTER();
2260 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
2261 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
2262 SERCOM_CRITICAL_SECTION_LEAVE();
2263 }
2264
hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void * const hw)2265 static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
2266 {
2267 SERCOM_CRITICAL_SECTION_ENTER();
2268 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2269 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
2270 SERCOM_CRITICAL_SECTION_LEAVE();
2271 }
2272
hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void * const hw)2273 static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
2274 {
2275 uint32_t tmp;
2276 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2277 tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
2278 return (bool)tmp;
2279 }
2280
hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)2281 static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
2282 {
2283 uint32_t tmp;
2284 SERCOM_CRITICAL_SECTION_ENTER();
2285 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2286 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2287 tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
2288 tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
2289 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2290 SERCOM_CRITICAL_SECTION_LEAVE();
2291 }
2292
hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void * const hw)2293 static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
2294 {
2295 SERCOM_CRITICAL_SECTION_ENTER();
2296 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2297 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
2298 SERCOM_CRITICAL_SECTION_LEAVE();
2299 }
2300
hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)2301 static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
2302 {
2303 SERCOM_CRITICAL_SECTION_ENTER();
2304 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2305 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
2306 SERCOM_CRITICAL_SECTION_LEAVE();
2307 }
2308
hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void * const hw)2309 static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
2310 {
2311 SERCOM_CRITICAL_SECTION_ENTER();
2312 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2313 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
2314 SERCOM_CRITICAL_SECTION_LEAVE();
2315 }
2316
hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void * const hw)2317 static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
2318 {
2319 uint32_t tmp;
2320 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2321 tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
2322 return (bool)tmp;
2323 }
2324
hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void * const hw,bool value)2325 static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
2326 {
2327 uint32_t tmp;
2328 SERCOM_CRITICAL_SECTION_ENTER();
2329 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2330 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2331 tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
2332 tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
2333 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2334 SERCOM_CRITICAL_SECTION_LEAVE();
2335 }
2336
hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void * const hw)2337 static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
2338 {
2339 SERCOM_CRITICAL_SECTION_ENTER();
2340 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2341 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
2342 SERCOM_CRITICAL_SECTION_LEAVE();
2343 }
2344
hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void * const hw)2345 static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
2346 {
2347 SERCOM_CRITICAL_SECTION_ENTER();
2348 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2349 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
2350 SERCOM_CRITICAL_SECTION_LEAVE();
2351 }
2352
hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void * const hw)2353 static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
2354 {
2355 SERCOM_CRITICAL_SECTION_ENTER();
2356 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2357 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
2358 SERCOM_CRITICAL_SECTION_LEAVE();
2359 }
2360
hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void * const hw)2361 static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
2362 {
2363 uint32_t tmp;
2364 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2365 tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
2366 return (bool)tmp;
2367 }
2368
hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void * const hw,bool value)2369 static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
2370 {
2371 uint32_t tmp;
2372 SERCOM_CRITICAL_SECTION_ENTER();
2373 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2374 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2375 tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
2376 tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
2377 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2378 SERCOM_CRITICAL_SECTION_LEAVE();
2379 }
2380
hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void * const hw)2381 static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
2382 {
2383 SERCOM_CRITICAL_SECTION_ENTER();
2384 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2385 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
2386 SERCOM_CRITICAL_SECTION_LEAVE();
2387 }
2388
hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void * const hw)2389 static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
2390 {
2391 SERCOM_CRITICAL_SECTION_ENTER();
2392 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2393 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
2394 SERCOM_CRITICAL_SECTION_LEAVE();
2395 }
2396
hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void * const hw)2397 static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
2398 {
2399 SERCOM_CRITICAL_SECTION_ENTER();
2400 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2401 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
2402 SERCOM_CRITICAL_SECTION_LEAVE();
2403 }
2404
hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void * const hw)2405 static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
2406 {
2407 uint32_t tmp;
2408 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2409 tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
2410 return (bool)tmp;
2411 }
2412
hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void * const hw,bool value)2413 static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
2414 {
2415 uint32_t tmp;
2416 SERCOM_CRITICAL_SECTION_ENTER();
2417 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2418 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2419 tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
2420 tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
2421 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2422 SERCOM_CRITICAL_SECTION_LEAVE();
2423 }
2424
hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void * const hw)2425 static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
2426 {
2427 SERCOM_CRITICAL_SECTION_ENTER();
2428 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2429 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
2430 SERCOM_CRITICAL_SECTION_LEAVE();
2431 }
2432
hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void * const hw)2433 static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
2434 {
2435 SERCOM_CRITICAL_SECTION_ENTER();
2436 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2437 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
2438 SERCOM_CRITICAL_SECTION_LEAVE();
2439 }
2440
hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void * const hw)2441 static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
2442 {
2443 SERCOM_CRITICAL_SECTION_ENTER();
2444 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2445 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
2446 SERCOM_CRITICAL_SECTION_LEAVE();
2447 }
2448
hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void * const hw)2449 static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
2450 {
2451 uint32_t tmp;
2452 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2453 tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
2454 return (bool)tmp;
2455 }
2456
hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void * const hw,bool value)2457 static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
2458 {
2459 uint32_t tmp;
2460 SERCOM_CRITICAL_SECTION_ENTER();
2461 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2462 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2463 tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
2464 tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
2465 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2466 SERCOM_CRITICAL_SECTION_LEAVE();
2467 }
2468
hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void * const hw)2469 static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
2470 {
2471 SERCOM_CRITICAL_SECTION_ENTER();
2472 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2473 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
2474 SERCOM_CRITICAL_SECTION_LEAVE();
2475 }
2476
hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void * const hw)2477 static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
2478 {
2479 SERCOM_CRITICAL_SECTION_ENTER();
2480 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2481 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
2482 SERCOM_CRITICAL_SECTION_LEAVE();
2483 }
2484
hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void * const hw)2485 static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
2486 {
2487 SERCOM_CRITICAL_SECTION_ENTER();
2488 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2489 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
2490 SERCOM_CRITICAL_SECTION_LEAVE();
2491 }
2492
hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void * const hw)2493 static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
2494 {
2495 uint32_t tmp;
2496 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2497 tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
2498 return (bool)tmp;
2499 }
2500
hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void * const hw,bool value)2501 static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
2502 {
2503 uint32_t tmp;
2504 SERCOM_CRITICAL_SECTION_ENTER();
2505 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2506 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2507 tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
2508 tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
2509 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2510 SERCOM_CRITICAL_SECTION_LEAVE();
2511 }
2512
hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void * const hw)2513 static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
2514 {
2515 SERCOM_CRITICAL_SECTION_ENTER();
2516 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2517 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
2518 SERCOM_CRITICAL_SECTION_LEAVE();
2519 }
2520
hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void * const hw)2521 static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
2522 {
2523 SERCOM_CRITICAL_SECTION_ENTER();
2524 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2525 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
2526 SERCOM_CRITICAL_SECTION_LEAVE();
2527 }
2528
hri_sercomi2cm_set_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2529 static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2530 {
2531 SERCOM_CRITICAL_SECTION_ENTER();
2532 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2533 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
2534 SERCOM_CRITICAL_SECTION_LEAVE();
2535 }
2536
hri_sercomi2cm_get_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2537 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw,
2538 hri_sercomi2cm_ctrla_reg_t mask)
2539 {
2540 uint32_t tmp;
2541 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2542 tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
2543 return tmp;
2544 }
2545
hri_sercomi2cm_write_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t data)2546 static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
2547 {
2548 uint32_t tmp;
2549 SERCOM_CRITICAL_SECTION_ENTER();
2550 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2551 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2552 tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
2553 tmp |= SERCOM_I2CM_CTRLA_MODE(data);
2554 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2555 SERCOM_CRITICAL_SECTION_LEAVE();
2556 }
2557
hri_sercomi2cm_clear_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2558 static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2559 {
2560 SERCOM_CRITICAL_SECTION_ENTER();
2561 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2562 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
2563 SERCOM_CRITICAL_SECTION_LEAVE();
2564 }
2565
hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2566 static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2567 {
2568 SERCOM_CRITICAL_SECTION_ENTER();
2569 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2570 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
2571 SERCOM_CRITICAL_SECTION_LEAVE();
2572 }
2573
hri_sercomi2cm_read_CTRLA_MODE_bf(const void * const hw)2574 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
2575 {
2576 uint32_t tmp;
2577 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2578 tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
2579 return tmp;
2580 }
2581
hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2582 static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2583 {
2584 SERCOM_CRITICAL_SECTION_ENTER();
2585 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2586 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
2587 SERCOM_CRITICAL_SECTION_LEAVE();
2588 }
2589
hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2590 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw,
2591 hri_sercomi2cm_ctrla_reg_t mask)
2592 {
2593 uint32_t tmp;
2594 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2595 tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
2596 return tmp;
2597 }
2598
hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t data)2599 static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
2600 {
2601 uint32_t tmp;
2602 SERCOM_CRITICAL_SECTION_ENTER();
2603 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2604 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2605 tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
2606 tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
2607 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2608 SERCOM_CRITICAL_SECTION_LEAVE();
2609 }
2610
hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2611 static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2612 {
2613 SERCOM_CRITICAL_SECTION_ENTER();
2614 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2615 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
2616 SERCOM_CRITICAL_SECTION_LEAVE();
2617 }
2618
hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2619 static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2620 {
2621 SERCOM_CRITICAL_SECTION_ENTER();
2622 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2623 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
2624 SERCOM_CRITICAL_SECTION_LEAVE();
2625 }
2626
hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void * const hw)2627 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
2628 {
2629 uint32_t tmp;
2630 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2631 tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
2632 return tmp;
2633 }
2634
hri_sercomi2cm_set_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2635 static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2636 {
2637 SERCOM_CRITICAL_SECTION_ENTER();
2638 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2639 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
2640 SERCOM_CRITICAL_SECTION_LEAVE();
2641 }
2642
hri_sercomi2cm_get_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2643 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw,
2644 hri_sercomi2cm_ctrla_reg_t mask)
2645 {
2646 uint32_t tmp;
2647 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2648 tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
2649 return tmp;
2650 }
2651
hri_sercomi2cm_write_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t data)2652 static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
2653 {
2654 uint32_t tmp;
2655 SERCOM_CRITICAL_SECTION_ENTER();
2656 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2657 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2658 tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
2659 tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
2660 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2661 SERCOM_CRITICAL_SECTION_LEAVE();
2662 }
2663
hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2664 static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2665 {
2666 SERCOM_CRITICAL_SECTION_ENTER();
2667 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2668 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
2669 SERCOM_CRITICAL_SECTION_LEAVE();
2670 }
2671
hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2672 static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2673 {
2674 SERCOM_CRITICAL_SECTION_ENTER();
2675 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2676 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
2677 SERCOM_CRITICAL_SECTION_LEAVE();
2678 }
2679
hri_sercomi2cm_read_CTRLA_SPEED_bf(const void * const hw)2680 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
2681 {
2682 uint32_t tmp;
2683 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2684 tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
2685 return tmp;
2686 }
2687
hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2688 static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2689 {
2690 SERCOM_CRITICAL_SECTION_ENTER();
2691 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2692 ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
2693 SERCOM_CRITICAL_SECTION_LEAVE();
2694 }
2695
hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2696 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw,
2697 hri_sercomi2cm_ctrla_reg_t mask)
2698 {
2699 uint32_t tmp;
2700 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2701 tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
2702 return tmp;
2703 }
2704
hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t data)2705 static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
2706 {
2707 uint32_t tmp;
2708 SERCOM_CRITICAL_SECTION_ENTER();
2709 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2710 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2711 tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
2712 tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
2713 ((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
2714 SERCOM_CRITICAL_SECTION_LEAVE();
2715 }
2716
hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2717 static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2718 {
2719 SERCOM_CRITICAL_SECTION_ENTER();
2720 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2721 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
2722 SERCOM_CRITICAL_SECTION_LEAVE();
2723 }
2724
hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2725 static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2726 {
2727 SERCOM_CRITICAL_SECTION_ENTER();
2728 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
2729 ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
2730 SERCOM_CRITICAL_SECTION_LEAVE();
2731 }
2732
hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void * const hw)2733 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
2734 {
2735 uint32_t tmp;
2736 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2737 tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
2738 return tmp;
2739 }
2740
hri_sercomi2cm_set_CTRLA_reg(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2741 static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2742 {
2743 SERCOM_CRITICAL_SECTION_ENTER();
2744 ((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
2745 SERCOM_CRITICAL_SECTION_LEAVE();
2746 }
2747
hri_sercomi2cm_get_CTRLA_reg(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2748 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw,
2749 hri_sercomi2cm_ctrla_reg_t mask)
2750 {
2751 uint32_t tmp;
2752 tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
2753 tmp &= mask;
2754 return tmp;
2755 }
2756
hri_sercomi2cm_write_CTRLA_reg(const void * const hw,hri_sercomi2cm_ctrla_reg_t data)2757 static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
2758 {
2759 SERCOM_CRITICAL_SECTION_ENTER();
2760 ((Sercom *)hw)->I2CM.CTRLA.reg = data;
2761 SERCOM_CRITICAL_SECTION_LEAVE();
2762 }
2763
hri_sercomi2cm_clear_CTRLA_reg(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2764 static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2765 {
2766 SERCOM_CRITICAL_SECTION_ENTER();
2767 ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
2768 SERCOM_CRITICAL_SECTION_LEAVE();
2769 }
2770
hri_sercomi2cm_toggle_CTRLA_reg(const void * const hw,hri_sercomi2cm_ctrla_reg_t mask)2771 static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
2772 {
2773 SERCOM_CRITICAL_SECTION_ENTER();
2774 ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
2775 SERCOM_CRITICAL_SECTION_LEAVE();
2776 }
2777
hri_sercomi2cm_read_CTRLA_reg(const void * const hw)2778 static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
2779 {
2780 return ((Sercom *)hw)->I2CM.CTRLA.reg;
2781 }
2782
hri_sercomi2cm_set_CTRLB_SMEN_bit(const void * const hw)2783 static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
2784 {
2785 SERCOM_CRITICAL_SECTION_ENTER();
2786 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2787 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
2788 SERCOM_CRITICAL_SECTION_LEAVE();
2789 }
2790
hri_sercomi2cm_get_CTRLB_SMEN_bit(const void * const hw)2791 static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
2792 {
2793 uint32_t tmp;
2794 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2795 tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
2796 return (bool)tmp;
2797 }
2798
hri_sercomi2cm_write_CTRLB_SMEN_bit(const void * const hw,bool value)2799 static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
2800 {
2801 uint32_t tmp;
2802 SERCOM_CRITICAL_SECTION_ENTER();
2803 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2804 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2805 tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
2806 tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
2807 ((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
2808 SERCOM_CRITICAL_SECTION_LEAVE();
2809 }
2810
hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void * const hw)2811 static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
2812 {
2813 SERCOM_CRITICAL_SECTION_ENTER();
2814 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2815 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
2816 SERCOM_CRITICAL_SECTION_LEAVE();
2817 }
2818
hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void * const hw)2819 static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
2820 {
2821 SERCOM_CRITICAL_SECTION_ENTER();
2822 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2823 ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
2824 SERCOM_CRITICAL_SECTION_LEAVE();
2825 }
2826
hri_sercomi2cm_set_CTRLB_QCEN_bit(const void * const hw)2827 static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
2828 {
2829 SERCOM_CRITICAL_SECTION_ENTER();
2830 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2831 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
2832 SERCOM_CRITICAL_SECTION_LEAVE();
2833 }
2834
hri_sercomi2cm_get_CTRLB_QCEN_bit(const void * const hw)2835 static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
2836 {
2837 uint32_t tmp;
2838 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2839 tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
2840 return (bool)tmp;
2841 }
2842
hri_sercomi2cm_write_CTRLB_QCEN_bit(const void * const hw,bool value)2843 static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
2844 {
2845 uint32_t tmp;
2846 SERCOM_CRITICAL_SECTION_ENTER();
2847 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2848 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2849 tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
2850 tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
2851 ((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
2852 SERCOM_CRITICAL_SECTION_LEAVE();
2853 }
2854
hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void * const hw)2855 static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
2856 {
2857 SERCOM_CRITICAL_SECTION_ENTER();
2858 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2859 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
2860 SERCOM_CRITICAL_SECTION_LEAVE();
2861 }
2862
hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void * const hw)2863 static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
2864 {
2865 SERCOM_CRITICAL_SECTION_ENTER();
2866 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2867 ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
2868 SERCOM_CRITICAL_SECTION_LEAVE();
2869 }
2870
hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void * const hw)2871 static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
2872 {
2873 SERCOM_CRITICAL_SECTION_ENTER();
2874 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2875 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
2876 SERCOM_CRITICAL_SECTION_LEAVE();
2877 }
2878
hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void * const hw)2879 static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
2880 {
2881 uint32_t tmp;
2882 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2883 tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
2884 return (bool)tmp;
2885 }
2886
hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void * const hw,bool value)2887 static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
2888 {
2889 uint32_t tmp;
2890 SERCOM_CRITICAL_SECTION_ENTER();
2891 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2892 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2893 tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
2894 tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
2895 ((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
2896 SERCOM_CRITICAL_SECTION_LEAVE();
2897 }
2898
hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void * const hw)2899 static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
2900 {
2901 SERCOM_CRITICAL_SECTION_ENTER();
2902 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2903 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
2904 SERCOM_CRITICAL_SECTION_LEAVE();
2905 }
2906
hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void * const hw)2907 static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
2908 {
2909 SERCOM_CRITICAL_SECTION_ENTER();
2910 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2911 ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
2912 SERCOM_CRITICAL_SECTION_LEAVE();
2913 }
2914
hri_sercomi2cm_set_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2915 static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2916 {
2917 SERCOM_CRITICAL_SECTION_ENTER();
2918 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2919 ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
2920 SERCOM_CRITICAL_SECTION_LEAVE();
2921 }
2922
hri_sercomi2cm_get_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2923 static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw,
2924 hri_sercomi2cm_ctrlb_reg_t mask)
2925 {
2926 uint32_t tmp;
2927 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2928 tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
2929 return tmp;
2930 }
2931
hri_sercomi2cm_write_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cm_ctrlb_reg_t data)2932 static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
2933 {
2934 uint32_t tmp;
2935 SERCOM_CRITICAL_SECTION_ENTER();
2936 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2937 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2938 tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
2939 tmp |= SERCOM_I2CM_CTRLB_CMD(data);
2940 ((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
2941 SERCOM_CRITICAL_SECTION_LEAVE();
2942 }
2943
hri_sercomi2cm_clear_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2944 static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2945 {
2946 SERCOM_CRITICAL_SECTION_ENTER();
2947 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2948 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
2949 SERCOM_CRITICAL_SECTION_LEAVE();
2950 }
2951
hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2952 static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2953 {
2954 SERCOM_CRITICAL_SECTION_ENTER();
2955 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
2956 ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
2957 SERCOM_CRITICAL_SECTION_LEAVE();
2958 }
2959
hri_sercomi2cm_read_CTRLB_CMD_bf(const void * const hw)2960 static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
2961 {
2962 uint32_t tmp;
2963 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2964 tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
2965 return tmp;
2966 }
2967
hri_sercomi2cm_set_CTRLB_reg(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2968 static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2969 {
2970 SERCOM_CRITICAL_SECTION_ENTER();
2971 ((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
2972 SERCOM_CRITICAL_SECTION_LEAVE();
2973 }
2974
hri_sercomi2cm_get_CTRLB_reg(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2975 static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw,
2976 hri_sercomi2cm_ctrlb_reg_t mask)
2977 {
2978 uint32_t tmp;
2979 tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
2980 tmp &= mask;
2981 return tmp;
2982 }
2983
hri_sercomi2cm_write_CTRLB_reg(const void * const hw,hri_sercomi2cm_ctrlb_reg_t data)2984 static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
2985 {
2986 SERCOM_CRITICAL_SECTION_ENTER();
2987 ((Sercom *)hw)->I2CM.CTRLB.reg = data;
2988 SERCOM_CRITICAL_SECTION_LEAVE();
2989 }
2990
hri_sercomi2cm_clear_CTRLB_reg(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2991 static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2992 {
2993 SERCOM_CRITICAL_SECTION_ENTER();
2994 ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
2995 SERCOM_CRITICAL_SECTION_LEAVE();
2996 }
2997
hri_sercomi2cm_toggle_CTRLB_reg(const void * const hw,hri_sercomi2cm_ctrlb_reg_t mask)2998 static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
2999 {
3000 SERCOM_CRITICAL_SECTION_ENTER();
3001 ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
3002 SERCOM_CRITICAL_SECTION_LEAVE();
3003 }
3004
hri_sercomi2cm_read_CTRLB_reg(const void * const hw)3005 static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
3006 {
3007 return ((Sercom *)hw)->I2CM.CTRLB.reg;
3008 }
3009
hri_sercomi2cm_set_BAUD_BAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3010 static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3011 {
3012 SERCOM_CRITICAL_SECTION_ENTER();
3013 ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
3014 SERCOM_CRITICAL_SECTION_LEAVE();
3015 }
3016
hri_sercomi2cm_get_BAUD_BAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3017 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw,
3018 hri_sercomi2cm_baud_reg_t mask)
3019 {
3020 uint32_t tmp;
3021 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3022 tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
3023 return tmp;
3024 }
3025
hri_sercomi2cm_write_BAUD_BAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t data)3026 static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
3027 {
3028 uint32_t tmp;
3029 SERCOM_CRITICAL_SECTION_ENTER();
3030 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3031 tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
3032 tmp |= SERCOM_I2CM_BAUD_BAUD(data);
3033 ((Sercom *)hw)->I2CM.BAUD.reg = tmp;
3034 SERCOM_CRITICAL_SECTION_LEAVE();
3035 }
3036
hri_sercomi2cm_clear_BAUD_BAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3037 static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3038 {
3039 SERCOM_CRITICAL_SECTION_ENTER();
3040 ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
3041 SERCOM_CRITICAL_SECTION_LEAVE();
3042 }
3043
hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3044 static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3045 {
3046 SERCOM_CRITICAL_SECTION_ENTER();
3047 ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
3048 SERCOM_CRITICAL_SECTION_LEAVE();
3049 }
3050
hri_sercomi2cm_read_BAUD_BAUD_bf(const void * const hw)3051 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
3052 {
3053 uint32_t tmp;
3054 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3055 tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
3056 return tmp;
3057 }
3058
hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3059 static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3060 {
3061 SERCOM_CRITICAL_SECTION_ENTER();
3062 ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
3063 SERCOM_CRITICAL_SECTION_LEAVE();
3064 }
3065
hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3066 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw,
3067 hri_sercomi2cm_baud_reg_t mask)
3068 {
3069 uint32_t tmp;
3070 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3071 tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
3072 return tmp;
3073 }
3074
hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t data)3075 static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
3076 {
3077 uint32_t tmp;
3078 SERCOM_CRITICAL_SECTION_ENTER();
3079 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3080 tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
3081 tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
3082 ((Sercom *)hw)->I2CM.BAUD.reg = tmp;
3083 SERCOM_CRITICAL_SECTION_LEAVE();
3084 }
3085
hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3086 static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3087 {
3088 SERCOM_CRITICAL_SECTION_ENTER();
3089 ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
3090 SERCOM_CRITICAL_SECTION_LEAVE();
3091 }
3092
hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3093 static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3094 {
3095 SERCOM_CRITICAL_SECTION_ENTER();
3096 ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
3097 SERCOM_CRITICAL_SECTION_LEAVE();
3098 }
3099
hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void * const hw)3100 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
3101 {
3102 uint32_t tmp;
3103 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3104 tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
3105 return tmp;
3106 }
3107
hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3108 static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3109 {
3110 SERCOM_CRITICAL_SECTION_ENTER();
3111 ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
3112 SERCOM_CRITICAL_SECTION_LEAVE();
3113 }
3114
hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3115 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw,
3116 hri_sercomi2cm_baud_reg_t mask)
3117 {
3118 uint32_t tmp;
3119 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3120 tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
3121 return tmp;
3122 }
3123
hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t data)3124 static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
3125 {
3126 uint32_t tmp;
3127 SERCOM_CRITICAL_SECTION_ENTER();
3128 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3129 tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
3130 tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
3131 ((Sercom *)hw)->I2CM.BAUD.reg = tmp;
3132 SERCOM_CRITICAL_SECTION_LEAVE();
3133 }
3134
hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3135 static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3136 {
3137 SERCOM_CRITICAL_SECTION_ENTER();
3138 ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
3139 SERCOM_CRITICAL_SECTION_LEAVE();
3140 }
3141
hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3142 static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3143 {
3144 SERCOM_CRITICAL_SECTION_ENTER();
3145 ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
3146 SERCOM_CRITICAL_SECTION_LEAVE();
3147 }
3148
hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void * const hw)3149 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
3150 {
3151 uint32_t tmp;
3152 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3153 tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
3154 return tmp;
3155 }
3156
hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3157 static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3158 {
3159 SERCOM_CRITICAL_SECTION_ENTER();
3160 ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
3161 SERCOM_CRITICAL_SECTION_LEAVE();
3162 }
3163
hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3164 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw,
3165 hri_sercomi2cm_baud_reg_t mask)
3166 {
3167 uint32_t tmp;
3168 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3169 tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
3170 return tmp;
3171 }
3172
hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t data)3173 static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
3174 {
3175 uint32_t tmp;
3176 SERCOM_CRITICAL_SECTION_ENTER();
3177 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3178 tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
3179 tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
3180 ((Sercom *)hw)->I2CM.BAUD.reg = tmp;
3181 SERCOM_CRITICAL_SECTION_LEAVE();
3182 }
3183
hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3184 static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3185 {
3186 SERCOM_CRITICAL_SECTION_ENTER();
3187 ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
3188 SERCOM_CRITICAL_SECTION_LEAVE();
3189 }
3190
hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3191 static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3192 {
3193 SERCOM_CRITICAL_SECTION_ENTER();
3194 ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
3195 SERCOM_CRITICAL_SECTION_LEAVE();
3196 }
3197
hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void * const hw)3198 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
3199 {
3200 uint32_t tmp;
3201 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3202 tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
3203 return tmp;
3204 }
3205
hri_sercomi2cm_set_BAUD_reg(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3206 static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3207 {
3208 SERCOM_CRITICAL_SECTION_ENTER();
3209 ((Sercom *)hw)->I2CM.BAUD.reg |= mask;
3210 SERCOM_CRITICAL_SECTION_LEAVE();
3211 }
3212
hri_sercomi2cm_get_BAUD_reg(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3213 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw,
3214 hri_sercomi2cm_baud_reg_t mask)
3215 {
3216 uint32_t tmp;
3217 tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
3218 tmp &= mask;
3219 return tmp;
3220 }
3221
hri_sercomi2cm_write_BAUD_reg(const void * const hw,hri_sercomi2cm_baud_reg_t data)3222 static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
3223 {
3224 SERCOM_CRITICAL_SECTION_ENTER();
3225 ((Sercom *)hw)->I2CM.BAUD.reg = data;
3226 SERCOM_CRITICAL_SECTION_LEAVE();
3227 }
3228
hri_sercomi2cm_clear_BAUD_reg(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3229 static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3230 {
3231 SERCOM_CRITICAL_SECTION_ENTER();
3232 ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
3233 SERCOM_CRITICAL_SECTION_LEAVE();
3234 }
3235
hri_sercomi2cm_toggle_BAUD_reg(const void * const hw,hri_sercomi2cm_baud_reg_t mask)3236 static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
3237 {
3238 SERCOM_CRITICAL_SECTION_ENTER();
3239 ((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
3240 SERCOM_CRITICAL_SECTION_LEAVE();
3241 }
3242
hri_sercomi2cm_read_BAUD_reg(const void * const hw)3243 static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
3244 {
3245 return ((Sercom *)hw)->I2CM.BAUD.reg;
3246 }
3247
hri_sercomi2cm_set_ADDR_LENEN_bit(const void * const hw)3248 static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
3249 {
3250 SERCOM_CRITICAL_SECTION_ENTER();
3251 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3252 ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
3253 SERCOM_CRITICAL_SECTION_LEAVE();
3254 }
3255
hri_sercomi2cm_get_ADDR_LENEN_bit(const void * const hw)3256 static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
3257 {
3258 uint32_t tmp;
3259 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3260 tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
3261 return (bool)tmp;
3262 }
3263
hri_sercomi2cm_write_ADDR_LENEN_bit(const void * const hw,bool value)3264 static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
3265 {
3266 uint32_t tmp;
3267 SERCOM_CRITICAL_SECTION_ENTER();
3268 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3269 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3270 tmp &= ~SERCOM_I2CM_ADDR_LENEN;
3271 tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
3272 ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
3273 SERCOM_CRITICAL_SECTION_LEAVE();
3274 }
3275
hri_sercomi2cm_clear_ADDR_LENEN_bit(const void * const hw)3276 static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
3277 {
3278 SERCOM_CRITICAL_SECTION_ENTER();
3279 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3280 ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
3281 SERCOM_CRITICAL_SECTION_LEAVE();
3282 }
3283
hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void * const hw)3284 static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
3285 {
3286 SERCOM_CRITICAL_SECTION_ENTER();
3287 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3288 ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
3289 SERCOM_CRITICAL_SECTION_LEAVE();
3290 }
3291
hri_sercomi2cm_set_ADDR_HS_bit(const void * const hw)3292 static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
3293 {
3294 SERCOM_CRITICAL_SECTION_ENTER();
3295 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3296 ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
3297 SERCOM_CRITICAL_SECTION_LEAVE();
3298 }
3299
hri_sercomi2cm_get_ADDR_HS_bit(const void * const hw)3300 static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
3301 {
3302 uint32_t tmp;
3303 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3304 tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
3305 return (bool)tmp;
3306 }
3307
hri_sercomi2cm_write_ADDR_HS_bit(const void * const hw,bool value)3308 static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
3309 {
3310 uint32_t tmp;
3311 SERCOM_CRITICAL_SECTION_ENTER();
3312 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3313 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3314 tmp &= ~SERCOM_I2CM_ADDR_HS;
3315 tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
3316 ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
3317 SERCOM_CRITICAL_SECTION_LEAVE();
3318 }
3319
hri_sercomi2cm_clear_ADDR_HS_bit(const void * const hw)3320 static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
3321 {
3322 SERCOM_CRITICAL_SECTION_ENTER();
3323 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3324 ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
3325 SERCOM_CRITICAL_SECTION_LEAVE();
3326 }
3327
hri_sercomi2cm_toggle_ADDR_HS_bit(const void * const hw)3328 static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
3329 {
3330 SERCOM_CRITICAL_SECTION_ENTER();
3331 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3332 ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
3333 SERCOM_CRITICAL_SECTION_LEAVE();
3334 }
3335
hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void * const hw)3336 static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
3337 {
3338 SERCOM_CRITICAL_SECTION_ENTER();
3339 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3340 ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
3341 SERCOM_CRITICAL_SECTION_LEAVE();
3342 }
3343
hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void * const hw)3344 static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
3345 {
3346 uint32_t tmp;
3347 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3348 tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
3349 return (bool)tmp;
3350 }
3351
hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void * const hw,bool value)3352 static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
3353 {
3354 uint32_t tmp;
3355 SERCOM_CRITICAL_SECTION_ENTER();
3356 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3357 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3358 tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
3359 tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
3360 ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
3361 SERCOM_CRITICAL_SECTION_LEAVE();
3362 }
3363
hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void * const hw)3364 static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
3365 {
3366 SERCOM_CRITICAL_SECTION_ENTER();
3367 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3368 ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
3369 SERCOM_CRITICAL_SECTION_LEAVE();
3370 }
3371
hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void * const hw)3372 static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
3373 {
3374 SERCOM_CRITICAL_SECTION_ENTER();
3375 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3376 ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
3377 SERCOM_CRITICAL_SECTION_LEAVE();
3378 }
3379
hri_sercomi2cm_set_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3380 static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3381 {
3382 SERCOM_CRITICAL_SECTION_ENTER();
3383 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3384 ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
3385 SERCOM_CRITICAL_SECTION_LEAVE();
3386 }
3387
hri_sercomi2cm_get_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3388 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw,
3389 hri_sercomi2cm_addr_reg_t mask)
3390 {
3391 uint32_t tmp;
3392 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3393 tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
3394 return tmp;
3395 }
3396
hri_sercomi2cm_write_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cm_addr_reg_t data)3397 static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
3398 {
3399 uint32_t tmp;
3400 SERCOM_CRITICAL_SECTION_ENTER();
3401 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3402 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3403 tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
3404 tmp |= SERCOM_I2CM_ADDR_ADDR(data);
3405 ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
3406 SERCOM_CRITICAL_SECTION_LEAVE();
3407 }
3408
hri_sercomi2cm_clear_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3409 static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3410 {
3411 SERCOM_CRITICAL_SECTION_ENTER();
3412 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3413 ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
3414 SERCOM_CRITICAL_SECTION_LEAVE();
3415 }
3416
hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3417 static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3418 {
3419 SERCOM_CRITICAL_SECTION_ENTER();
3420 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3421 ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
3422 SERCOM_CRITICAL_SECTION_LEAVE();
3423 }
3424
hri_sercomi2cm_read_ADDR_ADDR_bf(const void * const hw)3425 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
3426 {
3427 uint32_t tmp;
3428 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3429 tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
3430 return tmp;
3431 }
3432
hri_sercomi2cm_set_ADDR_LEN_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3433 static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3434 {
3435 SERCOM_CRITICAL_SECTION_ENTER();
3436 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3437 ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
3438 SERCOM_CRITICAL_SECTION_LEAVE();
3439 }
3440
hri_sercomi2cm_get_ADDR_LEN_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3441 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw,
3442 hri_sercomi2cm_addr_reg_t mask)
3443 {
3444 uint32_t tmp;
3445 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3446 tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
3447 return tmp;
3448 }
3449
hri_sercomi2cm_write_ADDR_LEN_bf(const void * const hw,hri_sercomi2cm_addr_reg_t data)3450 static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
3451 {
3452 uint32_t tmp;
3453 SERCOM_CRITICAL_SECTION_ENTER();
3454 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3455 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3456 tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
3457 tmp |= SERCOM_I2CM_ADDR_LEN(data);
3458 ((Sercom *)hw)->I2CM.ADDR.reg = tmp;
3459 SERCOM_CRITICAL_SECTION_LEAVE();
3460 }
3461
hri_sercomi2cm_clear_ADDR_LEN_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3462 static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3463 {
3464 SERCOM_CRITICAL_SECTION_ENTER();
3465 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3466 ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
3467 SERCOM_CRITICAL_SECTION_LEAVE();
3468 }
3469
hri_sercomi2cm_toggle_ADDR_LEN_bf(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3470 static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3471 {
3472 SERCOM_CRITICAL_SECTION_ENTER();
3473 hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
3474 ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
3475 SERCOM_CRITICAL_SECTION_LEAVE();
3476 }
3477
hri_sercomi2cm_read_ADDR_LEN_bf(const void * const hw)3478 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
3479 {
3480 uint32_t tmp;
3481 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3482 tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
3483 return tmp;
3484 }
3485
hri_sercomi2cm_set_ADDR_reg(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3486 static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3487 {
3488 SERCOM_CRITICAL_SECTION_ENTER();
3489 ((Sercom *)hw)->I2CM.ADDR.reg |= mask;
3490 SERCOM_CRITICAL_SECTION_LEAVE();
3491 }
3492
hri_sercomi2cm_get_ADDR_reg(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3493 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw,
3494 hri_sercomi2cm_addr_reg_t mask)
3495 {
3496 uint32_t tmp;
3497 tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
3498 tmp &= mask;
3499 return tmp;
3500 }
3501
hri_sercomi2cm_write_ADDR_reg(const void * const hw,hri_sercomi2cm_addr_reg_t data)3502 static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
3503 {
3504 SERCOM_CRITICAL_SECTION_ENTER();
3505 ((Sercom *)hw)->I2CM.ADDR.reg = data;
3506 SERCOM_CRITICAL_SECTION_LEAVE();
3507 }
3508
hri_sercomi2cm_clear_ADDR_reg(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3509 static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3510 {
3511 SERCOM_CRITICAL_SECTION_ENTER();
3512 ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
3513 SERCOM_CRITICAL_SECTION_LEAVE();
3514 }
3515
hri_sercomi2cm_toggle_ADDR_reg(const void * const hw,hri_sercomi2cm_addr_reg_t mask)3516 static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
3517 {
3518 SERCOM_CRITICAL_SECTION_ENTER();
3519 ((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
3520 SERCOM_CRITICAL_SECTION_LEAVE();
3521 }
3522
hri_sercomi2cm_read_ADDR_reg(const void * const hw)3523 static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
3524 {
3525 return ((Sercom *)hw)->I2CM.ADDR.reg;
3526 }
3527
hri_sercomi2cm_read_DATA_reg(const void * const hw)3528 static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
3529 {
3530 return ((Sercom *)hw)->I2CM.DATA.reg;
3531 }
3532
hri_sercomi2cm_write_DATA_reg(const void * const hw,hri_sercomi2cm_data_reg_t data)3533 static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
3534 {
3535 SERCOM_CRITICAL_SECTION_ENTER();
3536 ((Sercom *)hw)->I2CM.DATA.reg = data;
3537 SERCOM_CRITICAL_SECTION_LEAVE();
3538 }
3539
hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void * const hw)3540 static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
3541 {
3542 SERCOM_CRITICAL_SECTION_ENTER();
3543 ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
3544 SERCOM_CRITICAL_SECTION_LEAVE();
3545 }
3546
hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void * const hw)3547 static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
3548 {
3549 uint8_t tmp;
3550 tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
3551 tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
3552 return (bool)tmp;
3553 }
3554
hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void * const hw,bool value)3555 static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
3556 {
3557 uint8_t tmp;
3558 SERCOM_CRITICAL_SECTION_ENTER();
3559 tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
3560 tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
3561 tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
3562 ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
3563 SERCOM_CRITICAL_SECTION_LEAVE();
3564 }
3565
hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void * const hw)3566 static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
3567 {
3568 SERCOM_CRITICAL_SECTION_ENTER();
3569 ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
3570 SERCOM_CRITICAL_SECTION_LEAVE();
3571 }
3572
hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void * const hw)3573 static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
3574 {
3575 SERCOM_CRITICAL_SECTION_ENTER();
3576 ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
3577 SERCOM_CRITICAL_SECTION_LEAVE();
3578 }
3579
hri_sercomi2cm_set_DBGCTRL_reg(const void * const hw,hri_sercomi2cm_dbgctrl_reg_t mask)3580 static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
3581 {
3582 SERCOM_CRITICAL_SECTION_ENTER();
3583 ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
3584 SERCOM_CRITICAL_SECTION_LEAVE();
3585 }
3586
hri_sercomi2cm_get_DBGCTRL_reg(const void * const hw,hri_sercomi2cm_dbgctrl_reg_t mask)3587 static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw,
3588 hri_sercomi2cm_dbgctrl_reg_t mask)
3589 {
3590 uint8_t tmp;
3591 tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
3592 tmp &= mask;
3593 return tmp;
3594 }
3595
hri_sercomi2cm_write_DBGCTRL_reg(const void * const hw,hri_sercomi2cm_dbgctrl_reg_t data)3596 static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
3597 {
3598 SERCOM_CRITICAL_SECTION_ENTER();
3599 ((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
3600 SERCOM_CRITICAL_SECTION_LEAVE();
3601 }
3602
hri_sercomi2cm_clear_DBGCTRL_reg(const void * const hw,hri_sercomi2cm_dbgctrl_reg_t mask)3603 static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
3604 {
3605 SERCOM_CRITICAL_SECTION_ENTER();
3606 ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
3607 SERCOM_CRITICAL_SECTION_LEAVE();
3608 }
3609
hri_sercomi2cm_toggle_DBGCTRL_reg(const void * const hw,hri_sercomi2cm_dbgctrl_reg_t mask)3610 static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
3611 {
3612 SERCOM_CRITICAL_SECTION_ENTER();
3613 ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
3614 SERCOM_CRITICAL_SECTION_LEAVE();
3615 }
3616
hri_sercomi2cm_read_DBGCTRL_reg(const void * const hw)3617 static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
3618 {
3619 return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
3620 }
3621
hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void * const hw)3622 static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
3623 {
3624 return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
3625 }
3626
hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void * const hw)3627 static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
3628 {
3629 return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
3630 }
3631
hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void * const hw)3632 static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
3633 {
3634 return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
3635 }
3636
hri_sercomi2cm_get_SYNCBUSY_reg(const void * const hw,hri_sercomi2cm_syncbusy_reg_t mask)3637 static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw,
3638 hri_sercomi2cm_syncbusy_reg_t mask)
3639 {
3640 uint32_t tmp;
3641 tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
3642 tmp &= mask;
3643 return tmp;
3644 }
3645
hri_sercomi2cm_read_SYNCBUSY_reg(const void * const hw)3646 static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
3647 {
3648 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
3649 }
3650
hri_sercomusart_set_BAUD_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3651 static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3652 {
3653 SERCOM_CRITICAL_SECTION_ENTER();
3654 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
3655 SERCOM_CRITICAL_SECTION_LEAVE();
3656 }
3657
hri_sercomusart_get_BAUD_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3658 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw,
3659 hri_sercomusart_baud_reg_t mask)
3660 {
3661 uint16_t tmp;
3662 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3663 tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
3664 return tmp;
3665 }
3666
hri_sercomusart_write_BAUD_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3667 static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3668 {
3669 uint16_t tmp;
3670 SERCOM_CRITICAL_SECTION_ENTER();
3671 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3672 tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
3673 tmp |= SERCOM_USART_BAUD_BAUD(data);
3674 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3675 SERCOM_CRITICAL_SECTION_LEAVE();
3676 }
3677
hri_sercomusart_clear_BAUD_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3678 static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3679 {
3680 SERCOM_CRITICAL_SECTION_ENTER();
3681 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
3682 SERCOM_CRITICAL_SECTION_LEAVE();
3683 }
3684
hri_sercomusart_toggle_BAUD_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3685 static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3686 {
3687 SERCOM_CRITICAL_SECTION_ENTER();
3688 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
3689 SERCOM_CRITICAL_SECTION_LEAVE();
3690 }
3691
hri_sercomusart_read_BAUD_BAUD_bf(const void * const hw)3692 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
3693 {
3694 uint16_t tmp;
3695 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3696 tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
3697 return tmp;
3698 }
3699
hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3700 static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3701 {
3702 SERCOM_CRITICAL_SECTION_ENTER();
3703 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask);
3704 SERCOM_CRITICAL_SECTION_LEAVE();
3705 }
3706
hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3707 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw,
3708 hri_sercomusart_baud_reg_t mask)
3709 {
3710 uint16_t tmp;
3711 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3712 tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos;
3713 return tmp;
3714 }
3715
hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3716 static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3717 {
3718 uint16_t tmp;
3719 SERCOM_CRITICAL_SECTION_ENTER();
3720 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3721 tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk;
3722 tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data);
3723 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3724 SERCOM_CRITICAL_SECTION_LEAVE();
3725 }
3726
hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3727 static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3728 {
3729 SERCOM_CRITICAL_SECTION_ENTER();
3730 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask);
3731 SERCOM_CRITICAL_SECTION_LEAVE();
3732 }
3733
hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3734 static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3735 {
3736 SERCOM_CRITICAL_SECTION_ENTER();
3737 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask);
3738 SERCOM_CRITICAL_SECTION_LEAVE();
3739 }
3740
hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void * const hw)3741 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
3742 {
3743 uint16_t tmp;
3744 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3745 tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos;
3746 return tmp;
3747 }
3748
hri_sercomusart_set_BAUD_FRAC_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3749 static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3750 {
3751 SERCOM_CRITICAL_SECTION_ENTER();
3752 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
3753 SERCOM_CRITICAL_SECTION_LEAVE();
3754 }
3755
hri_sercomusart_get_BAUD_FRAC_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3756 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw,
3757 hri_sercomusart_baud_reg_t mask)
3758 {
3759 uint16_t tmp;
3760 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3761 tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
3762 return tmp;
3763 }
3764
hri_sercomusart_write_BAUD_FRAC_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3765 static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3766 {
3767 uint16_t tmp;
3768 SERCOM_CRITICAL_SECTION_ENTER();
3769 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3770 tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
3771 tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
3772 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3773 SERCOM_CRITICAL_SECTION_LEAVE();
3774 }
3775
hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3776 static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3777 {
3778 SERCOM_CRITICAL_SECTION_ENTER();
3779 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
3780 SERCOM_CRITICAL_SECTION_LEAVE();
3781 }
3782
hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3783 static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3784 {
3785 SERCOM_CRITICAL_SECTION_ENTER();
3786 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
3787 SERCOM_CRITICAL_SECTION_LEAVE();
3788 }
3789
hri_sercomusart_read_BAUD_FRAC_FP_bf(const void * const hw)3790 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
3791 {
3792 uint16_t tmp;
3793 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3794 tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
3795 return tmp;
3796 }
3797
hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3798 static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3799 {
3800 SERCOM_CRITICAL_SECTION_ENTER();
3801 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask);
3802 SERCOM_CRITICAL_SECTION_LEAVE();
3803 }
3804
hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3805 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw,
3806 hri_sercomusart_baud_reg_t mask)
3807 {
3808 uint16_t tmp;
3809 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3810 tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos;
3811 return tmp;
3812 }
3813
hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3814 static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3815 {
3816 uint16_t tmp;
3817 SERCOM_CRITICAL_SECTION_ENTER();
3818 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3819 tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk;
3820 tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data);
3821 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3822 SERCOM_CRITICAL_SECTION_LEAVE();
3823 }
3824
hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3825 static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3826 {
3827 SERCOM_CRITICAL_SECTION_ENTER();
3828 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask);
3829 SERCOM_CRITICAL_SECTION_LEAVE();
3830 }
3831
hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3832 static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3833 {
3834 SERCOM_CRITICAL_SECTION_ENTER();
3835 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask);
3836 SERCOM_CRITICAL_SECTION_LEAVE();
3837 }
3838
hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void * const hw)3839 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
3840 {
3841 uint16_t tmp;
3842 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3843 tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos;
3844 return tmp;
3845 }
3846
hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3847 static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3848 {
3849 SERCOM_CRITICAL_SECTION_ENTER();
3850 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
3851 SERCOM_CRITICAL_SECTION_LEAVE();
3852 }
3853
hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3854 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw,
3855 hri_sercomusart_baud_reg_t mask)
3856 {
3857 uint16_t tmp;
3858 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3859 tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
3860 return tmp;
3861 }
3862
hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3863 static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3864 {
3865 uint16_t tmp;
3866 SERCOM_CRITICAL_SECTION_ENTER();
3867 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3868 tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
3869 tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
3870 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3871 SERCOM_CRITICAL_SECTION_LEAVE();
3872 }
3873
hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3874 static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3875 {
3876 SERCOM_CRITICAL_SECTION_ENTER();
3877 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
3878 SERCOM_CRITICAL_SECTION_LEAVE();
3879 }
3880
hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3881 static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3882 {
3883 SERCOM_CRITICAL_SECTION_ENTER();
3884 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
3885 SERCOM_CRITICAL_SECTION_LEAVE();
3886 }
3887
hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void * const hw)3888 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
3889 {
3890 uint16_t tmp;
3891 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3892 tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
3893 return tmp;
3894 }
3895
hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3896 static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3897 {
3898 SERCOM_CRITICAL_SECTION_ENTER();
3899 ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask);
3900 SERCOM_CRITICAL_SECTION_LEAVE();
3901 }
3902
hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3903 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw,
3904 hri_sercomusart_baud_reg_t mask)
3905 {
3906 uint16_t tmp;
3907 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3908 tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos;
3909 return tmp;
3910 }
3911
hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t data)3912 static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
3913 {
3914 uint16_t tmp;
3915 SERCOM_CRITICAL_SECTION_ENTER();
3916 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3917 tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk;
3918 tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data);
3919 ((Sercom *)hw)->USART.BAUD.reg = tmp;
3920 SERCOM_CRITICAL_SECTION_LEAVE();
3921 }
3922
hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3923 static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3924 {
3925 SERCOM_CRITICAL_SECTION_ENTER();
3926 ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask);
3927 SERCOM_CRITICAL_SECTION_LEAVE();
3928 }
3929
hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void * const hw,hri_sercomusart_baud_reg_t mask)3930 static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
3931 {
3932 SERCOM_CRITICAL_SECTION_ENTER();
3933 ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask);
3934 SERCOM_CRITICAL_SECTION_LEAVE();
3935 }
3936
hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void * const hw)3937 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
3938 {
3939 uint16_t tmp;
3940 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3941 tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos;
3942 return tmp;
3943 }
3944
hri_sercomusart_set_BAUD_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3945 static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
3946 {
3947 SERCOM_CRITICAL_SECTION_ENTER();
3948 ((Sercom *)hw)->USART.BAUD.reg |= mask;
3949 SERCOM_CRITICAL_SECTION_LEAVE();
3950 }
3951
hri_sercomusart_get_BAUD_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3952 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw,
3953 hri_sercomusart_baud_reg_t mask)
3954 {
3955 uint16_t tmp;
3956 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3957 tmp &= mask;
3958 return tmp;
3959 }
3960
hri_sercomusart_write_BAUD_reg(const void * const hw,hri_sercomusart_baud_reg_t data)3961 static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
3962 {
3963 SERCOM_CRITICAL_SECTION_ENTER();
3964 ((Sercom *)hw)->USART.BAUD.reg = data;
3965 SERCOM_CRITICAL_SECTION_LEAVE();
3966 }
3967
hri_sercomusart_clear_BAUD_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3968 static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
3969 {
3970 SERCOM_CRITICAL_SECTION_ENTER();
3971 ((Sercom *)hw)->USART.BAUD.reg &= ~mask;
3972 SERCOM_CRITICAL_SECTION_LEAVE();
3973 }
3974
hri_sercomusart_toggle_BAUD_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3975 static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
3976 {
3977 SERCOM_CRITICAL_SECTION_ENTER();
3978 ((Sercom *)hw)->USART.BAUD.reg ^= mask;
3979 SERCOM_CRITICAL_SECTION_LEAVE();
3980 }
3981
hri_sercomusart_read_BAUD_reg(const void * const hw)3982 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
3983 {
3984 return ((Sercom *)hw)->USART.BAUD.reg;
3985 }
3986
hri_sercomusart_set_BAUD_FRAC_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3987 static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
3988 {
3989 SERCOM_CRITICAL_SECTION_ENTER();
3990 ((Sercom *)hw)->USART.BAUD.reg |= mask;
3991 SERCOM_CRITICAL_SECTION_LEAVE();
3992 }
3993
hri_sercomusart_get_BAUD_FRAC_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)3994 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const hw,
3995 hri_sercomusart_baud_reg_t mask)
3996 {
3997 uint16_t tmp;
3998 tmp = ((Sercom *)hw)->USART.BAUD.reg;
3999 tmp &= mask;
4000 return tmp;
4001 }
4002
hri_sercomusart_write_BAUD_FRAC_reg(const void * const hw,hri_sercomusart_baud_reg_t data)4003 static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
4004 {
4005 SERCOM_CRITICAL_SECTION_ENTER();
4006 ((Sercom *)hw)->USART.BAUD.reg = data;
4007 SERCOM_CRITICAL_SECTION_LEAVE();
4008 }
4009
hri_sercomusart_clear_BAUD_FRAC_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4010 static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4011 {
4012 SERCOM_CRITICAL_SECTION_ENTER();
4013 ((Sercom *)hw)->USART.BAUD.reg &= ~mask;
4014 SERCOM_CRITICAL_SECTION_LEAVE();
4015 }
4016
hri_sercomusart_toggle_BAUD_FRAC_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4017 static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4018 {
4019 SERCOM_CRITICAL_SECTION_ENTER();
4020 ((Sercom *)hw)->USART.BAUD.reg ^= mask;
4021 SERCOM_CRITICAL_SECTION_LEAVE();
4022 }
4023
hri_sercomusart_read_BAUD_FRAC_reg(const void * const hw)4024 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw)
4025 {
4026 return ((Sercom *)hw)->USART.BAUD.reg;
4027 }
4028
hri_sercomusart_set_BAUD_FRACFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4029 static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4030 {
4031 SERCOM_CRITICAL_SECTION_ENTER();
4032 ((Sercom *)hw)->USART.BAUD.reg |= mask;
4033 SERCOM_CRITICAL_SECTION_LEAVE();
4034 }
4035
hri_sercomusart_get_BAUD_FRACFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4036 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const hw,
4037 hri_sercomusart_baud_reg_t mask)
4038 {
4039 uint16_t tmp;
4040 tmp = ((Sercom *)hw)->USART.BAUD.reg;
4041 tmp &= mask;
4042 return tmp;
4043 }
4044
hri_sercomusart_write_BAUD_FRACFP_reg(const void * const hw,hri_sercomusart_baud_reg_t data)4045 static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
4046 {
4047 SERCOM_CRITICAL_SECTION_ENTER();
4048 ((Sercom *)hw)->USART.BAUD.reg = data;
4049 SERCOM_CRITICAL_SECTION_LEAVE();
4050 }
4051
hri_sercomusart_clear_BAUD_FRACFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4052 static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4053 {
4054 SERCOM_CRITICAL_SECTION_ENTER();
4055 ((Sercom *)hw)->USART.BAUD.reg &= ~mask;
4056 SERCOM_CRITICAL_SECTION_LEAVE();
4057 }
4058
hri_sercomusart_toggle_BAUD_FRACFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4059 static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4060 {
4061 SERCOM_CRITICAL_SECTION_ENTER();
4062 ((Sercom *)hw)->USART.BAUD.reg ^= mask;
4063 SERCOM_CRITICAL_SECTION_LEAVE();
4064 }
4065
hri_sercomusart_read_BAUD_FRACFP_reg(const void * const hw)4066 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw)
4067 {
4068 return ((Sercom *)hw)->USART.BAUD.reg;
4069 }
4070
hri_sercomusart_set_BAUD_USARTFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4071 static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4072 {
4073 SERCOM_CRITICAL_SECTION_ENTER();
4074 ((Sercom *)hw)->USART.BAUD.reg |= mask;
4075 SERCOM_CRITICAL_SECTION_LEAVE();
4076 }
4077
hri_sercomusart_get_BAUD_USARTFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4078 static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const hw,
4079 hri_sercomusart_baud_reg_t mask)
4080 {
4081 uint16_t tmp;
4082 tmp = ((Sercom *)hw)->USART.BAUD.reg;
4083 tmp &= mask;
4084 return tmp;
4085 }
4086
hri_sercomusart_write_BAUD_USARTFP_reg(const void * const hw,hri_sercomusart_baud_reg_t data)4087 static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
4088 {
4089 SERCOM_CRITICAL_SECTION_ENTER();
4090 ((Sercom *)hw)->USART.BAUD.reg = data;
4091 SERCOM_CRITICAL_SECTION_LEAVE();
4092 }
4093
hri_sercomusart_clear_BAUD_USARTFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4094 static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4095 {
4096 SERCOM_CRITICAL_SECTION_ENTER();
4097 ((Sercom *)hw)->USART.BAUD.reg &= ~mask;
4098 SERCOM_CRITICAL_SECTION_LEAVE();
4099 }
4100
hri_sercomusart_toggle_BAUD_USARTFP_reg(const void * const hw,hri_sercomusart_baud_reg_t mask)4101 static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
4102 {
4103 SERCOM_CRITICAL_SECTION_ENTER();
4104 ((Sercom *)hw)->USART.BAUD.reg ^= mask;
4105 SERCOM_CRITICAL_SECTION_LEAVE();
4106 }
4107
hri_sercomusart_read_BAUD_USARTFP_reg(const void * const hw)4108 static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw)
4109 {
4110 return ((Sercom *)hw)->USART.BAUD.reg;
4111 }
4112
hri_sercomusart_set_INTEN_DRE_bit(const void * const hw)4113 static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
4114 {
4115 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
4116 }
4117
hri_sercomusart_get_INTEN_DRE_bit(const void * const hw)4118 static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
4119 {
4120 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
4121 }
4122
hri_sercomusart_write_INTEN_DRE_bit(const void * const hw,bool value)4123 static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
4124 {
4125 if (value == 0x0) {
4126 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
4127 } else {
4128 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
4129 }
4130 }
4131
hri_sercomusart_clear_INTEN_DRE_bit(const void * const hw)4132 static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
4133 {
4134 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
4135 }
4136
hri_sercomusart_set_INTEN_TXC_bit(const void * const hw)4137 static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
4138 {
4139 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
4140 }
4141
hri_sercomusart_get_INTEN_TXC_bit(const void * const hw)4142 static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
4143 {
4144 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
4145 }
4146
hri_sercomusart_write_INTEN_TXC_bit(const void * const hw,bool value)4147 static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
4148 {
4149 if (value == 0x0) {
4150 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
4151 } else {
4152 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
4153 }
4154 }
4155
hri_sercomusart_clear_INTEN_TXC_bit(const void * const hw)4156 static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
4157 {
4158 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
4159 }
4160
hri_sercomusart_set_INTEN_RXC_bit(const void * const hw)4161 static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
4162 {
4163 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
4164 }
4165
hri_sercomusart_get_INTEN_RXC_bit(const void * const hw)4166 static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
4167 {
4168 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
4169 }
4170
hri_sercomusart_write_INTEN_RXC_bit(const void * const hw,bool value)4171 static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
4172 {
4173 if (value == 0x0) {
4174 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
4175 } else {
4176 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
4177 }
4178 }
4179
hri_sercomusart_clear_INTEN_RXC_bit(const void * const hw)4180 static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
4181 {
4182 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
4183 }
4184
hri_sercomusart_set_INTEN_RXS_bit(const void * const hw)4185 static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
4186 {
4187 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
4188 }
4189
hri_sercomusart_get_INTEN_RXS_bit(const void * const hw)4190 static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
4191 {
4192 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
4193 }
4194
hri_sercomusart_write_INTEN_RXS_bit(const void * const hw,bool value)4195 static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
4196 {
4197 if (value == 0x0) {
4198 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
4199 } else {
4200 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
4201 }
4202 }
4203
hri_sercomusart_clear_INTEN_RXS_bit(const void * const hw)4204 static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
4205 {
4206 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
4207 }
4208
hri_sercomusart_set_INTEN_CTSIC_bit(const void * const hw)4209 static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
4210 {
4211 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
4212 }
4213
hri_sercomusart_get_INTEN_CTSIC_bit(const void * const hw)4214 static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
4215 {
4216 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
4217 }
4218
hri_sercomusart_write_INTEN_CTSIC_bit(const void * const hw,bool value)4219 static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
4220 {
4221 if (value == 0x0) {
4222 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
4223 } else {
4224 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
4225 }
4226 }
4227
hri_sercomusart_clear_INTEN_CTSIC_bit(const void * const hw)4228 static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
4229 {
4230 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
4231 }
4232
hri_sercomusart_set_INTEN_RXBRK_bit(const void * const hw)4233 static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
4234 {
4235 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
4236 }
4237
hri_sercomusart_get_INTEN_RXBRK_bit(const void * const hw)4238 static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
4239 {
4240 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
4241 }
4242
hri_sercomusart_write_INTEN_RXBRK_bit(const void * const hw,bool value)4243 static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
4244 {
4245 if (value == 0x0) {
4246 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
4247 } else {
4248 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
4249 }
4250 }
4251
hri_sercomusart_clear_INTEN_RXBRK_bit(const void * const hw)4252 static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
4253 {
4254 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
4255 }
4256
hri_sercomusart_set_INTEN_ERROR_bit(const void * const hw)4257 static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
4258 {
4259 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
4260 }
4261
hri_sercomusart_get_INTEN_ERROR_bit(const void * const hw)4262 static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
4263 {
4264 return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
4265 }
4266
hri_sercomusart_write_INTEN_ERROR_bit(const void * const hw,bool value)4267 static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
4268 {
4269 if (value == 0x0) {
4270 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
4271 } else {
4272 ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
4273 }
4274 }
4275
hri_sercomusart_clear_INTEN_ERROR_bit(const void * const hw)4276 static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
4277 {
4278 ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
4279 }
4280
hri_sercomusart_set_INTEN_reg(const void * const hw,hri_sercomusart_intenset_reg_t mask)4281 static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
4282 {
4283 ((Sercom *)hw)->USART.INTENSET.reg = mask;
4284 }
4285
hri_sercomusart_get_INTEN_reg(const void * const hw,hri_sercomusart_intenset_reg_t mask)4286 static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw,
4287 hri_sercomusart_intenset_reg_t mask)
4288 {
4289 uint8_t tmp;
4290 tmp = ((Sercom *)hw)->USART.INTENSET.reg;
4291 tmp &= mask;
4292 return tmp;
4293 }
4294
hri_sercomusart_read_INTEN_reg(const void * const hw)4295 static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
4296 {
4297 return ((Sercom *)hw)->USART.INTENSET.reg;
4298 }
4299
hri_sercomusart_write_INTEN_reg(const void * const hw,hri_sercomusart_intenset_reg_t data)4300 static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
4301 {
4302 ((Sercom *)hw)->USART.INTENSET.reg = data;
4303 ((Sercom *)hw)->USART.INTENCLR.reg = ~data;
4304 }
4305
hri_sercomusart_clear_INTEN_reg(const void * const hw,hri_sercomusart_intenset_reg_t mask)4306 static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
4307 {
4308 ((Sercom *)hw)->USART.INTENCLR.reg = mask;
4309 }
4310
hri_sercomusart_get_INTFLAG_DRE_bit(const void * const hw)4311 static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
4312 {
4313 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
4314 }
4315
hri_sercomusart_clear_INTFLAG_DRE_bit(const void * const hw)4316 static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
4317 {
4318 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
4319 }
4320
hri_sercomusart_get_INTFLAG_TXC_bit(const void * const hw)4321 static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
4322 {
4323 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
4324 }
4325
hri_sercomusart_clear_INTFLAG_TXC_bit(const void * const hw)4326 static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
4327 {
4328 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
4329 }
4330
hri_sercomusart_get_INTFLAG_RXC_bit(const void * const hw)4331 static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
4332 {
4333 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
4334 }
4335
hri_sercomusart_clear_INTFLAG_RXC_bit(const void * const hw)4336 static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
4337 {
4338 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
4339 }
4340
hri_sercomusart_get_INTFLAG_RXS_bit(const void * const hw)4341 static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
4342 {
4343 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
4344 }
4345
hri_sercomusart_clear_INTFLAG_RXS_bit(const void * const hw)4346 static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
4347 {
4348 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
4349 }
4350
hri_sercomusart_get_INTFLAG_CTSIC_bit(const void * const hw)4351 static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
4352 {
4353 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
4354 }
4355
hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void * const hw)4356 static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
4357 {
4358 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
4359 }
4360
hri_sercomusart_get_INTFLAG_RXBRK_bit(const void * const hw)4361 static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
4362 {
4363 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
4364 }
4365
hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void * const hw)4366 static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
4367 {
4368 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
4369 }
4370
hri_sercomusart_get_INTFLAG_ERROR_bit(const void * const hw)4371 static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
4372 {
4373 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
4374 }
4375
hri_sercomusart_clear_INTFLAG_ERROR_bit(const void * const hw)4376 static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
4377 {
4378 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
4379 }
4380
hri_sercomusart_get_interrupt_DRE_bit(const void * const hw)4381 static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
4382 {
4383 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
4384 }
4385
hri_sercomusart_clear_interrupt_DRE_bit(const void * const hw)4386 static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
4387 {
4388 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
4389 }
4390
hri_sercomusart_get_interrupt_TXC_bit(const void * const hw)4391 static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
4392 {
4393 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
4394 }
4395
hri_sercomusart_clear_interrupt_TXC_bit(const void * const hw)4396 static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
4397 {
4398 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
4399 }
4400
hri_sercomusart_get_interrupt_RXC_bit(const void * const hw)4401 static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
4402 {
4403 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
4404 }
4405
hri_sercomusart_clear_interrupt_RXC_bit(const void * const hw)4406 static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
4407 {
4408 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
4409 }
4410
hri_sercomusart_get_interrupt_RXS_bit(const void * const hw)4411 static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
4412 {
4413 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
4414 }
4415
hri_sercomusart_clear_interrupt_RXS_bit(const void * const hw)4416 static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
4417 {
4418 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
4419 }
4420
hri_sercomusart_get_interrupt_CTSIC_bit(const void * const hw)4421 static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
4422 {
4423 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
4424 }
4425
hri_sercomusart_clear_interrupt_CTSIC_bit(const void * const hw)4426 static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
4427 {
4428 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
4429 }
4430
hri_sercomusart_get_interrupt_RXBRK_bit(const void * const hw)4431 static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
4432 {
4433 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
4434 }
4435
hri_sercomusart_clear_interrupt_RXBRK_bit(const void * const hw)4436 static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
4437 {
4438 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
4439 }
4440
hri_sercomusart_get_interrupt_ERROR_bit(const void * const hw)4441 static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
4442 {
4443 return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
4444 }
4445
hri_sercomusart_clear_interrupt_ERROR_bit(const void * const hw)4446 static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
4447 {
4448 ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
4449 }
4450
hri_sercomusart_get_INTFLAG_reg(const void * const hw,hri_sercomusart_intflag_reg_t mask)4451 static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw,
4452 hri_sercomusart_intflag_reg_t mask)
4453 {
4454 uint8_t tmp;
4455 tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
4456 tmp &= mask;
4457 return tmp;
4458 }
4459
hri_sercomusart_read_INTFLAG_reg(const void * const hw)4460 static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
4461 {
4462 return ((Sercom *)hw)->USART.INTFLAG.reg;
4463 }
4464
hri_sercomusart_clear_INTFLAG_reg(const void * const hw,hri_sercomusart_intflag_reg_t mask)4465 static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
4466 {
4467 ((Sercom *)hw)->USART.INTFLAG.reg = mask;
4468 }
4469
hri_sercomusart_set_CTRLA_SWRST_bit(const void * const hw)4470 static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
4471 {
4472 SERCOM_CRITICAL_SECTION_ENTER();
4473 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
4474 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
4475 SERCOM_CRITICAL_SECTION_LEAVE();
4476 }
4477
hri_sercomusart_get_CTRLA_SWRST_bit(const void * const hw)4478 static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
4479 {
4480 uint32_t tmp;
4481 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
4482 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4483 tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
4484 return (bool)tmp;
4485 }
4486
hri_sercomusart_set_CTRLA_ENABLE_bit(const void * const hw)4487 static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
4488 {
4489 SERCOM_CRITICAL_SECTION_ENTER();
4490 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4491 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
4492 SERCOM_CRITICAL_SECTION_LEAVE();
4493 }
4494
hri_sercomusart_get_CTRLA_ENABLE_bit(const void * const hw)4495 static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
4496 {
4497 uint32_t tmp;
4498 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4499 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4500 tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
4501 return (bool)tmp;
4502 }
4503
hri_sercomusart_write_CTRLA_ENABLE_bit(const void * const hw,bool value)4504 static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
4505 {
4506 uint32_t tmp;
4507 SERCOM_CRITICAL_SECTION_ENTER();
4508 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4509 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4510 tmp &= ~SERCOM_USART_CTRLA_ENABLE;
4511 tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
4512 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4513 SERCOM_CRITICAL_SECTION_LEAVE();
4514 }
4515
hri_sercomusart_clear_CTRLA_ENABLE_bit(const void * const hw)4516 static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
4517 {
4518 SERCOM_CRITICAL_SECTION_ENTER();
4519 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4520 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
4521 SERCOM_CRITICAL_SECTION_LEAVE();
4522 }
4523
hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void * const hw)4524 static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
4525 {
4526 SERCOM_CRITICAL_SECTION_ENTER();
4527 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4528 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
4529 SERCOM_CRITICAL_SECTION_LEAVE();
4530 }
4531
hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void * const hw)4532 static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
4533 {
4534 SERCOM_CRITICAL_SECTION_ENTER();
4535 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4536 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
4537 SERCOM_CRITICAL_SECTION_LEAVE();
4538 }
4539
hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void * const hw)4540 static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
4541 {
4542 uint32_t tmp;
4543 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4544 tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
4545 return (bool)tmp;
4546 }
4547
hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)4548 static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
4549 {
4550 uint32_t tmp;
4551 SERCOM_CRITICAL_SECTION_ENTER();
4552 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4553 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4554 tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
4555 tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
4556 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4557 SERCOM_CRITICAL_SECTION_LEAVE();
4558 }
4559
hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void * const hw)4560 static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
4561 {
4562 SERCOM_CRITICAL_SECTION_ENTER();
4563 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4564 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
4565 SERCOM_CRITICAL_SECTION_LEAVE();
4566 }
4567
hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)4568 static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
4569 {
4570 SERCOM_CRITICAL_SECTION_ENTER();
4571 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4572 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
4573 SERCOM_CRITICAL_SECTION_LEAVE();
4574 }
4575
hri_sercomusart_set_CTRLA_IBON_bit(const void * const hw)4576 static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
4577 {
4578 SERCOM_CRITICAL_SECTION_ENTER();
4579 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4580 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
4581 SERCOM_CRITICAL_SECTION_LEAVE();
4582 }
4583
hri_sercomusart_get_CTRLA_IBON_bit(const void * const hw)4584 static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
4585 {
4586 uint32_t tmp;
4587 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4588 tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
4589 return (bool)tmp;
4590 }
4591
hri_sercomusart_write_CTRLA_IBON_bit(const void * const hw,bool value)4592 static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
4593 {
4594 uint32_t tmp;
4595 SERCOM_CRITICAL_SECTION_ENTER();
4596 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4597 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4598 tmp &= ~SERCOM_USART_CTRLA_IBON;
4599 tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
4600 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4601 SERCOM_CRITICAL_SECTION_LEAVE();
4602 }
4603
hri_sercomusart_clear_CTRLA_IBON_bit(const void * const hw)4604 static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
4605 {
4606 SERCOM_CRITICAL_SECTION_ENTER();
4607 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4608 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
4609 SERCOM_CRITICAL_SECTION_LEAVE();
4610 }
4611
hri_sercomusart_toggle_CTRLA_IBON_bit(const void * const hw)4612 static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
4613 {
4614 SERCOM_CRITICAL_SECTION_ENTER();
4615 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4616 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
4617 SERCOM_CRITICAL_SECTION_LEAVE();
4618 }
4619
hri_sercomusart_set_CTRLA_CMODE_bit(const void * const hw)4620 static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
4621 {
4622 SERCOM_CRITICAL_SECTION_ENTER();
4623 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4624 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
4625 SERCOM_CRITICAL_SECTION_LEAVE();
4626 }
4627
hri_sercomusart_get_CTRLA_CMODE_bit(const void * const hw)4628 static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
4629 {
4630 uint32_t tmp;
4631 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4632 tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
4633 return (bool)tmp;
4634 }
4635
hri_sercomusart_write_CTRLA_CMODE_bit(const void * const hw,bool value)4636 static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
4637 {
4638 uint32_t tmp;
4639 SERCOM_CRITICAL_SECTION_ENTER();
4640 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4641 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4642 tmp &= ~SERCOM_USART_CTRLA_CMODE;
4643 tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
4644 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4645 SERCOM_CRITICAL_SECTION_LEAVE();
4646 }
4647
hri_sercomusart_clear_CTRLA_CMODE_bit(const void * const hw)4648 static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
4649 {
4650 SERCOM_CRITICAL_SECTION_ENTER();
4651 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4652 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
4653 SERCOM_CRITICAL_SECTION_LEAVE();
4654 }
4655
hri_sercomusart_toggle_CTRLA_CMODE_bit(const void * const hw)4656 static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
4657 {
4658 SERCOM_CRITICAL_SECTION_ENTER();
4659 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4660 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
4661 SERCOM_CRITICAL_SECTION_LEAVE();
4662 }
4663
hri_sercomusart_set_CTRLA_CPOL_bit(const void * const hw)4664 static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
4665 {
4666 SERCOM_CRITICAL_SECTION_ENTER();
4667 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4668 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
4669 SERCOM_CRITICAL_SECTION_LEAVE();
4670 }
4671
hri_sercomusart_get_CTRLA_CPOL_bit(const void * const hw)4672 static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
4673 {
4674 uint32_t tmp;
4675 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4676 tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
4677 return (bool)tmp;
4678 }
4679
hri_sercomusart_write_CTRLA_CPOL_bit(const void * const hw,bool value)4680 static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
4681 {
4682 uint32_t tmp;
4683 SERCOM_CRITICAL_SECTION_ENTER();
4684 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4685 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4686 tmp &= ~SERCOM_USART_CTRLA_CPOL;
4687 tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
4688 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4689 SERCOM_CRITICAL_SECTION_LEAVE();
4690 }
4691
hri_sercomusart_clear_CTRLA_CPOL_bit(const void * const hw)4692 static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
4693 {
4694 SERCOM_CRITICAL_SECTION_ENTER();
4695 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4696 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
4697 SERCOM_CRITICAL_SECTION_LEAVE();
4698 }
4699
hri_sercomusart_toggle_CTRLA_CPOL_bit(const void * const hw)4700 static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
4701 {
4702 SERCOM_CRITICAL_SECTION_ENTER();
4703 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4704 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
4705 SERCOM_CRITICAL_SECTION_LEAVE();
4706 }
4707
hri_sercomusart_set_CTRLA_DORD_bit(const void * const hw)4708 static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
4709 {
4710 SERCOM_CRITICAL_SECTION_ENTER();
4711 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4712 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
4713 SERCOM_CRITICAL_SECTION_LEAVE();
4714 }
4715
hri_sercomusart_get_CTRLA_DORD_bit(const void * const hw)4716 static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
4717 {
4718 uint32_t tmp;
4719 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4720 tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
4721 return (bool)tmp;
4722 }
4723
hri_sercomusart_write_CTRLA_DORD_bit(const void * const hw,bool value)4724 static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
4725 {
4726 uint32_t tmp;
4727 SERCOM_CRITICAL_SECTION_ENTER();
4728 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4729 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4730 tmp &= ~SERCOM_USART_CTRLA_DORD;
4731 tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
4732 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4733 SERCOM_CRITICAL_SECTION_LEAVE();
4734 }
4735
hri_sercomusart_clear_CTRLA_DORD_bit(const void * const hw)4736 static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
4737 {
4738 SERCOM_CRITICAL_SECTION_ENTER();
4739 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4740 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
4741 SERCOM_CRITICAL_SECTION_LEAVE();
4742 }
4743
hri_sercomusart_toggle_CTRLA_DORD_bit(const void * const hw)4744 static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
4745 {
4746 SERCOM_CRITICAL_SECTION_ENTER();
4747 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4748 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
4749 SERCOM_CRITICAL_SECTION_LEAVE();
4750 }
4751
hri_sercomusart_set_CTRLA_MODE_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4752 static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4753 {
4754 SERCOM_CRITICAL_SECTION_ENTER();
4755 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4756 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
4757 SERCOM_CRITICAL_SECTION_LEAVE();
4758 }
4759
hri_sercomusart_get_CTRLA_MODE_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4760 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw,
4761 hri_sercomusart_ctrla_reg_t mask)
4762 {
4763 uint32_t tmp;
4764 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4765 tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
4766 return tmp;
4767 }
4768
hri_sercomusart_write_CTRLA_MODE_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)4769 static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
4770 {
4771 uint32_t tmp;
4772 SERCOM_CRITICAL_SECTION_ENTER();
4773 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4774 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4775 tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
4776 tmp |= SERCOM_USART_CTRLA_MODE(data);
4777 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4778 SERCOM_CRITICAL_SECTION_LEAVE();
4779 }
4780
hri_sercomusart_clear_CTRLA_MODE_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4781 static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4782 {
4783 SERCOM_CRITICAL_SECTION_ENTER();
4784 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4785 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
4786 SERCOM_CRITICAL_SECTION_LEAVE();
4787 }
4788
hri_sercomusart_toggle_CTRLA_MODE_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4789 static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4790 {
4791 SERCOM_CRITICAL_SECTION_ENTER();
4792 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4793 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
4794 SERCOM_CRITICAL_SECTION_LEAVE();
4795 }
4796
hri_sercomusart_read_CTRLA_MODE_bf(const void * const hw)4797 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
4798 {
4799 uint32_t tmp;
4800 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4801 tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
4802 return tmp;
4803 }
4804
hri_sercomusart_set_CTRLA_SAMPR_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4805 static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4806 {
4807 SERCOM_CRITICAL_SECTION_ENTER();
4808 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4809 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
4810 SERCOM_CRITICAL_SECTION_LEAVE();
4811 }
4812
hri_sercomusart_get_CTRLA_SAMPR_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4813 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw,
4814 hri_sercomusart_ctrla_reg_t mask)
4815 {
4816 uint32_t tmp;
4817 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4818 tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
4819 return tmp;
4820 }
4821
hri_sercomusart_write_CTRLA_SAMPR_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)4822 static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
4823 {
4824 uint32_t tmp;
4825 SERCOM_CRITICAL_SECTION_ENTER();
4826 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4827 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4828 tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
4829 tmp |= SERCOM_USART_CTRLA_SAMPR(data);
4830 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4831 SERCOM_CRITICAL_SECTION_LEAVE();
4832 }
4833
hri_sercomusart_clear_CTRLA_SAMPR_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4834 static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4835 {
4836 SERCOM_CRITICAL_SECTION_ENTER();
4837 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4838 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
4839 SERCOM_CRITICAL_SECTION_LEAVE();
4840 }
4841
hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4842 static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4843 {
4844 SERCOM_CRITICAL_SECTION_ENTER();
4845 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4846 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
4847 SERCOM_CRITICAL_SECTION_LEAVE();
4848 }
4849
hri_sercomusart_read_CTRLA_SAMPR_bf(const void * const hw)4850 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
4851 {
4852 uint32_t tmp;
4853 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4854 tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
4855 return tmp;
4856 }
4857
hri_sercomusart_set_CTRLA_TXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4858 static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4859 {
4860 SERCOM_CRITICAL_SECTION_ENTER();
4861 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4862 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
4863 SERCOM_CRITICAL_SECTION_LEAVE();
4864 }
4865
hri_sercomusart_get_CTRLA_TXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4866 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw,
4867 hri_sercomusart_ctrla_reg_t mask)
4868 {
4869 uint32_t tmp;
4870 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4871 tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
4872 return tmp;
4873 }
4874
hri_sercomusart_write_CTRLA_TXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)4875 static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
4876 {
4877 uint32_t tmp;
4878 SERCOM_CRITICAL_SECTION_ENTER();
4879 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4880 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4881 tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
4882 tmp |= SERCOM_USART_CTRLA_TXPO(data);
4883 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4884 SERCOM_CRITICAL_SECTION_LEAVE();
4885 }
4886
hri_sercomusart_clear_CTRLA_TXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4887 static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4888 {
4889 SERCOM_CRITICAL_SECTION_ENTER();
4890 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4891 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
4892 SERCOM_CRITICAL_SECTION_LEAVE();
4893 }
4894
hri_sercomusart_toggle_CTRLA_TXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4895 static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4896 {
4897 SERCOM_CRITICAL_SECTION_ENTER();
4898 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4899 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
4900 SERCOM_CRITICAL_SECTION_LEAVE();
4901 }
4902
hri_sercomusart_read_CTRLA_TXPO_bf(const void * const hw)4903 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
4904 {
4905 uint32_t tmp;
4906 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4907 tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
4908 return tmp;
4909 }
4910
hri_sercomusart_set_CTRLA_RXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4911 static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4912 {
4913 SERCOM_CRITICAL_SECTION_ENTER();
4914 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4915 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
4916 SERCOM_CRITICAL_SECTION_LEAVE();
4917 }
4918
hri_sercomusart_get_CTRLA_RXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4919 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw,
4920 hri_sercomusart_ctrla_reg_t mask)
4921 {
4922 uint32_t tmp;
4923 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4924 tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
4925 return tmp;
4926 }
4927
hri_sercomusart_write_CTRLA_RXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)4928 static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
4929 {
4930 uint32_t tmp;
4931 SERCOM_CRITICAL_SECTION_ENTER();
4932 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4933 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4934 tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
4935 tmp |= SERCOM_USART_CTRLA_RXPO(data);
4936 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4937 SERCOM_CRITICAL_SECTION_LEAVE();
4938 }
4939
hri_sercomusart_clear_CTRLA_RXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4940 static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4941 {
4942 SERCOM_CRITICAL_SECTION_ENTER();
4943 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4944 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
4945 SERCOM_CRITICAL_SECTION_LEAVE();
4946 }
4947
hri_sercomusart_toggle_CTRLA_RXPO_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4948 static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4949 {
4950 SERCOM_CRITICAL_SECTION_ENTER();
4951 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4952 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
4953 SERCOM_CRITICAL_SECTION_LEAVE();
4954 }
4955
hri_sercomusart_read_CTRLA_RXPO_bf(const void * const hw)4956 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
4957 {
4958 uint32_t tmp;
4959 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4960 tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
4961 return tmp;
4962 }
4963
hri_sercomusart_set_CTRLA_SAMPA_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4964 static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4965 {
4966 SERCOM_CRITICAL_SECTION_ENTER();
4967 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4968 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
4969 SERCOM_CRITICAL_SECTION_LEAVE();
4970 }
4971
hri_sercomusart_get_CTRLA_SAMPA_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4972 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw,
4973 hri_sercomusart_ctrla_reg_t mask)
4974 {
4975 uint32_t tmp;
4976 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4977 tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
4978 return tmp;
4979 }
4980
hri_sercomusart_write_CTRLA_SAMPA_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)4981 static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
4982 {
4983 uint32_t tmp;
4984 SERCOM_CRITICAL_SECTION_ENTER();
4985 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4986 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4987 tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
4988 tmp |= SERCOM_USART_CTRLA_SAMPA(data);
4989 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
4990 SERCOM_CRITICAL_SECTION_LEAVE();
4991 }
4992
hri_sercomusart_clear_CTRLA_SAMPA_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)4993 static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
4994 {
4995 SERCOM_CRITICAL_SECTION_ENTER();
4996 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4997 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
4998 SERCOM_CRITICAL_SECTION_LEAVE();
4999 }
5000
hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5001 static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5002 {
5003 SERCOM_CRITICAL_SECTION_ENTER();
5004 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
5005 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
5006 SERCOM_CRITICAL_SECTION_LEAVE();
5007 }
5008
hri_sercomusart_read_CTRLA_SAMPA_bf(const void * const hw)5009 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
5010 {
5011 uint32_t tmp;
5012 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
5013 tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
5014 return tmp;
5015 }
5016
hri_sercomusart_set_CTRLA_FORM_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5017 static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5018 {
5019 SERCOM_CRITICAL_SECTION_ENTER();
5020 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
5021 ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
5022 SERCOM_CRITICAL_SECTION_LEAVE();
5023 }
5024
hri_sercomusart_get_CTRLA_FORM_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5025 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw,
5026 hri_sercomusart_ctrla_reg_t mask)
5027 {
5028 uint32_t tmp;
5029 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
5030 tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
5031 return tmp;
5032 }
5033
hri_sercomusart_write_CTRLA_FORM_bf(const void * const hw,hri_sercomusart_ctrla_reg_t data)5034 static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
5035 {
5036 uint32_t tmp;
5037 SERCOM_CRITICAL_SECTION_ENTER();
5038 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
5039 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
5040 tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
5041 tmp |= SERCOM_USART_CTRLA_FORM(data);
5042 ((Sercom *)hw)->USART.CTRLA.reg = tmp;
5043 SERCOM_CRITICAL_SECTION_LEAVE();
5044 }
5045
hri_sercomusart_clear_CTRLA_FORM_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5046 static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5047 {
5048 SERCOM_CRITICAL_SECTION_ENTER();
5049 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
5050 ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
5051 SERCOM_CRITICAL_SECTION_LEAVE();
5052 }
5053
hri_sercomusart_toggle_CTRLA_FORM_bf(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5054 static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5055 {
5056 SERCOM_CRITICAL_SECTION_ENTER();
5057 hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
5058 ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
5059 SERCOM_CRITICAL_SECTION_LEAVE();
5060 }
5061
hri_sercomusart_read_CTRLA_FORM_bf(const void * const hw)5062 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
5063 {
5064 uint32_t tmp;
5065 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
5066 tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
5067 return tmp;
5068 }
5069
hri_sercomusart_set_CTRLA_reg(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5070 static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5071 {
5072 SERCOM_CRITICAL_SECTION_ENTER();
5073 ((Sercom *)hw)->USART.CTRLA.reg |= mask;
5074 SERCOM_CRITICAL_SECTION_LEAVE();
5075 }
5076
hri_sercomusart_get_CTRLA_reg(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5077 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw,
5078 hri_sercomusart_ctrla_reg_t mask)
5079 {
5080 uint32_t tmp;
5081 tmp = ((Sercom *)hw)->USART.CTRLA.reg;
5082 tmp &= mask;
5083 return tmp;
5084 }
5085
hri_sercomusart_write_CTRLA_reg(const void * const hw,hri_sercomusart_ctrla_reg_t data)5086 static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
5087 {
5088 SERCOM_CRITICAL_SECTION_ENTER();
5089 ((Sercom *)hw)->USART.CTRLA.reg = data;
5090 SERCOM_CRITICAL_SECTION_LEAVE();
5091 }
5092
hri_sercomusart_clear_CTRLA_reg(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5093 static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5094 {
5095 SERCOM_CRITICAL_SECTION_ENTER();
5096 ((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
5097 SERCOM_CRITICAL_SECTION_LEAVE();
5098 }
5099
hri_sercomusart_toggle_CTRLA_reg(const void * const hw,hri_sercomusart_ctrla_reg_t mask)5100 static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
5101 {
5102 SERCOM_CRITICAL_SECTION_ENTER();
5103 ((Sercom *)hw)->USART.CTRLA.reg ^= mask;
5104 SERCOM_CRITICAL_SECTION_LEAVE();
5105 }
5106
hri_sercomusart_read_CTRLA_reg(const void * const hw)5107 static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
5108 {
5109 return ((Sercom *)hw)->USART.CTRLA.reg;
5110 }
5111
hri_sercomusart_set_CTRLB_SBMODE_bit(const void * const hw)5112 static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
5113 {
5114 SERCOM_CRITICAL_SECTION_ENTER();
5115 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
5116 SERCOM_CRITICAL_SECTION_LEAVE();
5117 }
5118
hri_sercomusart_get_CTRLB_SBMODE_bit(const void * const hw)5119 static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
5120 {
5121 uint32_t tmp;
5122 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5123 tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
5124 return (bool)tmp;
5125 }
5126
hri_sercomusart_write_CTRLB_SBMODE_bit(const void * const hw,bool value)5127 static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
5128 {
5129 uint32_t tmp;
5130 SERCOM_CRITICAL_SECTION_ENTER();
5131 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5132 tmp &= ~SERCOM_USART_CTRLB_SBMODE;
5133 tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
5134 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5135 SERCOM_CRITICAL_SECTION_LEAVE();
5136 }
5137
hri_sercomusart_clear_CTRLB_SBMODE_bit(const void * const hw)5138 static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
5139 {
5140 SERCOM_CRITICAL_SECTION_ENTER();
5141 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
5142 SERCOM_CRITICAL_SECTION_LEAVE();
5143 }
5144
hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void * const hw)5145 static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
5146 {
5147 SERCOM_CRITICAL_SECTION_ENTER();
5148 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
5149 SERCOM_CRITICAL_SECTION_LEAVE();
5150 }
5151
hri_sercomusart_set_CTRLB_COLDEN_bit(const void * const hw)5152 static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
5153 {
5154 SERCOM_CRITICAL_SECTION_ENTER();
5155 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
5156 SERCOM_CRITICAL_SECTION_LEAVE();
5157 }
5158
hri_sercomusart_get_CTRLB_COLDEN_bit(const void * const hw)5159 static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
5160 {
5161 uint32_t tmp;
5162 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5163 tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
5164 return (bool)tmp;
5165 }
5166
hri_sercomusart_write_CTRLB_COLDEN_bit(const void * const hw,bool value)5167 static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
5168 {
5169 uint32_t tmp;
5170 SERCOM_CRITICAL_SECTION_ENTER();
5171 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5172 tmp &= ~SERCOM_USART_CTRLB_COLDEN;
5173 tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
5174 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5175 SERCOM_CRITICAL_SECTION_LEAVE();
5176 }
5177
hri_sercomusart_clear_CTRLB_COLDEN_bit(const void * const hw)5178 static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
5179 {
5180 SERCOM_CRITICAL_SECTION_ENTER();
5181 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
5182 SERCOM_CRITICAL_SECTION_LEAVE();
5183 }
5184
hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void * const hw)5185 static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
5186 {
5187 SERCOM_CRITICAL_SECTION_ENTER();
5188 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
5189 SERCOM_CRITICAL_SECTION_LEAVE();
5190 }
5191
hri_sercomusart_set_CTRLB_SFDE_bit(const void * const hw)5192 static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
5193 {
5194 SERCOM_CRITICAL_SECTION_ENTER();
5195 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
5196 SERCOM_CRITICAL_SECTION_LEAVE();
5197 }
5198
hri_sercomusart_get_CTRLB_SFDE_bit(const void * const hw)5199 static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
5200 {
5201 uint32_t tmp;
5202 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5203 tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
5204 return (bool)tmp;
5205 }
5206
hri_sercomusart_write_CTRLB_SFDE_bit(const void * const hw,bool value)5207 static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
5208 {
5209 uint32_t tmp;
5210 SERCOM_CRITICAL_SECTION_ENTER();
5211 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5212 tmp &= ~SERCOM_USART_CTRLB_SFDE;
5213 tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
5214 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5215 SERCOM_CRITICAL_SECTION_LEAVE();
5216 }
5217
hri_sercomusart_clear_CTRLB_SFDE_bit(const void * const hw)5218 static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
5219 {
5220 SERCOM_CRITICAL_SECTION_ENTER();
5221 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
5222 SERCOM_CRITICAL_SECTION_LEAVE();
5223 }
5224
hri_sercomusart_toggle_CTRLB_SFDE_bit(const void * const hw)5225 static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
5226 {
5227 SERCOM_CRITICAL_SECTION_ENTER();
5228 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
5229 SERCOM_CRITICAL_SECTION_LEAVE();
5230 }
5231
hri_sercomusart_set_CTRLB_ENC_bit(const void * const hw)5232 static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
5233 {
5234 SERCOM_CRITICAL_SECTION_ENTER();
5235 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
5236 SERCOM_CRITICAL_SECTION_LEAVE();
5237 }
5238
hri_sercomusart_get_CTRLB_ENC_bit(const void * const hw)5239 static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
5240 {
5241 uint32_t tmp;
5242 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5243 tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
5244 return (bool)tmp;
5245 }
5246
hri_sercomusart_write_CTRLB_ENC_bit(const void * const hw,bool value)5247 static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
5248 {
5249 uint32_t tmp;
5250 SERCOM_CRITICAL_SECTION_ENTER();
5251 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5252 tmp &= ~SERCOM_USART_CTRLB_ENC;
5253 tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
5254 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5255 SERCOM_CRITICAL_SECTION_LEAVE();
5256 }
5257
hri_sercomusart_clear_CTRLB_ENC_bit(const void * const hw)5258 static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
5259 {
5260 SERCOM_CRITICAL_SECTION_ENTER();
5261 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
5262 SERCOM_CRITICAL_SECTION_LEAVE();
5263 }
5264
hri_sercomusart_toggle_CTRLB_ENC_bit(const void * const hw)5265 static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
5266 {
5267 SERCOM_CRITICAL_SECTION_ENTER();
5268 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
5269 SERCOM_CRITICAL_SECTION_LEAVE();
5270 }
5271
hri_sercomusart_set_CTRLB_PMODE_bit(const void * const hw)5272 static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
5273 {
5274 SERCOM_CRITICAL_SECTION_ENTER();
5275 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
5276 SERCOM_CRITICAL_SECTION_LEAVE();
5277 }
5278
hri_sercomusart_get_CTRLB_PMODE_bit(const void * const hw)5279 static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
5280 {
5281 uint32_t tmp;
5282 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5283 tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
5284 return (bool)tmp;
5285 }
5286
hri_sercomusart_write_CTRLB_PMODE_bit(const void * const hw,bool value)5287 static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
5288 {
5289 uint32_t tmp;
5290 SERCOM_CRITICAL_SECTION_ENTER();
5291 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5292 tmp &= ~SERCOM_USART_CTRLB_PMODE;
5293 tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
5294 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5295 SERCOM_CRITICAL_SECTION_LEAVE();
5296 }
5297
hri_sercomusart_clear_CTRLB_PMODE_bit(const void * const hw)5298 static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
5299 {
5300 SERCOM_CRITICAL_SECTION_ENTER();
5301 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
5302 SERCOM_CRITICAL_SECTION_LEAVE();
5303 }
5304
hri_sercomusart_toggle_CTRLB_PMODE_bit(const void * const hw)5305 static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
5306 {
5307 SERCOM_CRITICAL_SECTION_ENTER();
5308 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
5309 SERCOM_CRITICAL_SECTION_LEAVE();
5310 }
5311
hri_sercomusart_set_CTRLB_TXEN_bit(const void * const hw)5312 static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
5313 {
5314 SERCOM_CRITICAL_SECTION_ENTER();
5315 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
5316 SERCOM_CRITICAL_SECTION_LEAVE();
5317 }
5318
hri_sercomusart_get_CTRLB_TXEN_bit(const void * const hw)5319 static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
5320 {
5321 uint32_t tmp;
5322 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5323 tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
5324 return (bool)tmp;
5325 }
5326
hri_sercomusart_write_CTRLB_TXEN_bit(const void * const hw,bool value)5327 static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
5328 {
5329 uint32_t tmp;
5330 SERCOM_CRITICAL_SECTION_ENTER();
5331 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5332 tmp &= ~SERCOM_USART_CTRLB_TXEN;
5333 tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
5334 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5335 SERCOM_CRITICAL_SECTION_LEAVE();
5336 }
5337
hri_sercomusart_clear_CTRLB_TXEN_bit(const void * const hw)5338 static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
5339 {
5340 SERCOM_CRITICAL_SECTION_ENTER();
5341 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
5342 SERCOM_CRITICAL_SECTION_LEAVE();
5343 }
5344
hri_sercomusart_toggle_CTRLB_TXEN_bit(const void * const hw)5345 static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
5346 {
5347 SERCOM_CRITICAL_SECTION_ENTER();
5348 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
5349 SERCOM_CRITICAL_SECTION_LEAVE();
5350 }
5351
hri_sercomusart_set_CTRLB_RXEN_bit(const void * const hw)5352 static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
5353 {
5354 SERCOM_CRITICAL_SECTION_ENTER();
5355 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
5356 SERCOM_CRITICAL_SECTION_LEAVE();
5357 }
5358
hri_sercomusart_get_CTRLB_RXEN_bit(const void * const hw)5359 static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
5360 {
5361 uint32_t tmp;
5362 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5363 tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
5364 return (bool)tmp;
5365 }
5366
hri_sercomusart_write_CTRLB_RXEN_bit(const void * const hw,bool value)5367 static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
5368 {
5369 uint32_t tmp;
5370 SERCOM_CRITICAL_SECTION_ENTER();
5371 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5372 tmp &= ~SERCOM_USART_CTRLB_RXEN;
5373 tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
5374 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5375 SERCOM_CRITICAL_SECTION_LEAVE();
5376 }
5377
hri_sercomusart_clear_CTRLB_RXEN_bit(const void * const hw)5378 static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
5379 {
5380 SERCOM_CRITICAL_SECTION_ENTER();
5381 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
5382 SERCOM_CRITICAL_SECTION_LEAVE();
5383 }
5384
hri_sercomusart_toggle_CTRLB_RXEN_bit(const void * const hw)5385 static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
5386 {
5387 SERCOM_CRITICAL_SECTION_ENTER();
5388 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
5389 SERCOM_CRITICAL_SECTION_LEAVE();
5390 }
5391
hri_sercomusart_set_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5392 static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5393 {
5394 SERCOM_CRITICAL_SECTION_ENTER();
5395 ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
5396 SERCOM_CRITICAL_SECTION_LEAVE();
5397 }
5398
hri_sercomusart_get_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5399 static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw,
5400 hri_sercomusart_ctrlb_reg_t mask)
5401 {
5402 uint32_t tmp;
5403 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5404 tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
5405 return tmp;
5406 }
5407
hri_sercomusart_write_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomusart_ctrlb_reg_t data)5408 static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
5409 {
5410 uint32_t tmp;
5411 SERCOM_CRITICAL_SECTION_ENTER();
5412 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5413 tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
5414 tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
5415 ((Sercom *)hw)->USART.CTRLB.reg = tmp;
5416 SERCOM_CRITICAL_SECTION_LEAVE();
5417 }
5418
hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5419 static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5420 {
5421 SERCOM_CRITICAL_SECTION_ENTER();
5422 ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
5423 SERCOM_CRITICAL_SECTION_LEAVE();
5424 }
5425
hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5426 static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5427 {
5428 SERCOM_CRITICAL_SECTION_ENTER();
5429 ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
5430 SERCOM_CRITICAL_SECTION_LEAVE();
5431 }
5432
hri_sercomusart_read_CTRLB_CHSIZE_bf(const void * const hw)5433 static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
5434 {
5435 uint32_t tmp;
5436 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5437 tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
5438 return tmp;
5439 }
5440
hri_sercomusart_set_CTRLB_reg(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5441 static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5442 {
5443 SERCOM_CRITICAL_SECTION_ENTER();
5444 ((Sercom *)hw)->USART.CTRLB.reg |= mask;
5445 SERCOM_CRITICAL_SECTION_LEAVE();
5446 }
5447
hri_sercomusart_get_CTRLB_reg(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5448 static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw,
5449 hri_sercomusart_ctrlb_reg_t mask)
5450 {
5451 uint32_t tmp;
5452 tmp = ((Sercom *)hw)->USART.CTRLB.reg;
5453 tmp &= mask;
5454 return tmp;
5455 }
5456
hri_sercomusart_write_CTRLB_reg(const void * const hw,hri_sercomusart_ctrlb_reg_t data)5457 static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
5458 {
5459 SERCOM_CRITICAL_SECTION_ENTER();
5460 ((Sercom *)hw)->USART.CTRLB.reg = data;
5461 SERCOM_CRITICAL_SECTION_LEAVE();
5462 }
5463
hri_sercomusart_clear_CTRLB_reg(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5464 static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5465 {
5466 SERCOM_CRITICAL_SECTION_ENTER();
5467 ((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
5468 SERCOM_CRITICAL_SECTION_LEAVE();
5469 }
5470
hri_sercomusart_toggle_CTRLB_reg(const void * const hw,hri_sercomusart_ctrlb_reg_t mask)5471 static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
5472 {
5473 SERCOM_CRITICAL_SECTION_ENTER();
5474 ((Sercom *)hw)->USART.CTRLB.reg ^= mask;
5475 SERCOM_CRITICAL_SECTION_LEAVE();
5476 }
5477
hri_sercomusart_read_CTRLB_reg(const void * const hw)5478 static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
5479 {
5480 return ((Sercom *)hw)->USART.CTRLB.reg;
5481 }
5482
hri_sercomusart_set_RXPL_RXPL_bf(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5483 static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5484 {
5485 SERCOM_CRITICAL_SECTION_ENTER();
5486 ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
5487 SERCOM_CRITICAL_SECTION_LEAVE();
5488 }
5489
hri_sercomusart_get_RXPL_RXPL_bf(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5490 static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw,
5491 hri_sercomusart_rxpl_reg_t mask)
5492 {
5493 uint8_t tmp;
5494 tmp = ((Sercom *)hw)->USART.RXPL.reg;
5495 tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
5496 return tmp;
5497 }
5498
hri_sercomusart_write_RXPL_RXPL_bf(const void * const hw,hri_sercomusart_rxpl_reg_t data)5499 static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
5500 {
5501 uint8_t tmp;
5502 SERCOM_CRITICAL_SECTION_ENTER();
5503 tmp = ((Sercom *)hw)->USART.RXPL.reg;
5504 tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
5505 tmp |= SERCOM_USART_RXPL_RXPL(data);
5506 ((Sercom *)hw)->USART.RXPL.reg = tmp;
5507 SERCOM_CRITICAL_SECTION_LEAVE();
5508 }
5509
hri_sercomusart_clear_RXPL_RXPL_bf(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5510 static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5511 {
5512 SERCOM_CRITICAL_SECTION_ENTER();
5513 ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
5514 SERCOM_CRITICAL_SECTION_LEAVE();
5515 }
5516
hri_sercomusart_toggle_RXPL_RXPL_bf(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5517 static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5518 {
5519 SERCOM_CRITICAL_SECTION_ENTER();
5520 ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
5521 SERCOM_CRITICAL_SECTION_LEAVE();
5522 }
5523
hri_sercomusart_read_RXPL_RXPL_bf(const void * const hw)5524 static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
5525 {
5526 uint8_t tmp;
5527 tmp = ((Sercom *)hw)->USART.RXPL.reg;
5528 tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
5529 return tmp;
5530 }
5531
hri_sercomusart_set_RXPL_reg(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5532 static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5533 {
5534 SERCOM_CRITICAL_SECTION_ENTER();
5535 ((Sercom *)hw)->USART.RXPL.reg |= mask;
5536 SERCOM_CRITICAL_SECTION_LEAVE();
5537 }
5538
hri_sercomusart_get_RXPL_reg(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5539 static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw,
5540 hri_sercomusart_rxpl_reg_t mask)
5541 {
5542 uint8_t tmp;
5543 tmp = ((Sercom *)hw)->USART.RXPL.reg;
5544 tmp &= mask;
5545 return tmp;
5546 }
5547
hri_sercomusart_write_RXPL_reg(const void * const hw,hri_sercomusart_rxpl_reg_t data)5548 static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
5549 {
5550 SERCOM_CRITICAL_SECTION_ENTER();
5551 ((Sercom *)hw)->USART.RXPL.reg = data;
5552 SERCOM_CRITICAL_SECTION_LEAVE();
5553 }
5554
hri_sercomusart_clear_RXPL_reg(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5555 static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5556 {
5557 SERCOM_CRITICAL_SECTION_ENTER();
5558 ((Sercom *)hw)->USART.RXPL.reg &= ~mask;
5559 SERCOM_CRITICAL_SECTION_LEAVE();
5560 }
5561
hri_sercomusart_toggle_RXPL_reg(const void * const hw,hri_sercomusart_rxpl_reg_t mask)5562 static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
5563 {
5564 SERCOM_CRITICAL_SECTION_ENTER();
5565 ((Sercom *)hw)->USART.RXPL.reg ^= mask;
5566 SERCOM_CRITICAL_SECTION_LEAVE();
5567 }
5568
hri_sercomusart_read_RXPL_reg(const void * const hw)5569 static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
5570 {
5571 return ((Sercom *)hw)->USART.RXPL.reg;
5572 }
5573
hri_sercomusart_read_DATA_reg(const void * const hw)5574 static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
5575 {
5576 return ((Sercom *)hw)->USART.DATA.reg;
5577 }
5578
hri_sercomusart_write_DATA_reg(const void * const hw,hri_sercomusart_data_reg_t data)5579 static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
5580 {
5581 SERCOM_CRITICAL_SECTION_ENTER();
5582 ((Sercom *)hw)->USART.DATA.reg = data;
5583 SERCOM_CRITICAL_SECTION_LEAVE();
5584 }
5585
hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void * const hw)5586 static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
5587 {
5588 SERCOM_CRITICAL_SECTION_ENTER();
5589 ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
5590 SERCOM_CRITICAL_SECTION_LEAVE();
5591 }
5592
hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void * const hw)5593 static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
5594 {
5595 uint8_t tmp;
5596 tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
5597 tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
5598 return (bool)tmp;
5599 }
5600
hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void * const hw,bool value)5601 static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
5602 {
5603 uint8_t tmp;
5604 SERCOM_CRITICAL_SECTION_ENTER();
5605 tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
5606 tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
5607 tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
5608 ((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
5609 SERCOM_CRITICAL_SECTION_LEAVE();
5610 }
5611
hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void * const hw)5612 static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
5613 {
5614 SERCOM_CRITICAL_SECTION_ENTER();
5615 ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
5616 SERCOM_CRITICAL_SECTION_LEAVE();
5617 }
5618
hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void * const hw)5619 static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
5620 {
5621 SERCOM_CRITICAL_SECTION_ENTER();
5622 ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
5623 SERCOM_CRITICAL_SECTION_LEAVE();
5624 }
5625
hri_sercomusart_set_DBGCTRL_reg(const void * const hw,hri_sercomusart_dbgctrl_reg_t mask)5626 static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
5627 {
5628 SERCOM_CRITICAL_SECTION_ENTER();
5629 ((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
5630 SERCOM_CRITICAL_SECTION_LEAVE();
5631 }
5632
hri_sercomusart_get_DBGCTRL_reg(const void * const hw,hri_sercomusart_dbgctrl_reg_t mask)5633 static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw,
5634 hri_sercomusart_dbgctrl_reg_t mask)
5635 {
5636 uint8_t tmp;
5637 tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
5638 tmp &= mask;
5639 return tmp;
5640 }
5641
hri_sercomusart_write_DBGCTRL_reg(const void * const hw,hri_sercomusart_dbgctrl_reg_t data)5642 static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
5643 {
5644 SERCOM_CRITICAL_SECTION_ENTER();
5645 ((Sercom *)hw)->USART.DBGCTRL.reg = data;
5646 SERCOM_CRITICAL_SECTION_LEAVE();
5647 }
5648
hri_sercomusart_clear_DBGCTRL_reg(const void * const hw,hri_sercomusart_dbgctrl_reg_t mask)5649 static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
5650 {
5651 SERCOM_CRITICAL_SECTION_ENTER();
5652 ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
5653 SERCOM_CRITICAL_SECTION_LEAVE();
5654 }
5655
hri_sercomusart_toggle_DBGCTRL_reg(const void * const hw,hri_sercomusart_dbgctrl_reg_t mask)5656 static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
5657 {
5658 SERCOM_CRITICAL_SECTION_ENTER();
5659 ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
5660 SERCOM_CRITICAL_SECTION_LEAVE();
5661 }
5662
hri_sercomusart_read_DBGCTRL_reg(const void * const hw)5663 static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
5664 {
5665 return ((Sercom *)hw)->USART.DBGCTRL.reg;
5666 }
5667
hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void * const hw)5668 static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
5669 {
5670 return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
5671 }
5672
hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void * const hw)5673 static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
5674 {
5675 return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
5676 }
5677
hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void * const hw)5678 static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
5679 {
5680 return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
5681 }
5682
hri_sercomusart_get_SYNCBUSY_reg(const void * const hw,hri_sercomusart_syncbusy_reg_t mask)5683 static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw,
5684 hri_sercomusart_syncbusy_reg_t mask)
5685 {
5686 uint32_t tmp;
5687 tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
5688 tmp &= mask;
5689 return tmp;
5690 }
5691
hri_sercomusart_read_SYNCBUSY_reg(const void * const hw)5692 static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
5693 {
5694 return ((Sercom *)hw)->USART.SYNCBUSY.reg;
5695 }
5696
hri_sercomusart_get_STATUS_PERR_bit(const void * const hw)5697 static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
5698 {
5699 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
5700 }
5701
hri_sercomusart_clear_STATUS_PERR_bit(const void * const hw)5702 static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
5703 {
5704 SERCOM_CRITICAL_SECTION_ENTER();
5705 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
5706 SERCOM_CRITICAL_SECTION_LEAVE();
5707 }
5708
hri_sercomusart_get_STATUS_FERR_bit(const void * const hw)5709 static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
5710 {
5711 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
5712 }
5713
hri_sercomusart_clear_STATUS_FERR_bit(const void * const hw)5714 static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
5715 {
5716 SERCOM_CRITICAL_SECTION_ENTER();
5717 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
5718 SERCOM_CRITICAL_SECTION_LEAVE();
5719 }
5720
hri_sercomusart_get_STATUS_BUFOVF_bit(const void * const hw)5721 static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
5722 {
5723 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
5724 }
5725
hri_sercomusart_clear_STATUS_BUFOVF_bit(const void * const hw)5726 static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
5727 {
5728 SERCOM_CRITICAL_SECTION_ENTER();
5729 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
5730 SERCOM_CRITICAL_SECTION_LEAVE();
5731 }
5732
hri_sercomusart_get_STATUS_CTS_bit(const void * const hw)5733 static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
5734 {
5735 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
5736 }
5737
hri_sercomusart_clear_STATUS_CTS_bit(const void * const hw)5738 static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
5739 {
5740 SERCOM_CRITICAL_SECTION_ENTER();
5741 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
5742 SERCOM_CRITICAL_SECTION_LEAVE();
5743 }
5744
hri_sercomusart_get_STATUS_ISF_bit(const void * const hw)5745 static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
5746 {
5747 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
5748 }
5749
hri_sercomusart_clear_STATUS_ISF_bit(const void * const hw)5750 static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
5751 {
5752 SERCOM_CRITICAL_SECTION_ENTER();
5753 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
5754 SERCOM_CRITICAL_SECTION_LEAVE();
5755 }
5756
hri_sercomusart_get_STATUS_COLL_bit(const void * const hw)5757 static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
5758 {
5759 return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
5760 }
5761
hri_sercomusart_clear_STATUS_COLL_bit(const void * const hw)5762 static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
5763 {
5764 SERCOM_CRITICAL_SECTION_ENTER();
5765 ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
5766 SERCOM_CRITICAL_SECTION_LEAVE();
5767 }
5768
hri_sercomusart_get_STATUS_reg(const void * const hw,hri_sercomusart_status_reg_t mask)5769 static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw,
5770 hri_sercomusart_status_reg_t mask)
5771 {
5772 uint16_t tmp;
5773 tmp = ((Sercom *)hw)->USART.STATUS.reg;
5774 tmp &= mask;
5775 return tmp;
5776 }
5777
hri_sercomusart_clear_STATUS_reg(const void * const hw,hri_sercomusart_status_reg_t mask)5778 static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
5779 {
5780 SERCOM_CRITICAL_SECTION_ENTER();
5781 ((Sercom *)hw)->USART.STATUS.reg = mask;
5782 SERCOM_CRITICAL_SECTION_LEAVE();
5783 }
5784
hri_sercomusart_read_STATUS_reg(const void * const hw)5785 static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
5786 {
5787 return ((Sercom *)hw)->USART.STATUS.reg;
5788 }
5789
hri_sercomi2cs_set_INTEN_PREC_bit(const void * const hw)5790 static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
5791 {
5792 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
5793 }
5794
hri_sercomi2cs_get_INTEN_PREC_bit(const void * const hw)5795 static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
5796 {
5797 return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
5798 }
5799
hri_sercomi2cs_write_INTEN_PREC_bit(const void * const hw,bool value)5800 static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
5801 {
5802 if (value == 0x0) {
5803 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
5804 } else {
5805 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
5806 }
5807 }
5808
hri_sercomi2cs_clear_INTEN_PREC_bit(const void * const hw)5809 static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
5810 {
5811 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
5812 }
5813
hri_sercomi2cs_set_INTEN_AMATCH_bit(const void * const hw)5814 static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
5815 {
5816 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
5817 }
5818
hri_sercomi2cs_get_INTEN_AMATCH_bit(const void * const hw)5819 static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
5820 {
5821 return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
5822 }
5823
hri_sercomi2cs_write_INTEN_AMATCH_bit(const void * const hw,bool value)5824 static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
5825 {
5826 if (value == 0x0) {
5827 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
5828 } else {
5829 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
5830 }
5831 }
5832
hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void * const hw)5833 static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
5834 {
5835 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
5836 }
5837
hri_sercomi2cs_set_INTEN_DRDY_bit(const void * const hw)5838 static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
5839 {
5840 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
5841 }
5842
hri_sercomi2cs_get_INTEN_DRDY_bit(const void * const hw)5843 static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
5844 {
5845 return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
5846 }
5847
hri_sercomi2cs_write_INTEN_DRDY_bit(const void * const hw,bool value)5848 static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
5849 {
5850 if (value == 0x0) {
5851 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
5852 } else {
5853 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
5854 }
5855 }
5856
hri_sercomi2cs_clear_INTEN_DRDY_bit(const void * const hw)5857 static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
5858 {
5859 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
5860 }
5861
hri_sercomi2cs_set_INTEN_ERROR_bit(const void * const hw)5862 static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
5863 {
5864 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
5865 }
5866
hri_sercomi2cs_get_INTEN_ERROR_bit(const void * const hw)5867 static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
5868 {
5869 return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
5870 }
5871
hri_sercomi2cs_write_INTEN_ERROR_bit(const void * const hw,bool value)5872 static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
5873 {
5874 if (value == 0x0) {
5875 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
5876 } else {
5877 ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
5878 }
5879 }
5880
hri_sercomi2cs_clear_INTEN_ERROR_bit(const void * const hw)5881 static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
5882 {
5883 ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
5884 }
5885
hri_sercomi2cs_set_INTEN_reg(const void * const hw,hri_sercomi2cs_intenset_reg_t mask)5886 static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
5887 {
5888 ((Sercom *)hw)->I2CS.INTENSET.reg = mask;
5889 }
5890
hri_sercomi2cs_get_INTEN_reg(const void * const hw,hri_sercomi2cs_intenset_reg_t mask)5891 static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw,
5892 hri_sercomi2cs_intenset_reg_t mask)
5893 {
5894 uint8_t tmp;
5895 tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
5896 tmp &= mask;
5897 return tmp;
5898 }
5899
hri_sercomi2cs_read_INTEN_reg(const void * const hw)5900 static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
5901 {
5902 return ((Sercom *)hw)->I2CS.INTENSET.reg;
5903 }
5904
hri_sercomi2cs_write_INTEN_reg(const void * const hw,hri_sercomi2cs_intenset_reg_t data)5905 static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
5906 {
5907 ((Sercom *)hw)->I2CS.INTENSET.reg = data;
5908 ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
5909 }
5910
hri_sercomi2cs_clear_INTEN_reg(const void * const hw,hri_sercomi2cs_intenset_reg_t mask)5911 static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
5912 {
5913 ((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
5914 }
5915
hri_sercomi2cs_get_INTFLAG_PREC_bit(const void * const hw)5916 static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
5917 {
5918 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
5919 }
5920
hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void * const hw)5921 static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
5922 {
5923 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
5924 }
5925
hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void * const hw)5926 static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
5927 {
5928 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
5929 }
5930
hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void * const hw)5931 static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
5932 {
5933 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
5934 }
5935
hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void * const hw)5936 static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
5937 {
5938 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
5939 }
5940
hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void * const hw)5941 static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
5942 {
5943 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
5944 }
5945
hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void * const hw)5946 static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
5947 {
5948 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
5949 }
5950
hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void * const hw)5951 static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
5952 {
5953 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
5954 }
5955
hri_sercomi2cs_get_interrupt_PREC_bit(const void * const hw)5956 static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
5957 {
5958 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
5959 }
5960
hri_sercomi2cs_clear_interrupt_PREC_bit(const void * const hw)5961 static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
5962 {
5963 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
5964 }
5965
hri_sercomi2cs_get_interrupt_AMATCH_bit(const void * const hw)5966 static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
5967 {
5968 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
5969 }
5970
hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void * const hw)5971 static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
5972 {
5973 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
5974 }
5975
hri_sercomi2cs_get_interrupt_DRDY_bit(const void * const hw)5976 static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
5977 {
5978 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
5979 }
5980
hri_sercomi2cs_clear_interrupt_DRDY_bit(const void * const hw)5981 static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
5982 {
5983 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
5984 }
5985
hri_sercomi2cs_get_interrupt_ERROR_bit(const void * const hw)5986 static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
5987 {
5988 return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
5989 }
5990
hri_sercomi2cs_clear_interrupt_ERROR_bit(const void * const hw)5991 static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
5992 {
5993 ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
5994 }
5995
hri_sercomi2cs_get_INTFLAG_reg(const void * const hw,hri_sercomi2cs_intflag_reg_t mask)5996 static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw,
5997 hri_sercomi2cs_intflag_reg_t mask)
5998 {
5999 uint8_t tmp;
6000 tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
6001 tmp &= mask;
6002 return tmp;
6003 }
6004
hri_sercomi2cs_read_INTFLAG_reg(const void * const hw)6005 static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
6006 {
6007 return ((Sercom *)hw)->I2CS.INTFLAG.reg;
6008 }
6009
hri_sercomi2cs_clear_INTFLAG_reg(const void * const hw,hri_sercomi2cs_intflag_reg_t mask)6010 static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
6011 {
6012 ((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
6013 }
6014
hri_sercomi2cs_set_CTRLA_SWRST_bit(const void * const hw)6015 static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
6016 {
6017 SERCOM_CRITICAL_SECTION_ENTER();
6018 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
6019 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
6020 SERCOM_CRITICAL_SECTION_LEAVE();
6021 }
6022
hri_sercomi2cs_get_CTRLA_SWRST_bit(const void * const hw)6023 static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
6024 {
6025 uint32_t tmp;
6026 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
6027 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6028 tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
6029 return (bool)tmp;
6030 }
6031
hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void * const hw)6032 static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
6033 {
6034 SERCOM_CRITICAL_SECTION_ENTER();
6035 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
6036 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
6037 SERCOM_CRITICAL_SECTION_LEAVE();
6038 }
6039
hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void * const hw)6040 static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
6041 {
6042 uint32_t tmp;
6043 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
6044 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6045 tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
6046 return (bool)tmp;
6047 }
6048
hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void * const hw,bool value)6049 static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
6050 {
6051 uint32_t tmp;
6052 SERCOM_CRITICAL_SECTION_ENTER();
6053 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
6054 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6055 tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
6056 tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
6057 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6058 SERCOM_CRITICAL_SECTION_LEAVE();
6059 }
6060
hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void * const hw)6061 static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
6062 {
6063 SERCOM_CRITICAL_SECTION_ENTER();
6064 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
6065 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
6066 SERCOM_CRITICAL_SECTION_LEAVE();
6067 }
6068
hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void * const hw)6069 static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
6070 {
6071 SERCOM_CRITICAL_SECTION_ENTER();
6072 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
6073 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
6074 SERCOM_CRITICAL_SECTION_LEAVE();
6075 }
6076
hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void * const hw)6077 static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
6078 {
6079 SERCOM_CRITICAL_SECTION_ENTER();
6080 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6081 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
6082 SERCOM_CRITICAL_SECTION_LEAVE();
6083 }
6084
hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void * const hw)6085 static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
6086 {
6087 uint32_t tmp;
6088 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6089 tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
6090 return (bool)tmp;
6091 }
6092
hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)6093 static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
6094 {
6095 uint32_t tmp;
6096 SERCOM_CRITICAL_SECTION_ENTER();
6097 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6098 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6099 tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
6100 tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
6101 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6102 SERCOM_CRITICAL_SECTION_LEAVE();
6103 }
6104
hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void * const hw)6105 static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
6106 {
6107 SERCOM_CRITICAL_SECTION_ENTER();
6108 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6109 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
6110 SERCOM_CRITICAL_SECTION_LEAVE();
6111 }
6112
hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)6113 static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
6114 {
6115 SERCOM_CRITICAL_SECTION_ENTER();
6116 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6117 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
6118 SERCOM_CRITICAL_SECTION_LEAVE();
6119 }
6120
hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void * const hw)6121 static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
6122 {
6123 SERCOM_CRITICAL_SECTION_ENTER();
6124 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6125 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
6126 SERCOM_CRITICAL_SECTION_LEAVE();
6127 }
6128
hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void * const hw)6129 static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
6130 {
6131 uint32_t tmp;
6132 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6133 tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
6134 return (bool)tmp;
6135 }
6136
hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void * const hw,bool value)6137 static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
6138 {
6139 uint32_t tmp;
6140 SERCOM_CRITICAL_SECTION_ENTER();
6141 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6142 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6143 tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
6144 tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
6145 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6146 SERCOM_CRITICAL_SECTION_LEAVE();
6147 }
6148
hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void * const hw)6149 static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
6150 {
6151 SERCOM_CRITICAL_SECTION_ENTER();
6152 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6153 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
6154 SERCOM_CRITICAL_SECTION_LEAVE();
6155 }
6156
hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void * const hw)6157 static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
6158 {
6159 SERCOM_CRITICAL_SECTION_ENTER();
6160 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6161 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
6162 SERCOM_CRITICAL_SECTION_LEAVE();
6163 }
6164
hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void * const hw)6165 static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
6166 {
6167 SERCOM_CRITICAL_SECTION_ENTER();
6168 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6169 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
6170 SERCOM_CRITICAL_SECTION_LEAVE();
6171 }
6172
hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void * const hw)6173 static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
6174 {
6175 uint32_t tmp;
6176 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6177 tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
6178 return (bool)tmp;
6179 }
6180
hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void * const hw,bool value)6181 static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
6182 {
6183 uint32_t tmp;
6184 SERCOM_CRITICAL_SECTION_ENTER();
6185 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6186 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6187 tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
6188 tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
6189 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6190 SERCOM_CRITICAL_SECTION_LEAVE();
6191 }
6192
hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void * const hw)6193 static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
6194 {
6195 SERCOM_CRITICAL_SECTION_ENTER();
6196 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6197 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
6198 SERCOM_CRITICAL_SECTION_LEAVE();
6199 }
6200
hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void * const hw)6201 static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
6202 {
6203 SERCOM_CRITICAL_SECTION_ENTER();
6204 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6205 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
6206 SERCOM_CRITICAL_SECTION_LEAVE();
6207 }
6208
hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void * const hw)6209 static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
6210 {
6211 SERCOM_CRITICAL_SECTION_ENTER();
6212 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6213 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
6214 SERCOM_CRITICAL_SECTION_LEAVE();
6215 }
6216
hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void * const hw)6217 static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
6218 {
6219 uint32_t tmp;
6220 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6221 tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
6222 return (bool)tmp;
6223 }
6224
hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void * const hw,bool value)6225 static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
6226 {
6227 uint32_t tmp;
6228 SERCOM_CRITICAL_SECTION_ENTER();
6229 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6230 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6231 tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
6232 tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
6233 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6234 SERCOM_CRITICAL_SECTION_LEAVE();
6235 }
6236
hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void * const hw)6237 static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
6238 {
6239 SERCOM_CRITICAL_SECTION_ENTER();
6240 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6241 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
6242 SERCOM_CRITICAL_SECTION_LEAVE();
6243 }
6244
hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void * const hw)6245 static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
6246 {
6247 SERCOM_CRITICAL_SECTION_ENTER();
6248 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6249 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
6250 SERCOM_CRITICAL_SECTION_LEAVE();
6251 }
6252
hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void * const hw)6253 static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
6254 {
6255 SERCOM_CRITICAL_SECTION_ENTER();
6256 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6257 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
6258 SERCOM_CRITICAL_SECTION_LEAVE();
6259 }
6260
hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void * const hw)6261 static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
6262 {
6263 uint32_t tmp;
6264 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6265 tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
6266 return (bool)tmp;
6267 }
6268
hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void * const hw,bool value)6269 static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
6270 {
6271 uint32_t tmp;
6272 SERCOM_CRITICAL_SECTION_ENTER();
6273 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6274 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6275 tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
6276 tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
6277 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6278 SERCOM_CRITICAL_SECTION_LEAVE();
6279 }
6280
hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void * const hw)6281 static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
6282 {
6283 SERCOM_CRITICAL_SECTION_ENTER();
6284 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6285 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
6286 SERCOM_CRITICAL_SECTION_LEAVE();
6287 }
6288
hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void * const hw)6289 static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
6290 {
6291 SERCOM_CRITICAL_SECTION_ENTER();
6292 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6293 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
6294 SERCOM_CRITICAL_SECTION_LEAVE();
6295 }
6296
hri_sercomi2cs_set_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6297 static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6298 {
6299 SERCOM_CRITICAL_SECTION_ENTER();
6300 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6301 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
6302 SERCOM_CRITICAL_SECTION_LEAVE();
6303 }
6304
hri_sercomi2cs_get_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6305 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw,
6306 hri_sercomi2cs_ctrla_reg_t mask)
6307 {
6308 uint32_t tmp;
6309 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6310 tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
6311 return tmp;
6312 }
6313
hri_sercomi2cs_write_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t data)6314 static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
6315 {
6316 uint32_t tmp;
6317 SERCOM_CRITICAL_SECTION_ENTER();
6318 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6319 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6320 tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
6321 tmp |= SERCOM_I2CS_CTRLA_MODE(data);
6322 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6323 SERCOM_CRITICAL_SECTION_LEAVE();
6324 }
6325
hri_sercomi2cs_clear_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6326 static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6327 {
6328 SERCOM_CRITICAL_SECTION_ENTER();
6329 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6330 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
6331 SERCOM_CRITICAL_SECTION_LEAVE();
6332 }
6333
hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6334 static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6335 {
6336 SERCOM_CRITICAL_SECTION_ENTER();
6337 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6338 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
6339 SERCOM_CRITICAL_SECTION_LEAVE();
6340 }
6341
hri_sercomi2cs_read_CTRLA_MODE_bf(const void * const hw)6342 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
6343 {
6344 uint32_t tmp;
6345 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6346 tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
6347 return tmp;
6348 }
6349
hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6350 static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6351 {
6352 SERCOM_CRITICAL_SECTION_ENTER();
6353 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6354 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
6355 SERCOM_CRITICAL_SECTION_LEAVE();
6356 }
6357
hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6358 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw,
6359 hri_sercomi2cs_ctrla_reg_t mask)
6360 {
6361 uint32_t tmp;
6362 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6363 tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
6364 return tmp;
6365 }
6366
hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t data)6367 static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
6368 {
6369 uint32_t tmp;
6370 SERCOM_CRITICAL_SECTION_ENTER();
6371 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6372 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6373 tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
6374 tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
6375 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6376 SERCOM_CRITICAL_SECTION_LEAVE();
6377 }
6378
hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6379 static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6380 {
6381 SERCOM_CRITICAL_SECTION_ENTER();
6382 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6383 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
6384 SERCOM_CRITICAL_SECTION_LEAVE();
6385 }
6386
hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6387 static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6388 {
6389 SERCOM_CRITICAL_SECTION_ENTER();
6390 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6391 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
6392 SERCOM_CRITICAL_SECTION_LEAVE();
6393 }
6394
hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void * const hw)6395 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
6396 {
6397 uint32_t tmp;
6398 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6399 tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
6400 return tmp;
6401 }
6402
hri_sercomi2cs_set_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6403 static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6404 {
6405 SERCOM_CRITICAL_SECTION_ENTER();
6406 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6407 ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
6408 SERCOM_CRITICAL_SECTION_LEAVE();
6409 }
6410
hri_sercomi2cs_get_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6411 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw,
6412 hri_sercomi2cs_ctrla_reg_t mask)
6413 {
6414 uint32_t tmp;
6415 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6416 tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
6417 return tmp;
6418 }
6419
hri_sercomi2cs_write_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t data)6420 static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
6421 {
6422 uint32_t tmp;
6423 SERCOM_CRITICAL_SECTION_ENTER();
6424 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6425 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6426 tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
6427 tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
6428 ((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
6429 SERCOM_CRITICAL_SECTION_LEAVE();
6430 }
6431
hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6432 static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6433 {
6434 SERCOM_CRITICAL_SECTION_ENTER();
6435 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6436 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
6437 SERCOM_CRITICAL_SECTION_LEAVE();
6438 }
6439
hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6440 static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6441 {
6442 SERCOM_CRITICAL_SECTION_ENTER();
6443 hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
6444 ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
6445 SERCOM_CRITICAL_SECTION_LEAVE();
6446 }
6447
hri_sercomi2cs_read_CTRLA_SPEED_bf(const void * const hw)6448 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
6449 {
6450 uint32_t tmp;
6451 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6452 tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
6453 return tmp;
6454 }
6455
hri_sercomi2cs_set_CTRLA_reg(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6456 static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6457 {
6458 SERCOM_CRITICAL_SECTION_ENTER();
6459 ((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
6460 SERCOM_CRITICAL_SECTION_LEAVE();
6461 }
6462
hri_sercomi2cs_get_CTRLA_reg(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6463 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw,
6464 hri_sercomi2cs_ctrla_reg_t mask)
6465 {
6466 uint32_t tmp;
6467 tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
6468 tmp &= mask;
6469 return tmp;
6470 }
6471
hri_sercomi2cs_write_CTRLA_reg(const void * const hw,hri_sercomi2cs_ctrla_reg_t data)6472 static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
6473 {
6474 SERCOM_CRITICAL_SECTION_ENTER();
6475 ((Sercom *)hw)->I2CS.CTRLA.reg = data;
6476 SERCOM_CRITICAL_SECTION_LEAVE();
6477 }
6478
hri_sercomi2cs_clear_CTRLA_reg(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6479 static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6480 {
6481 SERCOM_CRITICAL_SECTION_ENTER();
6482 ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
6483 SERCOM_CRITICAL_SECTION_LEAVE();
6484 }
6485
hri_sercomi2cs_toggle_CTRLA_reg(const void * const hw,hri_sercomi2cs_ctrla_reg_t mask)6486 static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
6487 {
6488 SERCOM_CRITICAL_SECTION_ENTER();
6489 ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
6490 SERCOM_CRITICAL_SECTION_LEAVE();
6491 }
6492
hri_sercomi2cs_read_CTRLA_reg(const void * const hw)6493 static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
6494 {
6495 return ((Sercom *)hw)->I2CS.CTRLA.reg;
6496 }
6497
hri_sercomi2cs_set_CTRLB_SMEN_bit(const void * const hw)6498 static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
6499 {
6500 SERCOM_CRITICAL_SECTION_ENTER();
6501 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
6502 SERCOM_CRITICAL_SECTION_LEAVE();
6503 }
6504
hri_sercomi2cs_get_CTRLB_SMEN_bit(const void * const hw)6505 static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
6506 {
6507 uint32_t tmp;
6508 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6509 tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
6510 return (bool)tmp;
6511 }
6512
hri_sercomi2cs_write_CTRLB_SMEN_bit(const void * const hw,bool value)6513 static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
6514 {
6515 uint32_t tmp;
6516 SERCOM_CRITICAL_SECTION_ENTER();
6517 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6518 tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
6519 tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
6520 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6521 SERCOM_CRITICAL_SECTION_LEAVE();
6522 }
6523
hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void * const hw)6524 static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
6525 {
6526 SERCOM_CRITICAL_SECTION_ENTER();
6527 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
6528 SERCOM_CRITICAL_SECTION_LEAVE();
6529 }
6530
hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void * const hw)6531 static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
6532 {
6533 SERCOM_CRITICAL_SECTION_ENTER();
6534 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
6535 SERCOM_CRITICAL_SECTION_LEAVE();
6536 }
6537
hri_sercomi2cs_set_CTRLB_GCMD_bit(const void * const hw)6538 static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
6539 {
6540 SERCOM_CRITICAL_SECTION_ENTER();
6541 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
6542 SERCOM_CRITICAL_SECTION_LEAVE();
6543 }
6544
hri_sercomi2cs_get_CTRLB_GCMD_bit(const void * const hw)6545 static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
6546 {
6547 uint32_t tmp;
6548 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6549 tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
6550 return (bool)tmp;
6551 }
6552
hri_sercomi2cs_write_CTRLB_GCMD_bit(const void * const hw,bool value)6553 static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
6554 {
6555 uint32_t tmp;
6556 SERCOM_CRITICAL_SECTION_ENTER();
6557 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6558 tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
6559 tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
6560 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6561 SERCOM_CRITICAL_SECTION_LEAVE();
6562 }
6563
hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void * const hw)6564 static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
6565 {
6566 SERCOM_CRITICAL_SECTION_ENTER();
6567 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
6568 SERCOM_CRITICAL_SECTION_LEAVE();
6569 }
6570
hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void * const hw)6571 static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
6572 {
6573 SERCOM_CRITICAL_SECTION_ENTER();
6574 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
6575 SERCOM_CRITICAL_SECTION_LEAVE();
6576 }
6577
hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void * const hw)6578 static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
6579 {
6580 SERCOM_CRITICAL_SECTION_ENTER();
6581 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
6582 SERCOM_CRITICAL_SECTION_LEAVE();
6583 }
6584
hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void * const hw)6585 static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
6586 {
6587 uint32_t tmp;
6588 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6589 tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
6590 return (bool)tmp;
6591 }
6592
hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void * const hw,bool value)6593 static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
6594 {
6595 uint32_t tmp;
6596 SERCOM_CRITICAL_SECTION_ENTER();
6597 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6598 tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
6599 tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
6600 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6601 SERCOM_CRITICAL_SECTION_LEAVE();
6602 }
6603
hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void * const hw)6604 static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
6605 {
6606 SERCOM_CRITICAL_SECTION_ENTER();
6607 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
6608 SERCOM_CRITICAL_SECTION_LEAVE();
6609 }
6610
hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void * const hw)6611 static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
6612 {
6613 SERCOM_CRITICAL_SECTION_ENTER();
6614 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
6615 SERCOM_CRITICAL_SECTION_LEAVE();
6616 }
6617
hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void * const hw)6618 static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
6619 {
6620 SERCOM_CRITICAL_SECTION_ENTER();
6621 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
6622 SERCOM_CRITICAL_SECTION_LEAVE();
6623 }
6624
hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void * const hw)6625 static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
6626 {
6627 uint32_t tmp;
6628 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6629 tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
6630 return (bool)tmp;
6631 }
6632
hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void * const hw,bool value)6633 static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
6634 {
6635 uint32_t tmp;
6636 SERCOM_CRITICAL_SECTION_ENTER();
6637 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6638 tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
6639 tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
6640 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6641 SERCOM_CRITICAL_SECTION_LEAVE();
6642 }
6643
hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void * const hw)6644 static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
6645 {
6646 SERCOM_CRITICAL_SECTION_ENTER();
6647 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
6648 SERCOM_CRITICAL_SECTION_LEAVE();
6649 }
6650
hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void * const hw)6651 static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
6652 {
6653 SERCOM_CRITICAL_SECTION_ENTER();
6654 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
6655 SERCOM_CRITICAL_SECTION_LEAVE();
6656 }
6657
hri_sercomi2cs_set_CTRLB_AMODE_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6658 static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6659 {
6660 SERCOM_CRITICAL_SECTION_ENTER();
6661 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
6662 SERCOM_CRITICAL_SECTION_LEAVE();
6663 }
6664
hri_sercomi2cs_get_CTRLB_AMODE_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6665 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw,
6666 hri_sercomi2cs_ctrlb_reg_t mask)
6667 {
6668 uint32_t tmp;
6669 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6670 tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
6671 return tmp;
6672 }
6673
hri_sercomi2cs_write_CTRLB_AMODE_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t data)6674 static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
6675 {
6676 uint32_t tmp;
6677 SERCOM_CRITICAL_SECTION_ENTER();
6678 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6679 tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
6680 tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
6681 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6682 SERCOM_CRITICAL_SECTION_LEAVE();
6683 }
6684
hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6685 static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6686 {
6687 SERCOM_CRITICAL_SECTION_ENTER();
6688 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
6689 SERCOM_CRITICAL_SECTION_LEAVE();
6690 }
6691
hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6692 static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6693 {
6694 SERCOM_CRITICAL_SECTION_ENTER();
6695 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
6696 SERCOM_CRITICAL_SECTION_LEAVE();
6697 }
6698
hri_sercomi2cs_read_CTRLB_AMODE_bf(const void * const hw)6699 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
6700 {
6701 uint32_t tmp;
6702 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6703 tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
6704 return tmp;
6705 }
6706
hri_sercomi2cs_set_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6707 static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6708 {
6709 SERCOM_CRITICAL_SECTION_ENTER();
6710 ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
6711 SERCOM_CRITICAL_SECTION_LEAVE();
6712 }
6713
hri_sercomi2cs_get_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6714 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw,
6715 hri_sercomi2cs_ctrlb_reg_t mask)
6716 {
6717 uint32_t tmp;
6718 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6719 tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
6720 return tmp;
6721 }
6722
hri_sercomi2cs_write_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t data)6723 static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
6724 {
6725 uint32_t tmp;
6726 SERCOM_CRITICAL_SECTION_ENTER();
6727 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6728 tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
6729 tmp |= SERCOM_I2CS_CTRLB_CMD(data);
6730 ((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
6731 SERCOM_CRITICAL_SECTION_LEAVE();
6732 }
6733
hri_sercomi2cs_clear_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6734 static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6735 {
6736 SERCOM_CRITICAL_SECTION_ENTER();
6737 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
6738 SERCOM_CRITICAL_SECTION_LEAVE();
6739 }
6740
hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6741 static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6742 {
6743 SERCOM_CRITICAL_SECTION_ENTER();
6744 ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
6745 SERCOM_CRITICAL_SECTION_LEAVE();
6746 }
6747
hri_sercomi2cs_read_CTRLB_CMD_bf(const void * const hw)6748 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
6749 {
6750 uint32_t tmp;
6751 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6752 tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
6753 return tmp;
6754 }
6755
hri_sercomi2cs_set_CTRLB_reg(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6756 static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6757 {
6758 SERCOM_CRITICAL_SECTION_ENTER();
6759 ((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
6760 SERCOM_CRITICAL_SECTION_LEAVE();
6761 }
6762
hri_sercomi2cs_get_CTRLB_reg(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6763 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw,
6764 hri_sercomi2cs_ctrlb_reg_t mask)
6765 {
6766 uint32_t tmp;
6767 tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
6768 tmp &= mask;
6769 return tmp;
6770 }
6771
hri_sercomi2cs_write_CTRLB_reg(const void * const hw,hri_sercomi2cs_ctrlb_reg_t data)6772 static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
6773 {
6774 SERCOM_CRITICAL_SECTION_ENTER();
6775 ((Sercom *)hw)->I2CS.CTRLB.reg = data;
6776 SERCOM_CRITICAL_SECTION_LEAVE();
6777 }
6778
hri_sercomi2cs_clear_CTRLB_reg(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6779 static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6780 {
6781 SERCOM_CRITICAL_SECTION_ENTER();
6782 ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
6783 SERCOM_CRITICAL_SECTION_LEAVE();
6784 }
6785
hri_sercomi2cs_toggle_CTRLB_reg(const void * const hw,hri_sercomi2cs_ctrlb_reg_t mask)6786 static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
6787 {
6788 SERCOM_CRITICAL_SECTION_ENTER();
6789 ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
6790 SERCOM_CRITICAL_SECTION_LEAVE();
6791 }
6792
hri_sercomi2cs_read_CTRLB_reg(const void * const hw)6793 static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
6794 {
6795 return ((Sercom *)hw)->I2CS.CTRLB.reg;
6796 }
6797
hri_sercomi2cs_set_ADDR_GENCEN_bit(const void * const hw)6798 static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
6799 {
6800 SERCOM_CRITICAL_SECTION_ENTER();
6801 ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
6802 SERCOM_CRITICAL_SECTION_LEAVE();
6803 }
6804
hri_sercomi2cs_get_ADDR_GENCEN_bit(const void * const hw)6805 static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
6806 {
6807 uint32_t tmp;
6808 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6809 tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
6810 return (bool)tmp;
6811 }
6812
hri_sercomi2cs_write_ADDR_GENCEN_bit(const void * const hw,bool value)6813 static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
6814 {
6815 uint32_t tmp;
6816 SERCOM_CRITICAL_SECTION_ENTER();
6817 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6818 tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
6819 tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
6820 ((Sercom *)hw)->I2CS.ADDR.reg = tmp;
6821 SERCOM_CRITICAL_SECTION_LEAVE();
6822 }
6823
hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void * const hw)6824 static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
6825 {
6826 SERCOM_CRITICAL_SECTION_ENTER();
6827 ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
6828 SERCOM_CRITICAL_SECTION_LEAVE();
6829 }
6830
hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void * const hw)6831 static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
6832 {
6833 SERCOM_CRITICAL_SECTION_ENTER();
6834 ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
6835 SERCOM_CRITICAL_SECTION_LEAVE();
6836 }
6837
hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void * const hw)6838 static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
6839 {
6840 SERCOM_CRITICAL_SECTION_ENTER();
6841 ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
6842 SERCOM_CRITICAL_SECTION_LEAVE();
6843 }
6844
hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void * const hw)6845 static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
6846 {
6847 uint32_t tmp;
6848 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6849 tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
6850 return (bool)tmp;
6851 }
6852
hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void * const hw,bool value)6853 static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
6854 {
6855 uint32_t tmp;
6856 SERCOM_CRITICAL_SECTION_ENTER();
6857 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6858 tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
6859 tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
6860 ((Sercom *)hw)->I2CS.ADDR.reg = tmp;
6861 SERCOM_CRITICAL_SECTION_LEAVE();
6862 }
6863
hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void * const hw)6864 static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
6865 {
6866 SERCOM_CRITICAL_SECTION_ENTER();
6867 ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
6868 SERCOM_CRITICAL_SECTION_LEAVE();
6869 }
6870
hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void * const hw)6871 static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
6872 {
6873 SERCOM_CRITICAL_SECTION_ENTER();
6874 ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
6875 SERCOM_CRITICAL_SECTION_LEAVE();
6876 }
6877
hri_sercomi2cs_set_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6878 static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6879 {
6880 SERCOM_CRITICAL_SECTION_ENTER();
6881 ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
6882 SERCOM_CRITICAL_SECTION_LEAVE();
6883 }
6884
hri_sercomi2cs_get_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6885 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw,
6886 hri_sercomi2cs_addr_reg_t mask)
6887 {
6888 uint32_t tmp;
6889 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6890 tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
6891 return tmp;
6892 }
6893
hri_sercomi2cs_write_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cs_addr_reg_t data)6894 static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
6895 {
6896 uint32_t tmp;
6897 SERCOM_CRITICAL_SECTION_ENTER();
6898 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6899 tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
6900 tmp |= SERCOM_I2CS_ADDR_ADDR(data);
6901 ((Sercom *)hw)->I2CS.ADDR.reg = tmp;
6902 SERCOM_CRITICAL_SECTION_LEAVE();
6903 }
6904
hri_sercomi2cs_clear_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6905 static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6906 {
6907 SERCOM_CRITICAL_SECTION_ENTER();
6908 ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
6909 SERCOM_CRITICAL_SECTION_LEAVE();
6910 }
6911
hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6912 static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6913 {
6914 SERCOM_CRITICAL_SECTION_ENTER();
6915 ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
6916 SERCOM_CRITICAL_SECTION_LEAVE();
6917 }
6918
hri_sercomi2cs_read_ADDR_ADDR_bf(const void * const hw)6919 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
6920 {
6921 uint32_t tmp;
6922 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6923 tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
6924 return tmp;
6925 }
6926
hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6927 static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6928 {
6929 SERCOM_CRITICAL_SECTION_ENTER();
6930 ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
6931 SERCOM_CRITICAL_SECTION_LEAVE();
6932 }
6933
hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6934 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw,
6935 hri_sercomi2cs_addr_reg_t mask)
6936 {
6937 uint32_t tmp;
6938 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6939 tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
6940 return tmp;
6941 }
6942
hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomi2cs_addr_reg_t data)6943 static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
6944 {
6945 uint32_t tmp;
6946 SERCOM_CRITICAL_SECTION_ENTER();
6947 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6948 tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
6949 tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
6950 ((Sercom *)hw)->I2CS.ADDR.reg = tmp;
6951 SERCOM_CRITICAL_SECTION_LEAVE();
6952 }
6953
hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6954 static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6955 {
6956 SERCOM_CRITICAL_SECTION_ENTER();
6957 ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
6958 SERCOM_CRITICAL_SECTION_LEAVE();
6959 }
6960
hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6961 static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6962 {
6963 SERCOM_CRITICAL_SECTION_ENTER();
6964 ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
6965 SERCOM_CRITICAL_SECTION_LEAVE();
6966 }
6967
hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void * const hw)6968 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
6969 {
6970 uint32_t tmp;
6971 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6972 tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
6973 return tmp;
6974 }
6975
hri_sercomi2cs_set_ADDR_reg(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6976 static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
6977 {
6978 SERCOM_CRITICAL_SECTION_ENTER();
6979 ((Sercom *)hw)->I2CS.ADDR.reg |= mask;
6980 SERCOM_CRITICAL_SECTION_LEAVE();
6981 }
6982
hri_sercomi2cs_get_ADDR_reg(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6983 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw,
6984 hri_sercomi2cs_addr_reg_t mask)
6985 {
6986 uint32_t tmp;
6987 tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
6988 tmp &= mask;
6989 return tmp;
6990 }
6991
hri_sercomi2cs_write_ADDR_reg(const void * const hw,hri_sercomi2cs_addr_reg_t data)6992 static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
6993 {
6994 SERCOM_CRITICAL_SECTION_ENTER();
6995 ((Sercom *)hw)->I2CS.ADDR.reg = data;
6996 SERCOM_CRITICAL_SECTION_LEAVE();
6997 }
6998
hri_sercomi2cs_clear_ADDR_reg(const void * const hw,hri_sercomi2cs_addr_reg_t mask)6999 static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
7000 {
7001 SERCOM_CRITICAL_SECTION_ENTER();
7002 ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
7003 SERCOM_CRITICAL_SECTION_LEAVE();
7004 }
7005
hri_sercomi2cs_toggle_ADDR_reg(const void * const hw,hri_sercomi2cs_addr_reg_t mask)7006 static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
7007 {
7008 SERCOM_CRITICAL_SECTION_ENTER();
7009 ((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
7010 SERCOM_CRITICAL_SECTION_LEAVE();
7011 }
7012
hri_sercomi2cs_read_ADDR_reg(const void * const hw)7013 static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
7014 {
7015 return ((Sercom *)hw)->I2CS.ADDR.reg;
7016 }
7017
hri_sercomi2cs_read_DATA_reg(const void * const hw)7018 static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
7019 {
7020 return ((Sercom *)hw)->I2CS.DATA.reg;
7021 }
7022
hri_sercomi2cs_write_DATA_reg(const void * const hw,hri_sercomi2cs_data_reg_t data)7023 static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
7024 {
7025 SERCOM_CRITICAL_SECTION_ENTER();
7026 ((Sercom *)hw)->I2CS.DATA.reg = data;
7027 SERCOM_CRITICAL_SECTION_LEAVE();
7028 }
7029
hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void * const hw)7030 static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
7031 {
7032 return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
7033 }
7034
hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void * const hw)7035 static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
7036 {
7037 return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
7038 }
7039
hri_sercomi2cs_get_SYNCBUSY_reg(const void * const hw,hri_sercomi2cs_syncbusy_reg_t mask)7040 static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw,
7041 hri_sercomi2cs_syncbusy_reg_t mask)
7042 {
7043 uint32_t tmp;
7044 tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
7045 tmp &= mask;
7046 return tmp;
7047 }
7048
hri_sercomi2cs_read_SYNCBUSY_reg(const void * const hw)7049 static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
7050 {
7051 return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
7052 }
7053
hri_sercomi2cs_get_STATUS_BUSERR_bit(const void * const hw)7054 static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
7055 {
7056 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
7057 }
7058
hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void * const hw)7059 static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
7060 {
7061 SERCOM_CRITICAL_SECTION_ENTER();
7062 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
7063 SERCOM_CRITICAL_SECTION_LEAVE();
7064 }
7065
hri_sercomi2cs_get_STATUS_COLL_bit(const void * const hw)7066 static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
7067 {
7068 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
7069 }
7070
hri_sercomi2cs_clear_STATUS_COLL_bit(const void * const hw)7071 static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
7072 {
7073 SERCOM_CRITICAL_SECTION_ENTER();
7074 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
7075 SERCOM_CRITICAL_SECTION_LEAVE();
7076 }
7077
hri_sercomi2cs_get_STATUS_RXNACK_bit(const void * const hw)7078 static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
7079 {
7080 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
7081 }
7082
hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void * const hw)7083 static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
7084 {
7085 SERCOM_CRITICAL_SECTION_ENTER();
7086 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
7087 SERCOM_CRITICAL_SECTION_LEAVE();
7088 }
7089
hri_sercomi2cs_get_STATUS_DIR_bit(const void * const hw)7090 static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
7091 {
7092 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
7093 }
7094
hri_sercomi2cs_clear_STATUS_DIR_bit(const void * const hw)7095 static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
7096 {
7097 SERCOM_CRITICAL_SECTION_ENTER();
7098 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
7099 SERCOM_CRITICAL_SECTION_LEAVE();
7100 }
7101
hri_sercomi2cs_get_STATUS_SR_bit(const void * const hw)7102 static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
7103 {
7104 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
7105 }
7106
hri_sercomi2cs_clear_STATUS_SR_bit(const void * const hw)7107 static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
7108 {
7109 SERCOM_CRITICAL_SECTION_ENTER();
7110 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
7111 SERCOM_CRITICAL_SECTION_LEAVE();
7112 }
7113
hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void * const hw)7114 static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
7115 {
7116 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
7117 }
7118
hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void * const hw)7119 static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
7120 {
7121 SERCOM_CRITICAL_SECTION_ENTER();
7122 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
7123 SERCOM_CRITICAL_SECTION_LEAVE();
7124 }
7125
hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void * const hw)7126 static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
7127 {
7128 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
7129 }
7130
hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void * const hw)7131 static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
7132 {
7133 SERCOM_CRITICAL_SECTION_ENTER();
7134 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
7135 SERCOM_CRITICAL_SECTION_LEAVE();
7136 }
7137
hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void * const hw)7138 static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
7139 {
7140 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
7141 }
7142
hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void * const hw)7143 static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
7144 {
7145 SERCOM_CRITICAL_SECTION_ENTER();
7146 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
7147 SERCOM_CRITICAL_SECTION_LEAVE();
7148 }
7149
hri_sercomi2cs_get_STATUS_HS_bit(const void * const hw)7150 static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
7151 {
7152 return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
7153 }
7154
hri_sercomi2cs_clear_STATUS_HS_bit(const void * const hw)7155 static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
7156 {
7157 SERCOM_CRITICAL_SECTION_ENTER();
7158 ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
7159 SERCOM_CRITICAL_SECTION_LEAVE();
7160 }
7161
hri_sercomi2cs_get_STATUS_reg(const void * const hw,hri_sercomi2cs_status_reg_t mask)7162 static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw,
7163 hri_sercomi2cs_status_reg_t mask)
7164 {
7165 uint16_t tmp;
7166 tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
7167 tmp &= mask;
7168 return tmp;
7169 }
7170
hri_sercomi2cs_clear_STATUS_reg(const void * const hw,hri_sercomi2cs_status_reg_t mask)7171 static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
7172 {
7173 SERCOM_CRITICAL_SECTION_ENTER();
7174 ((Sercom *)hw)->I2CS.STATUS.reg = mask;
7175 SERCOM_CRITICAL_SECTION_LEAVE();
7176 }
7177
hri_sercomi2cs_read_STATUS_reg(const void * const hw)7178 static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
7179 {
7180 return ((Sercom *)hw)->I2CS.STATUS.reg;
7181 }
7182
7183 #ifdef __cplusplus
7184 }
7185 #endif
7186
7187 #endif /* _HRI_SERCOM_L21_H_INCLUDED */
7188 #endif /* _SAML21_SERCOM_COMPONENT_ */
7189
