1 /**
2 * \file
3 *
4 * \brief SAM RTC
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_RTC_COMPONENT_
44 #ifndef _HRI_RTC_L21_H_INCLUDED_
45 #define _HRI_RTC_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_RTC_CRITICAL_SECTIONS)
55 #define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define RTC_CRITICAL_SECTION_ENTER()
59 #define RTC_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_rtcmode0_ctrla_reg_t;
63 typedef uint16_t hri_rtcmode0_intenset_reg_t;
64 typedef uint16_t hri_rtcmode0_intflag_reg_t;
65 typedef uint16_t hri_rtcmode1_comp_reg_t;
66 typedef uint16_t hri_rtcmode1_count_reg_t;
67 typedef uint16_t hri_rtcmode1_ctrla_reg_t;
68 typedef uint16_t hri_rtcmode1_intenset_reg_t;
69 typedef uint16_t hri_rtcmode1_intflag_reg_t;
70 typedef uint16_t hri_rtcmode1_per_reg_t;
71 typedef uint16_t hri_rtcmode2_ctrla_reg_t;
72 typedef uint16_t hri_rtcmode2_intenset_reg_t;
73 typedef uint16_t hri_rtcmode2_intflag_reg_t;
74 typedef uint32_t hri_rtcalarm_alarm_reg_t;
75 typedef uint32_t hri_rtcmode0_comp_reg_t;
76 typedef uint32_t hri_rtcmode0_count_reg_t;
77 typedef uint32_t hri_rtcmode0_evctrl_reg_t;
78 typedef uint32_t hri_rtcmode0_gp_reg_t;
79 typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
80 typedef uint32_t hri_rtcmode1_evctrl_reg_t;
81 typedef uint32_t hri_rtcmode1_gp_reg_t;
82 typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
83 typedef uint32_t hri_rtcmode2_alarm_reg_t;
84 typedef uint32_t hri_rtcmode2_clock_reg_t;
85 typedef uint32_t hri_rtcmode2_evctrl_reg_t;
86 typedef uint32_t hri_rtcmode2_gp_reg_t;
87 typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
88 typedef uint8_t hri_rtcalarm_mask_reg_t;
89 typedef uint8_t hri_rtcmode0_dbgctrl_reg_t;
90 typedef uint8_t hri_rtcmode0_freqcorr_reg_t;
91 typedef uint8_t hri_rtcmode1_dbgctrl_reg_t;
92 typedef uint8_t hri_rtcmode1_freqcorr_reg_t;
93 typedef uint8_t hri_rtcmode2_dbgctrl_reg_t;
94 typedef uint8_t hri_rtcmode2_freqcorr_reg_t;
95 typedef uint8_t hri_rtcmode2_mask_reg_t;
96
hri_rtcmode0_wait_for_sync(const void * const hw,hri_rtcmode0_syncbusy_reg_t reg)97 static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
98 {
99 while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
100 };
101 }
102
hri_rtcmode0_is_syncing(const void * const hw,hri_rtcmode0_syncbusy_reg_t reg)103 static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
104 {
105 return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
106 }
107
hri_rtcmode1_wait_for_sync(const void * const hw,hri_rtcmode1_syncbusy_reg_t reg)108 static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
109 {
110 while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
111 };
112 }
113
hri_rtcmode1_is_syncing(const void * const hw,hri_rtcmode1_syncbusy_reg_t reg)114 static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
115 {
116 return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
117 }
118
hri_rtcmode2_wait_for_sync(const void * const hw,hri_rtcmode2_syncbusy_reg_t reg)119 static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
120 {
121 while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
122 };
123 }
124
hri_rtcmode2_is_syncing(const void * const hw,hri_rtcmode2_syncbusy_reg_t reg)125 static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
126 {
127 return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
128 }
129
hri_rtcalarm_set_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)130 static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
131 hri_rtcalarm_alarm_reg_t mask)
132 {
133 RTC_CRITICAL_SECTION_ENTER();
134 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
135 RTC_CRITICAL_SECTION_LEAVE();
136 }
137
hri_rtcalarm_get_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)138 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
139 hri_rtcalarm_alarm_reg_t mask)
140 {
141 uint32_t tmp;
142 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
143 tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
144 return tmp;
145 }
146
hri_rtcalarm_write_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)147 static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
148 hri_rtcalarm_alarm_reg_t data)
149 {
150 uint32_t tmp;
151 RTC_CRITICAL_SECTION_ENTER();
152 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
153 tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
154 tmp |= RTC_MODE2_ALARM_SECOND(data);
155 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
156 RTC_CRITICAL_SECTION_LEAVE();
157 }
158
hri_rtcalarm_clear_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)159 static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
160 hri_rtcalarm_alarm_reg_t mask)
161 {
162 RTC_CRITICAL_SECTION_ENTER();
163 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
164 RTC_CRITICAL_SECTION_LEAVE();
165 }
166
hri_rtcalarm_toggle_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)167 static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
168 hri_rtcalarm_alarm_reg_t mask)
169 {
170 RTC_CRITICAL_SECTION_ENTER();
171 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
172 RTC_CRITICAL_SECTION_LEAVE();
173 }
174
hri_rtcalarm_read_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index)175 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
176 {
177 uint32_t tmp;
178 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
179 tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
180 return tmp;
181 }
182
hri_rtcalarm_set_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)183 static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
184 hri_rtcalarm_alarm_reg_t mask)
185 {
186 RTC_CRITICAL_SECTION_ENTER();
187 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
188 RTC_CRITICAL_SECTION_LEAVE();
189 }
190
hri_rtcalarm_get_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)191 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
192 hri_rtcalarm_alarm_reg_t mask)
193 {
194 uint32_t tmp;
195 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
196 tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
197 return tmp;
198 }
199
hri_rtcalarm_write_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)200 static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
201 hri_rtcalarm_alarm_reg_t data)
202 {
203 uint32_t tmp;
204 RTC_CRITICAL_SECTION_ENTER();
205 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
206 tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
207 tmp |= RTC_MODE2_ALARM_MINUTE(data);
208 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
209 RTC_CRITICAL_SECTION_LEAVE();
210 }
211
hri_rtcalarm_clear_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)212 static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
213 hri_rtcalarm_alarm_reg_t mask)
214 {
215 RTC_CRITICAL_SECTION_ENTER();
216 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
217 RTC_CRITICAL_SECTION_LEAVE();
218 }
219
hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)220 static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
221 hri_rtcalarm_alarm_reg_t mask)
222 {
223 RTC_CRITICAL_SECTION_ENTER();
224 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
225 RTC_CRITICAL_SECTION_LEAVE();
226 }
227
hri_rtcalarm_read_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index)228 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
229 {
230 uint32_t tmp;
231 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
232 tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
233 return tmp;
234 }
235
hri_rtcalarm_set_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)236 static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
237 hri_rtcalarm_alarm_reg_t mask)
238 {
239 RTC_CRITICAL_SECTION_ENTER();
240 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
241 RTC_CRITICAL_SECTION_LEAVE();
242 }
243
hri_rtcalarm_get_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)244 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
245 hri_rtcalarm_alarm_reg_t mask)
246 {
247 uint32_t tmp;
248 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
249 tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
250 return tmp;
251 }
252
hri_rtcalarm_write_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)253 static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
254 hri_rtcalarm_alarm_reg_t data)
255 {
256 uint32_t tmp;
257 RTC_CRITICAL_SECTION_ENTER();
258 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
259 tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
260 tmp |= RTC_MODE2_ALARM_HOUR(data);
261 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
262 RTC_CRITICAL_SECTION_LEAVE();
263 }
264
hri_rtcalarm_clear_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)265 static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
266 hri_rtcalarm_alarm_reg_t mask)
267 {
268 RTC_CRITICAL_SECTION_ENTER();
269 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
270 RTC_CRITICAL_SECTION_LEAVE();
271 }
272
hri_rtcalarm_toggle_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)273 static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
274 hri_rtcalarm_alarm_reg_t mask)
275 {
276 RTC_CRITICAL_SECTION_ENTER();
277 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
278 RTC_CRITICAL_SECTION_LEAVE();
279 }
280
hri_rtcalarm_read_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index)281 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
282 {
283 uint32_t tmp;
284 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
285 tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
286 return tmp;
287 }
288
hri_rtcalarm_set_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)289 static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
290 hri_rtcalarm_alarm_reg_t mask)
291 {
292 RTC_CRITICAL_SECTION_ENTER();
293 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
294 RTC_CRITICAL_SECTION_LEAVE();
295 }
296
hri_rtcalarm_get_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)297 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
298 hri_rtcalarm_alarm_reg_t mask)
299 {
300 uint32_t tmp;
301 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
302 tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
303 return tmp;
304 }
305
hri_rtcalarm_write_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)306 static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
307 hri_rtcalarm_alarm_reg_t data)
308 {
309 uint32_t tmp;
310 RTC_CRITICAL_SECTION_ENTER();
311 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
312 tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
313 tmp |= RTC_MODE2_ALARM_DAY(data);
314 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
315 RTC_CRITICAL_SECTION_LEAVE();
316 }
317
hri_rtcalarm_clear_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)318 static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
319 hri_rtcalarm_alarm_reg_t mask)
320 {
321 RTC_CRITICAL_SECTION_ENTER();
322 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
323 RTC_CRITICAL_SECTION_LEAVE();
324 }
325
hri_rtcalarm_toggle_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)326 static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
327 hri_rtcalarm_alarm_reg_t mask)
328 {
329 RTC_CRITICAL_SECTION_ENTER();
330 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
331 RTC_CRITICAL_SECTION_LEAVE();
332 }
333
hri_rtcalarm_read_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index)334 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
335 {
336 uint32_t tmp;
337 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
338 tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
339 return tmp;
340 }
341
hri_rtcalarm_set_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)342 static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
343 hri_rtcalarm_alarm_reg_t mask)
344 {
345 RTC_CRITICAL_SECTION_ENTER();
346 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
347 RTC_CRITICAL_SECTION_LEAVE();
348 }
349
hri_rtcalarm_get_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)350 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
351 hri_rtcalarm_alarm_reg_t mask)
352 {
353 uint32_t tmp;
354 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
355 tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
356 return tmp;
357 }
358
hri_rtcalarm_write_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)359 static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
360 hri_rtcalarm_alarm_reg_t data)
361 {
362 uint32_t tmp;
363 RTC_CRITICAL_SECTION_ENTER();
364 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
365 tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
366 tmp |= RTC_MODE2_ALARM_MONTH(data);
367 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
368 RTC_CRITICAL_SECTION_LEAVE();
369 }
370
hri_rtcalarm_clear_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)371 static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
372 hri_rtcalarm_alarm_reg_t mask)
373 {
374 RTC_CRITICAL_SECTION_ENTER();
375 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
376 RTC_CRITICAL_SECTION_LEAVE();
377 }
378
hri_rtcalarm_toggle_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)379 static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
380 hri_rtcalarm_alarm_reg_t mask)
381 {
382 RTC_CRITICAL_SECTION_ENTER();
383 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
384 RTC_CRITICAL_SECTION_LEAVE();
385 }
386
hri_rtcalarm_read_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index)387 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
388 {
389 uint32_t tmp;
390 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
391 tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
392 return tmp;
393 }
394
hri_rtcalarm_set_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)395 static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
396 hri_rtcalarm_alarm_reg_t mask)
397 {
398 RTC_CRITICAL_SECTION_ENTER();
399 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
400 RTC_CRITICAL_SECTION_LEAVE();
401 }
402
hri_rtcalarm_get_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)403 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
404 hri_rtcalarm_alarm_reg_t mask)
405 {
406 uint32_t tmp;
407 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
408 tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
409 return tmp;
410 }
411
hri_rtcalarm_write_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)412 static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
413 hri_rtcalarm_alarm_reg_t data)
414 {
415 uint32_t tmp;
416 RTC_CRITICAL_SECTION_ENTER();
417 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
418 tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
419 tmp |= RTC_MODE2_ALARM_YEAR(data);
420 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
421 RTC_CRITICAL_SECTION_LEAVE();
422 }
423
hri_rtcalarm_clear_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)424 static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
425 hri_rtcalarm_alarm_reg_t mask)
426 {
427 RTC_CRITICAL_SECTION_ENTER();
428 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
429 RTC_CRITICAL_SECTION_LEAVE();
430 }
431
hri_rtcalarm_toggle_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)432 static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
433 hri_rtcalarm_alarm_reg_t mask)
434 {
435 RTC_CRITICAL_SECTION_ENTER();
436 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
437 RTC_CRITICAL_SECTION_LEAVE();
438 }
439
hri_rtcalarm_read_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index)440 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
441 {
442 uint32_t tmp;
443 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
444 tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
445 return tmp;
446 }
447
hri_rtcalarm_set_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)448 static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
449 hri_rtcalarm_alarm_reg_t mask)
450 {
451 RTC_CRITICAL_SECTION_ENTER();
452 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
453 RTC_CRITICAL_SECTION_LEAVE();
454 }
455
hri_rtcalarm_get_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)456 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
457 hri_rtcalarm_alarm_reg_t mask)
458 {
459 uint32_t tmp;
460 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
461 tmp &= mask;
462 return tmp;
463 }
464
hri_rtcalarm_write_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t data)465 static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
466 hri_rtcalarm_alarm_reg_t data)
467 {
468 RTC_CRITICAL_SECTION_ENTER();
469 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
470 RTC_CRITICAL_SECTION_LEAVE();
471 }
472
hri_rtcalarm_clear_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)473 static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
474 hri_rtcalarm_alarm_reg_t mask)
475 {
476 RTC_CRITICAL_SECTION_ENTER();
477 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
478 RTC_CRITICAL_SECTION_LEAVE();
479 }
480
hri_rtcalarm_toggle_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_alarm_reg_t mask)481 static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
482 hri_rtcalarm_alarm_reg_t mask)
483 {
484 RTC_CRITICAL_SECTION_ENTER();
485 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
486 RTC_CRITICAL_SECTION_LEAVE();
487 }
488
hri_rtcalarm_read_ALARM_reg(const void * const hw,uint8_t submodule_index)489 static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
490 {
491 return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
492 }
493
hri_rtcalarm_set_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)494 static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
495 hri_rtcalarm_mask_reg_t mask)
496 {
497 RTC_CRITICAL_SECTION_ENTER();
498 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
499 RTC_CRITICAL_SECTION_LEAVE();
500 }
501
hri_rtcalarm_get_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)502 static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
503 hri_rtcalarm_mask_reg_t mask)
504 {
505 uint8_t tmp;
506 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
507 tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
508 return tmp;
509 }
510
hri_rtcalarm_write_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t data)511 static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
512 hri_rtcalarm_mask_reg_t data)
513 {
514 uint8_t tmp;
515 RTC_CRITICAL_SECTION_ENTER();
516 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
517 tmp &= ~RTC_MODE2_MASK_SEL_Msk;
518 tmp |= RTC_MODE2_MASK_SEL(data);
519 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
520 RTC_CRITICAL_SECTION_LEAVE();
521 }
522
hri_rtcalarm_clear_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)523 static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
524 hri_rtcalarm_mask_reg_t mask)
525 {
526 RTC_CRITICAL_SECTION_ENTER();
527 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
528 RTC_CRITICAL_SECTION_LEAVE();
529 }
530
hri_rtcalarm_toggle_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)531 static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
532 hri_rtcalarm_mask_reg_t mask)
533 {
534 RTC_CRITICAL_SECTION_ENTER();
535 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
536 RTC_CRITICAL_SECTION_LEAVE();
537 }
538
hri_rtcalarm_read_MASK_SEL_bf(const void * const hw,uint8_t submodule_index)539 static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
540 {
541 uint8_t tmp;
542 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
543 tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
544 return tmp;
545 }
546
hri_rtcalarm_set_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)547 static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
548 hri_rtcalarm_mask_reg_t mask)
549 {
550 RTC_CRITICAL_SECTION_ENTER();
551 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
552 RTC_CRITICAL_SECTION_LEAVE();
553 }
554
hri_rtcalarm_get_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)555 static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
556 hri_rtcalarm_mask_reg_t mask)
557 {
558 uint8_t tmp;
559 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
560 tmp &= mask;
561 return tmp;
562 }
563
hri_rtcalarm_write_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t data)564 static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
565 hri_rtcalarm_mask_reg_t data)
566 {
567 RTC_CRITICAL_SECTION_ENTER();
568 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
569 RTC_CRITICAL_SECTION_LEAVE();
570 }
571
hri_rtcalarm_clear_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)572 static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
573 hri_rtcalarm_mask_reg_t mask)
574 {
575 RTC_CRITICAL_SECTION_ENTER();
576 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
577 RTC_CRITICAL_SECTION_LEAVE();
578 }
579
hri_rtcalarm_toggle_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcalarm_mask_reg_t mask)580 static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
581 hri_rtcalarm_mask_reg_t mask)
582 {
583 RTC_CRITICAL_SECTION_ENTER();
584 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
585 RTC_CRITICAL_SECTION_LEAVE();
586 }
587
hri_rtcalarm_read_MASK_reg(const void * const hw,uint8_t submodule_index)588 static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
589 {
590 return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
591 }
592
hri_rtcmode2_set_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)593 static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
594 hri_rtcmode2_alarm_reg_t mask)
595 {
596 RTC_CRITICAL_SECTION_ENTER();
597 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
598 RTC_CRITICAL_SECTION_LEAVE();
599 }
600
hri_rtcmode2_get_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)601 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
602 hri_rtcmode2_alarm_reg_t mask)
603 {
604 uint32_t tmp;
605 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
606 tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
607 return tmp;
608 }
609
hri_rtcmode2_write_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)610 static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
611 hri_rtcmode2_alarm_reg_t data)
612 {
613 uint32_t tmp;
614 RTC_CRITICAL_SECTION_ENTER();
615 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
616 tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
617 tmp |= RTC_MODE2_ALARM_SECOND(data);
618 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
619 RTC_CRITICAL_SECTION_LEAVE();
620 }
621
hri_rtcmode2_clear_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)622 static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
623 hri_rtcmode2_alarm_reg_t mask)
624 {
625 RTC_CRITICAL_SECTION_ENTER();
626 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
627 RTC_CRITICAL_SECTION_LEAVE();
628 }
629
hri_rtcmode2_toggle_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)630 static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
631 hri_rtcmode2_alarm_reg_t mask)
632 {
633 RTC_CRITICAL_SECTION_ENTER();
634 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
635 RTC_CRITICAL_SECTION_LEAVE();
636 }
637
hri_rtcmode2_read_ALARM_SECOND_bf(const void * const hw,uint8_t submodule_index)638 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
639 {
640 uint32_t tmp;
641 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
642 tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
643 return tmp;
644 }
645
hri_rtcmode2_set_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)646 static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
647 hri_rtcmode2_alarm_reg_t mask)
648 {
649 RTC_CRITICAL_SECTION_ENTER();
650 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
651 RTC_CRITICAL_SECTION_LEAVE();
652 }
653
hri_rtcmode2_get_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)654 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
655 hri_rtcmode2_alarm_reg_t mask)
656 {
657 uint32_t tmp;
658 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
659 tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
660 return tmp;
661 }
662
hri_rtcmode2_write_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)663 static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
664 hri_rtcmode2_alarm_reg_t data)
665 {
666 uint32_t tmp;
667 RTC_CRITICAL_SECTION_ENTER();
668 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
669 tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
670 tmp |= RTC_MODE2_ALARM_MINUTE(data);
671 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
672 RTC_CRITICAL_SECTION_LEAVE();
673 }
674
hri_rtcmode2_clear_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)675 static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
676 hri_rtcmode2_alarm_reg_t mask)
677 {
678 RTC_CRITICAL_SECTION_ENTER();
679 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
680 RTC_CRITICAL_SECTION_LEAVE();
681 }
682
hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)683 static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
684 hri_rtcmode2_alarm_reg_t mask)
685 {
686 RTC_CRITICAL_SECTION_ENTER();
687 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
688 RTC_CRITICAL_SECTION_LEAVE();
689 }
690
hri_rtcmode2_read_ALARM_MINUTE_bf(const void * const hw,uint8_t submodule_index)691 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
692 {
693 uint32_t tmp;
694 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
695 tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
696 return tmp;
697 }
698
hri_rtcmode2_set_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)699 static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
700 hri_rtcmode2_alarm_reg_t mask)
701 {
702 RTC_CRITICAL_SECTION_ENTER();
703 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
704 RTC_CRITICAL_SECTION_LEAVE();
705 }
706
hri_rtcmode2_get_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)707 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
708 hri_rtcmode2_alarm_reg_t mask)
709 {
710 uint32_t tmp;
711 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
712 tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
713 return tmp;
714 }
715
hri_rtcmode2_write_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)716 static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
717 hri_rtcmode2_alarm_reg_t data)
718 {
719 uint32_t tmp;
720 RTC_CRITICAL_SECTION_ENTER();
721 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
722 tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
723 tmp |= RTC_MODE2_ALARM_HOUR(data);
724 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
725 RTC_CRITICAL_SECTION_LEAVE();
726 }
727
hri_rtcmode2_clear_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)728 static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
729 hri_rtcmode2_alarm_reg_t mask)
730 {
731 RTC_CRITICAL_SECTION_ENTER();
732 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
733 RTC_CRITICAL_SECTION_LEAVE();
734 }
735
hri_rtcmode2_toggle_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)736 static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
737 hri_rtcmode2_alarm_reg_t mask)
738 {
739 RTC_CRITICAL_SECTION_ENTER();
740 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
741 RTC_CRITICAL_SECTION_LEAVE();
742 }
743
hri_rtcmode2_read_ALARM_HOUR_bf(const void * const hw,uint8_t submodule_index)744 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
745 {
746 uint32_t tmp;
747 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
748 tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
749 return tmp;
750 }
751
hri_rtcmode2_set_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)752 static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
753 hri_rtcmode2_alarm_reg_t mask)
754 {
755 RTC_CRITICAL_SECTION_ENTER();
756 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
757 RTC_CRITICAL_SECTION_LEAVE();
758 }
759
hri_rtcmode2_get_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)760 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
761 hri_rtcmode2_alarm_reg_t mask)
762 {
763 uint32_t tmp;
764 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
765 tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
766 return tmp;
767 }
768
hri_rtcmode2_write_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)769 static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
770 hri_rtcmode2_alarm_reg_t data)
771 {
772 uint32_t tmp;
773 RTC_CRITICAL_SECTION_ENTER();
774 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
775 tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
776 tmp |= RTC_MODE2_ALARM_DAY(data);
777 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
778 RTC_CRITICAL_SECTION_LEAVE();
779 }
780
hri_rtcmode2_clear_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)781 static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
782 hri_rtcmode2_alarm_reg_t mask)
783 {
784 RTC_CRITICAL_SECTION_ENTER();
785 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
786 RTC_CRITICAL_SECTION_LEAVE();
787 }
788
hri_rtcmode2_toggle_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)789 static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
790 hri_rtcmode2_alarm_reg_t mask)
791 {
792 RTC_CRITICAL_SECTION_ENTER();
793 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
794 RTC_CRITICAL_SECTION_LEAVE();
795 }
796
hri_rtcmode2_read_ALARM_DAY_bf(const void * const hw,uint8_t submodule_index)797 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
798 {
799 uint32_t tmp;
800 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
801 tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
802 return tmp;
803 }
804
hri_rtcmode2_set_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)805 static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
806 hri_rtcmode2_alarm_reg_t mask)
807 {
808 RTC_CRITICAL_SECTION_ENTER();
809 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
810 RTC_CRITICAL_SECTION_LEAVE();
811 }
812
hri_rtcmode2_get_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)813 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
814 hri_rtcmode2_alarm_reg_t mask)
815 {
816 uint32_t tmp;
817 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
818 tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
819 return tmp;
820 }
821
hri_rtcmode2_write_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)822 static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
823 hri_rtcmode2_alarm_reg_t data)
824 {
825 uint32_t tmp;
826 RTC_CRITICAL_SECTION_ENTER();
827 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
828 tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
829 tmp |= RTC_MODE2_ALARM_MONTH(data);
830 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
831 RTC_CRITICAL_SECTION_LEAVE();
832 }
833
hri_rtcmode2_clear_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)834 static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
835 hri_rtcmode2_alarm_reg_t mask)
836 {
837 RTC_CRITICAL_SECTION_ENTER();
838 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
839 RTC_CRITICAL_SECTION_LEAVE();
840 }
841
hri_rtcmode2_toggle_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)842 static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
843 hri_rtcmode2_alarm_reg_t mask)
844 {
845 RTC_CRITICAL_SECTION_ENTER();
846 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
847 RTC_CRITICAL_SECTION_LEAVE();
848 }
849
hri_rtcmode2_read_ALARM_MONTH_bf(const void * const hw,uint8_t submodule_index)850 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
851 {
852 uint32_t tmp;
853 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
854 tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
855 return tmp;
856 }
857
hri_rtcmode2_set_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)858 static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
859 hri_rtcmode2_alarm_reg_t mask)
860 {
861 RTC_CRITICAL_SECTION_ENTER();
862 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
863 RTC_CRITICAL_SECTION_LEAVE();
864 }
865
hri_rtcmode2_get_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)866 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
867 hri_rtcmode2_alarm_reg_t mask)
868 {
869 uint32_t tmp;
870 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
871 tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
872 return tmp;
873 }
874
hri_rtcmode2_write_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)875 static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
876 hri_rtcmode2_alarm_reg_t data)
877 {
878 uint32_t tmp;
879 RTC_CRITICAL_SECTION_ENTER();
880 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
881 tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
882 tmp |= RTC_MODE2_ALARM_YEAR(data);
883 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
884 RTC_CRITICAL_SECTION_LEAVE();
885 }
886
hri_rtcmode2_clear_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)887 static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
888 hri_rtcmode2_alarm_reg_t mask)
889 {
890 RTC_CRITICAL_SECTION_ENTER();
891 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
892 RTC_CRITICAL_SECTION_LEAVE();
893 }
894
hri_rtcmode2_toggle_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)895 static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
896 hri_rtcmode2_alarm_reg_t mask)
897 {
898 RTC_CRITICAL_SECTION_ENTER();
899 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
900 RTC_CRITICAL_SECTION_LEAVE();
901 }
902
hri_rtcmode2_read_ALARM_YEAR_bf(const void * const hw,uint8_t submodule_index)903 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
904 {
905 uint32_t tmp;
906 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
907 tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
908 return tmp;
909 }
910
hri_rtcmode2_set_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)911 static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
912 hri_rtcmode2_alarm_reg_t mask)
913 {
914 RTC_CRITICAL_SECTION_ENTER();
915 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
916 RTC_CRITICAL_SECTION_LEAVE();
917 }
918
hri_rtcmode2_get_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)919 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
920 hri_rtcmode2_alarm_reg_t mask)
921 {
922 uint32_t tmp;
923 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
924 tmp &= mask;
925 return tmp;
926 }
927
hri_rtcmode2_write_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t data)928 static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
929 hri_rtcmode2_alarm_reg_t data)
930 {
931 RTC_CRITICAL_SECTION_ENTER();
932 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
933 RTC_CRITICAL_SECTION_LEAVE();
934 }
935
hri_rtcmode2_clear_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)936 static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
937 hri_rtcmode2_alarm_reg_t mask)
938 {
939 RTC_CRITICAL_SECTION_ENTER();
940 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
941 RTC_CRITICAL_SECTION_LEAVE();
942 }
943
hri_rtcmode2_toggle_ALARM_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_alarm_reg_t mask)944 static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
945 hri_rtcmode2_alarm_reg_t mask)
946 {
947 RTC_CRITICAL_SECTION_ENTER();
948 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
949 RTC_CRITICAL_SECTION_LEAVE();
950 }
951
hri_rtcmode2_read_ALARM_reg(const void * const hw,uint8_t submodule_index)952 static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
953 {
954 return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
955 }
956
hri_rtcmode2_set_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)957 static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
958 hri_rtcmode2_mask_reg_t mask)
959 {
960 RTC_CRITICAL_SECTION_ENTER();
961 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
962 RTC_CRITICAL_SECTION_LEAVE();
963 }
964
hri_rtcmode2_get_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)965 static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
966 hri_rtcmode2_mask_reg_t mask)
967 {
968 uint8_t tmp;
969 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
970 tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
971 return tmp;
972 }
973
hri_rtcmode2_write_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t data)974 static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
975 hri_rtcmode2_mask_reg_t data)
976 {
977 uint8_t tmp;
978 RTC_CRITICAL_SECTION_ENTER();
979 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
980 tmp &= ~RTC_MODE2_MASK_SEL_Msk;
981 tmp |= RTC_MODE2_MASK_SEL(data);
982 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
983 RTC_CRITICAL_SECTION_LEAVE();
984 }
985
hri_rtcmode2_clear_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)986 static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
987 hri_rtcmode2_mask_reg_t mask)
988 {
989 RTC_CRITICAL_SECTION_ENTER();
990 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
991 RTC_CRITICAL_SECTION_LEAVE();
992 }
993
hri_rtcmode2_toggle_MASK_SEL_bf(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)994 static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
995 hri_rtcmode2_mask_reg_t mask)
996 {
997 RTC_CRITICAL_SECTION_ENTER();
998 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
999 RTC_CRITICAL_SECTION_LEAVE();
1000 }
1001
hri_rtcmode2_read_MASK_SEL_bf(const void * const hw,uint8_t submodule_index)1002 static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
1003 {
1004 uint8_t tmp;
1005 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
1006 tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
1007 return tmp;
1008 }
1009
hri_rtcmode2_set_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)1010 static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
1011 hri_rtcmode2_mask_reg_t mask)
1012 {
1013 RTC_CRITICAL_SECTION_ENTER();
1014 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
1015 RTC_CRITICAL_SECTION_LEAVE();
1016 }
1017
hri_rtcmode2_get_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)1018 static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
1019 hri_rtcmode2_mask_reg_t mask)
1020 {
1021 uint8_t tmp;
1022 tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
1023 tmp &= mask;
1024 return tmp;
1025 }
1026
hri_rtcmode2_write_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t data)1027 static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
1028 hri_rtcmode2_mask_reg_t data)
1029 {
1030 RTC_CRITICAL_SECTION_ENTER();
1031 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
1032 RTC_CRITICAL_SECTION_LEAVE();
1033 }
1034
hri_rtcmode2_clear_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)1035 static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
1036 hri_rtcmode2_mask_reg_t mask)
1037 {
1038 RTC_CRITICAL_SECTION_ENTER();
1039 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
1040 RTC_CRITICAL_SECTION_LEAVE();
1041 }
1042
hri_rtcmode2_toggle_MASK_reg(const void * const hw,uint8_t submodule_index,hri_rtcmode2_mask_reg_t mask)1043 static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
1044 hri_rtcmode2_mask_reg_t mask)
1045 {
1046 RTC_CRITICAL_SECTION_ENTER();
1047 ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
1048 RTC_CRITICAL_SECTION_LEAVE();
1049 }
1050
hri_rtcmode2_read_MASK_reg(const void * const hw,uint8_t submodule_index)1051 static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
1052 {
1053 return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
1054 }
1055
hri_rtcmode2_set_INTEN_PER0_bit(const void * const hw)1056 static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
1057 {
1058 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
1059 }
1060
hri_rtcmode2_get_INTEN_PER0_bit(const void * const hw)1061 static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
1062 {
1063 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
1064 }
1065
hri_rtcmode2_write_INTEN_PER0_bit(const void * const hw,bool value)1066 static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
1067 {
1068 if (value == 0x0) {
1069 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
1070 } else {
1071 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
1072 }
1073 }
1074
hri_rtcmode2_clear_INTEN_PER0_bit(const void * const hw)1075 static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
1076 {
1077 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
1078 }
1079
hri_rtcmode2_set_INTEN_PER1_bit(const void * const hw)1080 static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
1081 {
1082 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
1083 }
1084
hri_rtcmode2_get_INTEN_PER1_bit(const void * const hw)1085 static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
1086 {
1087 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
1088 }
1089
hri_rtcmode2_write_INTEN_PER1_bit(const void * const hw,bool value)1090 static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
1091 {
1092 if (value == 0x0) {
1093 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
1094 } else {
1095 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
1096 }
1097 }
1098
hri_rtcmode2_clear_INTEN_PER1_bit(const void * const hw)1099 static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
1100 {
1101 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
1102 }
1103
hri_rtcmode2_set_INTEN_PER2_bit(const void * const hw)1104 static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
1105 {
1106 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
1107 }
1108
hri_rtcmode2_get_INTEN_PER2_bit(const void * const hw)1109 static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
1110 {
1111 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
1112 }
1113
hri_rtcmode2_write_INTEN_PER2_bit(const void * const hw,bool value)1114 static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
1115 {
1116 if (value == 0x0) {
1117 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
1118 } else {
1119 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
1120 }
1121 }
1122
hri_rtcmode2_clear_INTEN_PER2_bit(const void * const hw)1123 static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
1124 {
1125 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
1126 }
1127
hri_rtcmode2_set_INTEN_PER3_bit(const void * const hw)1128 static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
1129 {
1130 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
1131 }
1132
hri_rtcmode2_get_INTEN_PER3_bit(const void * const hw)1133 static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
1134 {
1135 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
1136 }
1137
hri_rtcmode2_write_INTEN_PER3_bit(const void * const hw,bool value)1138 static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
1139 {
1140 if (value == 0x0) {
1141 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
1142 } else {
1143 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
1144 }
1145 }
1146
hri_rtcmode2_clear_INTEN_PER3_bit(const void * const hw)1147 static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
1148 {
1149 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
1150 }
1151
hri_rtcmode2_set_INTEN_PER4_bit(const void * const hw)1152 static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
1153 {
1154 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
1155 }
1156
hri_rtcmode2_get_INTEN_PER4_bit(const void * const hw)1157 static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
1158 {
1159 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
1160 }
1161
hri_rtcmode2_write_INTEN_PER4_bit(const void * const hw,bool value)1162 static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
1163 {
1164 if (value == 0x0) {
1165 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
1166 } else {
1167 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
1168 }
1169 }
1170
hri_rtcmode2_clear_INTEN_PER4_bit(const void * const hw)1171 static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
1172 {
1173 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
1174 }
1175
hri_rtcmode2_set_INTEN_PER5_bit(const void * const hw)1176 static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
1177 {
1178 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
1179 }
1180
hri_rtcmode2_get_INTEN_PER5_bit(const void * const hw)1181 static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
1182 {
1183 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
1184 }
1185
hri_rtcmode2_write_INTEN_PER5_bit(const void * const hw,bool value)1186 static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
1187 {
1188 if (value == 0x0) {
1189 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
1190 } else {
1191 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
1192 }
1193 }
1194
hri_rtcmode2_clear_INTEN_PER5_bit(const void * const hw)1195 static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
1196 {
1197 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
1198 }
1199
hri_rtcmode2_set_INTEN_PER6_bit(const void * const hw)1200 static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
1201 {
1202 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
1203 }
1204
hri_rtcmode2_get_INTEN_PER6_bit(const void * const hw)1205 static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
1206 {
1207 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
1208 }
1209
hri_rtcmode2_write_INTEN_PER6_bit(const void * const hw,bool value)1210 static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
1211 {
1212 if (value == 0x0) {
1213 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
1214 } else {
1215 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
1216 }
1217 }
1218
hri_rtcmode2_clear_INTEN_PER6_bit(const void * const hw)1219 static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
1220 {
1221 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
1222 }
1223
hri_rtcmode2_set_INTEN_PER7_bit(const void * const hw)1224 static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
1225 {
1226 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
1227 }
1228
hri_rtcmode2_get_INTEN_PER7_bit(const void * const hw)1229 static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
1230 {
1231 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
1232 }
1233
hri_rtcmode2_write_INTEN_PER7_bit(const void * const hw,bool value)1234 static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
1235 {
1236 if (value == 0x0) {
1237 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
1238 } else {
1239 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
1240 }
1241 }
1242
hri_rtcmode2_clear_INTEN_PER7_bit(const void * const hw)1243 static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
1244 {
1245 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
1246 }
1247
hri_rtcmode2_set_INTEN_ALARM0_bit(const void * const hw)1248 static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
1249 {
1250 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
1251 }
1252
hri_rtcmode2_get_INTEN_ALARM0_bit(const void * const hw)1253 static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
1254 {
1255 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
1256 }
1257
hri_rtcmode2_write_INTEN_ALARM0_bit(const void * const hw,bool value)1258 static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
1259 {
1260 if (value == 0x0) {
1261 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
1262 } else {
1263 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
1264 }
1265 }
1266
hri_rtcmode2_clear_INTEN_ALARM0_bit(const void * const hw)1267 static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
1268 {
1269 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
1270 }
1271
hri_rtcmode2_set_INTEN_OVF_bit(const void * const hw)1272 static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
1273 {
1274 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
1275 }
1276
hri_rtcmode2_get_INTEN_OVF_bit(const void * const hw)1277 static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
1278 {
1279 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
1280 }
1281
hri_rtcmode2_write_INTEN_OVF_bit(const void * const hw,bool value)1282 static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
1283 {
1284 if (value == 0x0) {
1285 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
1286 } else {
1287 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
1288 }
1289 }
1290
hri_rtcmode2_clear_INTEN_OVF_bit(const void * const hw)1291 static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
1292 {
1293 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
1294 }
1295
hri_rtcmode2_set_INTEN_reg(const void * const hw,hri_rtcmode2_intenset_reg_t mask)1296 static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
1297 {
1298 ((Rtc *)hw)->MODE2.INTENSET.reg = mask;
1299 }
1300
hri_rtcmode2_get_INTEN_reg(const void * const hw,hri_rtcmode2_intenset_reg_t mask)1301 static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw,
1302 hri_rtcmode2_intenset_reg_t mask)
1303 {
1304 uint16_t tmp;
1305 tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
1306 tmp &= mask;
1307 return tmp;
1308 }
1309
hri_rtcmode2_read_INTEN_reg(const void * const hw)1310 static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
1311 {
1312 return ((Rtc *)hw)->MODE2.INTENSET.reg;
1313 }
1314
hri_rtcmode2_write_INTEN_reg(const void * const hw,hri_rtcmode2_intenset_reg_t data)1315 static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
1316 {
1317 ((Rtc *)hw)->MODE2.INTENSET.reg = data;
1318 ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
1319 }
1320
hri_rtcmode2_clear_INTEN_reg(const void * const hw,hri_rtcmode2_intenset_reg_t mask)1321 static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
1322 {
1323 ((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
1324 }
1325
hri_rtcmode2_get_INTFLAG_PER0_bit(const void * const hw)1326 static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
1327 {
1328 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
1329 }
1330
hri_rtcmode2_clear_INTFLAG_PER0_bit(const void * const hw)1331 static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
1332 {
1333 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
1334 }
1335
hri_rtcmode2_get_INTFLAG_PER1_bit(const void * const hw)1336 static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
1337 {
1338 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
1339 }
1340
hri_rtcmode2_clear_INTFLAG_PER1_bit(const void * const hw)1341 static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
1342 {
1343 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
1344 }
1345
hri_rtcmode2_get_INTFLAG_PER2_bit(const void * const hw)1346 static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
1347 {
1348 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
1349 }
1350
hri_rtcmode2_clear_INTFLAG_PER2_bit(const void * const hw)1351 static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
1352 {
1353 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
1354 }
1355
hri_rtcmode2_get_INTFLAG_PER3_bit(const void * const hw)1356 static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
1357 {
1358 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
1359 }
1360
hri_rtcmode2_clear_INTFLAG_PER3_bit(const void * const hw)1361 static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
1362 {
1363 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
1364 }
1365
hri_rtcmode2_get_INTFLAG_PER4_bit(const void * const hw)1366 static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
1367 {
1368 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
1369 }
1370
hri_rtcmode2_clear_INTFLAG_PER4_bit(const void * const hw)1371 static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
1372 {
1373 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
1374 }
1375
hri_rtcmode2_get_INTFLAG_PER5_bit(const void * const hw)1376 static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
1377 {
1378 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
1379 }
1380
hri_rtcmode2_clear_INTFLAG_PER5_bit(const void * const hw)1381 static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
1382 {
1383 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
1384 }
1385
hri_rtcmode2_get_INTFLAG_PER6_bit(const void * const hw)1386 static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
1387 {
1388 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
1389 }
1390
hri_rtcmode2_clear_INTFLAG_PER6_bit(const void * const hw)1391 static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
1392 {
1393 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
1394 }
1395
hri_rtcmode2_get_INTFLAG_PER7_bit(const void * const hw)1396 static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
1397 {
1398 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
1399 }
1400
hri_rtcmode2_clear_INTFLAG_PER7_bit(const void * const hw)1401 static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
1402 {
1403 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
1404 }
1405
hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void * const hw)1406 static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
1407 {
1408 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
1409 }
1410
hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void * const hw)1411 static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
1412 {
1413 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
1414 }
1415
hri_rtcmode2_get_INTFLAG_OVF_bit(const void * const hw)1416 static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
1417 {
1418 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
1419 }
1420
hri_rtcmode2_clear_INTFLAG_OVF_bit(const void * const hw)1421 static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
1422 {
1423 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
1424 }
1425
hri_rtcmode2_get_interrupt_PER0_bit(const void * const hw)1426 static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
1427 {
1428 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
1429 }
1430
hri_rtcmode2_clear_interrupt_PER0_bit(const void * const hw)1431 static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
1432 {
1433 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
1434 }
1435
hri_rtcmode2_get_interrupt_PER1_bit(const void * const hw)1436 static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
1437 {
1438 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
1439 }
1440
hri_rtcmode2_clear_interrupt_PER1_bit(const void * const hw)1441 static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
1442 {
1443 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
1444 }
1445
hri_rtcmode2_get_interrupt_PER2_bit(const void * const hw)1446 static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
1447 {
1448 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
1449 }
1450
hri_rtcmode2_clear_interrupt_PER2_bit(const void * const hw)1451 static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
1452 {
1453 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
1454 }
1455
hri_rtcmode2_get_interrupt_PER3_bit(const void * const hw)1456 static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
1457 {
1458 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
1459 }
1460
hri_rtcmode2_clear_interrupt_PER3_bit(const void * const hw)1461 static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
1462 {
1463 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
1464 }
1465
hri_rtcmode2_get_interrupt_PER4_bit(const void * const hw)1466 static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
1467 {
1468 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
1469 }
1470
hri_rtcmode2_clear_interrupt_PER4_bit(const void * const hw)1471 static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
1472 {
1473 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
1474 }
1475
hri_rtcmode2_get_interrupt_PER5_bit(const void * const hw)1476 static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
1477 {
1478 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
1479 }
1480
hri_rtcmode2_clear_interrupt_PER5_bit(const void * const hw)1481 static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
1482 {
1483 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
1484 }
1485
hri_rtcmode2_get_interrupt_PER6_bit(const void * const hw)1486 static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
1487 {
1488 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
1489 }
1490
hri_rtcmode2_clear_interrupt_PER6_bit(const void * const hw)1491 static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
1492 {
1493 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
1494 }
1495
hri_rtcmode2_get_interrupt_PER7_bit(const void * const hw)1496 static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
1497 {
1498 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
1499 }
1500
hri_rtcmode2_clear_interrupt_PER7_bit(const void * const hw)1501 static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
1502 {
1503 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
1504 }
1505
hri_rtcmode2_get_interrupt_ALARM0_bit(const void * const hw)1506 static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
1507 {
1508 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
1509 }
1510
hri_rtcmode2_clear_interrupt_ALARM0_bit(const void * const hw)1511 static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
1512 {
1513 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
1514 }
1515
hri_rtcmode2_get_interrupt_OVF_bit(const void * const hw)1516 static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
1517 {
1518 return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
1519 }
1520
hri_rtcmode2_clear_interrupt_OVF_bit(const void * const hw)1521 static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
1522 {
1523 ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
1524 }
1525
hri_rtcmode2_get_INTFLAG_reg(const void * const hw,hri_rtcmode2_intflag_reg_t mask)1526 static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw,
1527 hri_rtcmode2_intflag_reg_t mask)
1528 {
1529 uint16_t tmp;
1530 tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
1531 tmp &= mask;
1532 return tmp;
1533 }
1534
hri_rtcmode2_read_INTFLAG_reg(const void * const hw)1535 static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
1536 {
1537 return ((Rtc *)hw)->MODE2.INTFLAG.reg;
1538 }
1539
hri_rtcmode2_clear_INTFLAG_reg(const void * const hw,hri_rtcmode2_intflag_reg_t mask)1540 static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
1541 {
1542 ((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
1543 }
1544
hri_rtcmode2_set_CTRLA_SWRST_bit(const void * const hw)1545 static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
1546 {
1547 RTC_CRITICAL_SECTION_ENTER();
1548 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
1549 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
1550 RTC_CRITICAL_SECTION_LEAVE();
1551 }
1552
hri_rtcmode2_get_CTRLA_SWRST_bit(const void * const hw)1553 static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
1554 {
1555 uint16_t tmp;
1556 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
1557 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1558 tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
1559 return (bool)tmp;
1560 }
1561
hri_rtcmode2_set_CTRLA_ENABLE_bit(const void * const hw)1562 static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
1563 {
1564 RTC_CRITICAL_SECTION_ENTER();
1565 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1566 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
1567 RTC_CRITICAL_SECTION_LEAVE();
1568 }
1569
hri_rtcmode2_get_CTRLA_ENABLE_bit(const void * const hw)1570 static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
1571 {
1572 uint16_t tmp;
1573 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1574 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1575 tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
1576 return (bool)tmp;
1577 }
1578
hri_rtcmode2_write_CTRLA_ENABLE_bit(const void * const hw,bool value)1579 static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
1580 {
1581 uint16_t tmp;
1582 RTC_CRITICAL_SECTION_ENTER();
1583 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1584 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1585 tmp &= ~RTC_MODE2_CTRLA_ENABLE;
1586 tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
1587 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1588 RTC_CRITICAL_SECTION_LEAVE();
1589 }
1590
hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void * const hw)1591 static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
1592 {
1593 RTC_CRITICAL_SECTION_ENTER();
1594 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1595 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
1596 RTC_CRITICAL_SECTION_LEAVE();
1597 }
1598
hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void * const hw)1599 static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
1600 {
1601 RTC_CRITICAL_SECTION_ENTER();
1602 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1603 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
1604 RTC_CRITICAL_SECTION_LEAVE();
1605 }
1606
hri_rtcmode2_set_CTRLA_CLKREP_bit(const void * const hw)1607 static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
1608 {
1609 RTC_CRITICAL_SECTION_ENTER();
1610 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1611 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
1612 RTC_CRITICAL_SECTION_LEAVE();
1613 }
1614
hri_rtcmode2_get_CTRLA_CLKREP_bit(const void * const hw)1615 static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
1616 {
1617 uint16_t tmp;
1618 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1619 tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
1620 return (bool)tmp;
1621 }
1622
hri_rtcmode2_write_CTRLA_CLKREP_bit(const void * const hw,bool value)1623 static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
1624 {
1625 uint16_t tmp;
1626 RTC_CRITICAL_SECTION_ENTER();
1627 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1628 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1629 tmp &= ~RTC_MODE2_CTRLA_CLKREP;
1630 tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
1631 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1632 RTC_CRITICAL_SECTION_LEAVE();
1633 }
1634
hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void * const hw)1635 static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
1636 {
1637 RTC_CRITICAL_SECTION_ENTER();
1638 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1639 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
1640 RTC_CRITICAL_SECTION_LEAVE();
1641 }
1642
hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void * const hw)1643 static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
1644 {
1645 RTC_CRITICAL_SECTION_ENTER();
1646 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1647 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
1648 RTC_CRITICAL_SECTION_LEAVE();
1649 }
1650
hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void * const hw)1651 static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
1652 {
1653 RTC_CRITICAL_SECTION_ENTER();
1654 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1655 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
1656 RTC_CRITICAL_SECTION_LEAVE();
1657 }
1658
hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void * const hw)1659 static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
1660 {
1661 uint16_t tmp;
1662 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1663 tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
1664 return (bool)tmp;
1665 }
1666
hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void * const hw,bool value)1667 static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
1668 {
1669 uint16_t tmp;
1670 RTC_CRITICAL_SECTION_ENTER();
1671 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1672 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1673 tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
1674 tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
1675 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1676 RTC_CRITICAL_SECTION_LEAVE();
1677 }
1678
hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void * const hw)1679 static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
1680 {
1681 RTC_CRITICAL_SECTION_ENTER();
1682 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1683 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
1684 RTC_CRITICAL_SECTION_LEAVE();
1685 }
1686
hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void * const hw)1687 static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
1688 {
1689 RTC_CRITICAL_SECTION_ENTER();
1690 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1691 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
1692 RTC_CRITICAL_SECTION_LEAVE();
1693 }
1694
hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void * const hw)1695 static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
1696 {
1697 RTC_CRITICAL_SECTION_ENTER();
1698 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1699 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
1700 RTC_CRITICAL_SECTION_LEAVE();
1701 }
1702
hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void * const hw)1703 static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
1704 {
1705 uint16_t tmp;
1706 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1707 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1708 tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
1709 return (bool)tmp;
1710 }
1711
hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void * const hw,bool value)1712 static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
1713 {
1714 uint16_t tmp;
1715 RTC_CRITICAL_SECTION_ENTER();
1716 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1717 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1718 tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
1719 tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
1720 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1721 RTC_CRITICAL_SECTION_LEAVE();
1722 }
1723
hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void * const hw)1724 static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
1725 {
1726 RTC_CRITICAL_SECTION_ENTER();
1727 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1728 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
1729 RTC_CRITICAL_SECTION_LEAVE();
1730 }
1731
hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void * const hw)1732 static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
1733 {
1734 RTC_CRITICAL_SECTION_ENTER();
1735 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
1736 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
1737 RTC_CRITICAL_SECTION_LEAVE();
1738 }
1739
hri_rtcmode2_set_CTRLA_MODE_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1740 static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1741 {
1742 RTC_CRITICAL_SECTION_ENTER();
1743 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1744 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
1745 RTC_CRITICAL_SECTION_LEAVE();
1746 }
1747
hri_rtcmode2_get_CTRLA_MODE_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1748 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw,
1749 hri_rtcmode2_ctrla_reg_t mask)
1750 {
1751 uint16_t tmp;
1752 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1753 tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
1754 return tmp;
1755 }
1756
hri_rtcmode2_write_CTRLA_MODE_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t data)1757 static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
1758 {
1759 uint16_t tmp;
1760 RTC_CRITICAL_SECTION_ENTER();
1761 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1762 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1763 tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
1764 tmp |= RTC_MODE2_CTRLA_MODE(data);
1765 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1766 RTC_CRITICAL_SECTION_LEAVE();
1767 }
1768
hri_rtcmode2_clear_CTRLA_MODE_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1769 static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1770 {
1771 RTC_CRITICAL_SECTION_ENTER();
1772 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1773 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
1774 RTC_CRITICAL_SECTION_LEAVE();
1775 }
1776
hri_rtcmode2_toggle_CTRLA_MODE_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1777 static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1778 {
1779 RTC_CRITICAL_SECTION_ENTER();
1780 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1781 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
1782 RTC_CRITICAL_SECTION_LEAVE();
1783 }
1784
hri_rtcmode2_read_CTRLA_MODE_bf(const void * const hw)1785 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
1786 {
1787 uint16_t tmp;
1788 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1789 tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
1790 return tmp;
1791 }
1792
hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1793 static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1794 {
1795 RTC_CRITICAL_SECTION_ENTER();
1796 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1797 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
1798 RTC_CRITICAL_SECTION_LEAVE();
1799 }
1800
hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1801 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw,
1802 hri_rtcmode2_ctrla_reg_t mask)
1803 {
1804 uint16_t tmp;
1805 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1806 tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
1807 return tmp;
1808 }
1809
hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t data)1810 static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
1811 {
1812 uint16_t tmp;
1813 RTC_CRITICAL_SECTION_ENTER();
1814 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1815 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1816 tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
1817 tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
1818 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
1819 RTC_CRITICAL_SECTION_LEAVE();
1820 }
1821
hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1822 static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1823 {
1824 RTC_CRITICAL_SECTION_ENTER();
1825 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1826 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
1827 RTC_CRITICAL_SECTION_LEAVE();
1828 }
1829
hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1830 static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1831 {
1832 RTC_CRITICAL_SECTION_ENTER();
1833 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
1834 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
1835 RTC_CRITICAL_SECTION_LEAVE();
1836 }
1837
hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void * const hw)1838 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
1839 {
1840 uint16_t tmp;
1841 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1842 tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
1843 return tmp;
1844 }
1845
hri_rtcmode2_set_CTRLA_reg(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1846 static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1847 {
1848 RTC_CRITICAL_SECTION_ENTER();
1849 ((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
1850 RTC_CRITICAL_SECTION_LEAVE();
1851 }
1852
hri_rtcmode2_get_CTRLA_reg(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1853 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1854 {
1855 uint16_t tmp;
1856 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
1857 tmp &= mask;
1858 return tmp;
1859 }
1860
hri_rtcmode2_write_CTRLA_reg(const void * const hw,hri_rtcmode2_ctrla_reg_t data)1861 static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
1862 {
1863 RTC_CRITICAL_SECTION_ENTER();
1864 ((Rtc *)hw)->MODE2.CTRLA.reg = data;
1865 RTC_CRITICAL_SECTION_LEAVE();
1866 }
1867
hri_rtcmode2_clear_CTRLA_reg(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1868 static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1869 {
1870 RTC_CRITICAL_SECTION_ENTER();
1871 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
1872 RTC_CRITICAL_SECTION_LEAVE();
1873 }
1874
hri_rtcmode2_toggle_CTRLA_reg(const void * const hw,hri_rtcmode2_ctrla_reg_t mask)1875 static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
1876 {
1877 RTC_CRITICAL_SECTION_ENTER();
1878 ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
1879 RTC_CRITICAL_SECTION_LEAVE();
1880 }
1881
hri_rtcmode2_read_CTRLA_reg(const void * const hw)1882 static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
1883 {
1884 return ((Rtc *)hw)->MODE2.CTRLA.reg;
1885 }
1886
hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void * const hw)1887 static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
1888 {
1889 RTC_CRITICAL_SECTION_ENTER();
1890 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
1891 RTC_CRITICAL_SECTION_LEAVE();
1892 }
1893
hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void * const hw)1894 static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
1895 {
1896 uint32_t tmp;
1897 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1898 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
1899 return (bool)tmp;
1900 }
1901
hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void * const hw,bool value)1902 static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
1903 {
1904 uint32_t tmp;
1905 RTC_CRITICAL_SECTION_ENTER();
1906 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1907 tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
1908 tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
1909 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
1910 RTC_CRITICAL_SECTION_LEAVE();
1911 }
1912
hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void * const hw)1913 static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
1914 {
1915 RTC_CRITICAL_SECTION_ENTER();
1916 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
1917 RTC_CRITICAL_SECTION_LEAVE();
1918 }
1919
hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void * const hw)1920 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
1921 {
1922 RTC_CRITICAL_SECTION_ENTER();
1923 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
1924 RTC_CRITICAL_SECTION_LEAVE();
1925 }
1926
hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void * const hw)1927 static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
1928 {
1929 RTC_CRITICAL_SECTION_ENTER();
1930 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
1931 RTC_CRITICAL_SECTION_LEAVE();
1932 }
1933
hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void * const hw)1934 static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
1935 {
1936 uint32_t tmp;
1937 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1938 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
1939 return (bool)tmp;
1940 }
1941
hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void * const hw,bool value)1942 static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
1943 {
1944 uint32_t tmp;
1945 RTC_CRITICAL_SECTION_ENTER();
1946 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1947 tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
1948 tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
1949 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
1950 RTC_CRITICAL_SECTION_LEAVE();
1951 }
1952
hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void * const hw)1953 static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
1954 {
1955 RTC_CRITICAL_SECTION_ENTER();
1956 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
1957 RTC_CRITICAL_SECTION_LEAVE();
1958 }
1959
hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void * const hw)1960 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
1961 {
1962 RTC_CRITICAL_SECTION_ENTER();
1963 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
1964 RTC_CRITICAL_SECTION_LEAVE();
1965 }
1966
hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void * const hw)1967 static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
1968 {
1969 RTC_CRITICAL_SECTION_ENTER();
1970 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
1971 RTC_CRITICAL_SECTION_LEAVE();
1972 }
1973
hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void * const hw)1974 static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
1975 {
1976 uint32_t tmp;
1977 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1978 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
1979 return (bool)tmp;
1980 }
1981
hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void * const hw,bool value)1982 static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
1983 {
1984 uint32_t tmp;
1985 RTC_CRITICAL_SECTION_ENTER();
1986 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
1987 tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
1988 tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
1989 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
1990 RTC_CRITICAL_SECTION_LEAVE();
1991 }
1992
hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void * const hw)1993 static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
1994 {
1995 RTC_CRITICAL_SECTION_ENTER();
1996 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
1997 RTC_CRITICAL_SECTION_LEAVE();
1998 }
1999
hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void * const hw)2000 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
2001 {
2002 RTC_CRITICAL_SECTION_ENTER();
2003 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
2004 RTC_CRITICAL_SECTION_LEAVE();
2005 }
2006
hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void * const hw)2007 static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
2008 {
2009 RTC_CRITICAL_SECTION_ENTER();
2010 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
2011 RTC_CRITICAL_SECTION_LEAVE();
2012 }
2013
hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void * const hw)2014 static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
2015 {
2016 uint32_t tmp;
2017 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2018 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
2019 return (bool)tmp;
2020 }
2021
hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void * const hw,bool value)2022 static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
2023 {
2024 uint32_t tmp;
2025 RTC_CRITICAL_SECTION_ENTER();
2026 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2027 tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
2028 tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
2029 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2030 RTC_CRITICAL_SECTION_LEAVE();
2031 }
2032
hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void * const hw)2033 static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
2034 {
2035 RTC_CRITICAL_SECTION_ENTER();
2036 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
2037 RTC_CRITICAL_SECTION_LEAVE();
2038 }
2039
hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void * const hw)2040 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
2041 {
2042 RTC_CRITICAL_SECTION_ENTER();
2043 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
2044 RTC_CRITICAL_SECTION_LEAVE();
2045 }
2046
hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void * const hw)2047 static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
2048 {
2049 RTC_CRITICAL_SECTION_ENTER();
2050 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
2051 RTC_CRITICAL_SECTION_LEAVE();
2052 }
2053
hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void * const hw)2054 static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
2055 {
2056 uint32_t tmp;
2057 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2058 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
2059 return (bool)tmp;
2060 }
2061
hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void * const hw,bool value)2062 static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
2063 {
2064 uint32_t tmp;
2065 RTC_CRITICAL_SECTION_ENTER();
2066 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2067 tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
2068 tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
2069 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2070 RTC_CRITICAL_SECTION_LEAVE();
2071 }
2072
hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void * const hw)2073 static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
2074 {
2075 RTC_CRITICAL_SECTION_ENTER();
2076 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
2077 RTC_CRITICAL_SECTION_LEAVE();
2078 }
2079
hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void * const hw)2080 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
2081 {
2082 RTC_CRITICAL_SECTION_ENTER();
2083 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
2084 RTC_CRITICAL_SECTION_LEAVE();
2085 }
2086
hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void * const hw)2087 static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
2088 {
2089 RTC_CRITICAL_SECTION_ENTER();
2090 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
2091 RTC_CRITICAL_SECTION_LEAVE();
2092 }
2093
hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void * const hw)2094 static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
2095 {
2096 uint32_t tmp;
2097 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2098 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
2099 return (bool)tmp;
2100 }
2101
hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void * const hw,bool value)2102 static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
2103 {
2104 uint32_t tmp;
2105 RTC_CRITICAL_SECTION_ENTER();
2106 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2107 tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
2108 tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
2109 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2110 RTC_CRITICAL_SECTION_LEAVE();
2111 }
2112
hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void * const hw)2113 static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
2114 {
2115 RTC_CRITICAL_SECTION_ENTER();
2116 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
2117 RTC_CRITICAL_SECTION_LEAVE();
2118 }
2119
hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void * const hw)2120 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
2121 {
2122 RTC_CRITICAL_SECTION_ENTER();
2123 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
2124 RTC_CRITICAL_SECTION_LEAVE();
2125 }
2126
hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void * const hw)2127 static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
2128 {
2129 RTC_CRITICAL_SECTION_ENTER();
2130 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
2131 RTC_CRITICAL_SECTION_LEAVE();
2132 }
2133
hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void * const hw)2134 static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
2135 {
2136 uint32_t tmp;
2137 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2138 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
2139 return (bool)tmp;
2140 }
2141
hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void * const hw,bool value)2142 static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
2143 {
2144 uint32_t tmp;
2145 RTC_CRITICAL_SECTION_ENTER();
2146 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2147 tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
2148 tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
2149 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2150 RTC_CRITICAL_SECTION_LEAVE();
2151 }
2152
hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void * const hw)2153 static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
2154 {
2155 RTC_CRITICAL_SECTION_ENTER();
2156 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
2157 RTC_CRITICAL_SECTION_LEAVE();
2158 }
2159
hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void * const hw)2160 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
2161 {
2162 RTC_CRITICAL_SECTION_ENTER();
2163 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
2164 RTC_CRITICAL_SECTION_LEAVE();
2165 }
2166
hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void * const hw)2167 static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
2168 {
2169 RTC_CRITICAL_SECTION_ENTER();
2170 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
2171 RTC_CRITICAL_SECTION_LEAVE();
2172 }
2173
hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void * const hw)2174 static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
2175 {
2176 uint32_t tmp;
2177 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2178 tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
2179 return (bool)tmp;
2180 }
2181
hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void * const hw,bool value)2182 static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
2183 {
2184 uint32_t tmp;
2185 RTC_CRITICAL_SECTION_ENTER();
2186 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2187 tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
2188 tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
2189 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2190 RTC_CRITICAL_SECTION_LEAVE();
2191 }
2192
hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void * const hw)2193 static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
2194 {
2195 RTC_CRITICAL_SECTION_ENTER();
2196 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
2197 RTC_CRITICAL_SECTION_LEAVE();
2198 }
2199
hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void * const hw)2200 static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
2201 {
2202 RTC_CRITICAL_SECTION_ENTER();
2203 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
2204 RTC_CRITICAL_SECTION_LEAVE();
2205 }
2206
hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void * const hw)2207 static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
2208 {
2209 RTC_CRITICAL_SECTION_ENTER();
2210 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
2211 RTC_CRITICAL_SECTION_LEAVE();
2212 }
2213
hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void * const hw)2214 static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
2215 {
2216 uint32_t tmp;
2217 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2218 tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
2219 return (bool)tmp;
2220 }
2221
hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void * const hw,bool value)2222 static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
2223 {
2224 uint32_t tmp;
2225 RTC_CRITICAL_SECTION_ENTER();
2226 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2227 tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
2228 tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
2229 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2230 RTC_CRITICAL_SECTION_LEAVE();
2231 }
2232
hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void * const hw)2233 static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
2234 {
2235 RTC_CRITICAL_SECTION_ENTER();
2236 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
2237 RTC_CRITICAL_SECTION_LEAVE();
2238 }
2239
hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void * const hw)2240 static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
2241 {
2242 RTC_CRITICAL_SECTION_ENTER();
2243 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
2244 RTC_CRITICAL_SECTION_LEAVE();
2245 }
2246
hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void * const hw)2247 static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
2248 {
2249 RTC_CRITICAL_SECTION_ENTER();
2250 ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
2251 RTC_CRITICAL_SECTION_LEAVE();
2252 }
2253
hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void * const hw)2254 static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
2255 {
2256 uint32_t tmp;
2257 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2258 tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
2259 return (bool)tmp;
2260 }
2261
hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void * const hw,bool value)2262 static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
2263 {
2264 uint32_t tmp;
2265 RTC_CRITICAL_SECTION_ENTER();
2266 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2267 tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
2268 tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
2269 ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
2270 RTC_CRITICAL_SECTION_LEAVE();
2271 }
2272
hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void * const hw)2273 static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
2274 {
2275 RTC_CRITICAL_SECTION_ENTER();
2276 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
2277 RTC_CRITICAL_SECTION_LEAVE();
2278 }
2279
hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void * const hw)2280 static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
2281 {
2282 RTC_CRITICAL_SECTION_ENTER();
2283 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
2284 RTC_CRITICAL_SECTION_LEAVE();
2285 }
2286
hri_rtcmode2_set_EVCTRL_reg(const void * const hw,hri_rtcmode2_evctrl_reg_t mask)2287 static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
2288 {
2289 RTC_CRITICAL_SECTION_ENTER();
2290 ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
2291 RTC_CRITICAL_SECTION_LEAVE();
2292 }
2293
hri_rtcmode2_get_EVCTRL_reg(const void * const hw,hri_rtcmode2_evctrl_reg_t mask)2294 static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw,
2295 hri_rtcmode2_evctrl_reg_t mask)
2296 {
2297 uint32_t tmp;
2298 tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
2299 tmp &= mask;
2300 return tmp;
2301 }
2302
hri_rtcmode2_write_EVCTRL_reg(const void * const hw,hri_rtcmode2_evctrl_reg_t data)2303 static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
2304 {
2305 RTC_CRITICAL_SECTION_ENTER();
2306 ((Rtc *)hw)->MODE2.EVCTRL.reg = data;
2307 RTC_CRITICAL_SECTION_LEAVE();
2308 }
2309
hri_rtcmode2_clear_EVCTRL_reg(const void * const hw,hri_rtcmode2_evctrl_reg_t mask)2310 static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
2311 {
2312 RTC_CRITICAL_SECTION_ENTER();
2313 ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
2314 RTC_CRITICAL_SECTION_LEAVE();
2315 }
2316
hri_rtcmode2_toggle_EVCTRL_reg(const void * const hw,hri_rtcmode2_evctrl_reg_t mask)2317 static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
2318 {
2319 RTC_CRITICAL_SECTION_ENTER();
2320 ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
2321 RTC_CRITICAL_SECTION_LEAVE();
2322 }
2323
hri_rtcmode2_read_EVCTRL_reg(const void * const hw)2324 static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
2325 {
2326 return ((Rtc *)hw)->MODE2.EVCTRL.reg;
2327 }
2328
hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void * const hw)2329 static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw)
2330 {
2331 RTC_CRITICAL_SECTION_ENTER();
2332 ((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
2333 RTC_CRITICAL_SECTION_LEAVE();
2334 }
2335
hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void * const hw)2336 static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw)
2337 {
2338 uint8_t tmp;
2339 tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
2340 tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
2341 return (bool)tmp;
2342 }
2343
hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)2344 static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
2345 {
2346 uint8_t tmp;
2347 RTC_CRITICAL_SECTION_ENTER();
2348 tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
2349 tmp &= ~RTC_DBGCTRL_DBGRUN;
2350 tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
2351 ((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp;
2352 RTC_CRITICAL_SECTION_LEAVE();
2353 }
2354
hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void * const hw)2355 static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
2356 {
2357 RTC_CRITICAL_SECTION_ENTER();
2358 ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
2359 RTC_CRITICAL_SECTION_LEAVE();
2360 }
2361
hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)2362 static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
2363 {
2364 RTC_CRITICAL_SECTION_ENTER();
2365 ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
2366 RTC_CRITICAL_SECTION_LEAVE();
2367 }
2368
hri_rtcmode2_set_DBGCTRL_reg(const void * const hw,hri_rtcmode2_dbgctrl_reg_t mask)2369 static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
2370 {
2371 RTC_CRITICAL_SECTION_ENTER();
2372 ((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask;
2373 RTC_CRITICAL_SECTION_LEAVE();
2374 }
2375
hri_rtcmode2_get_DBGCTRL_reg(const void * const hw,hri_rtcmode2_dbgctrl_reg_t mask)2376 static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const hw,
2377 hri_rtcmode2_dbgctrl_reg_t mask)
2378 {
2379 uint8_t tmp;
2380 tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg;
2381 tmp &= mask;
2382 return tmp;
2383 }
2384
hri_rtcmode2_write_DBGCTRL_reg(const void * const hw,hri_rtcmode2_dbgctrl_reg_t data)2385 static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data)
2386 {
2387 RTC_CRITICAL_SECTION_ENTER();
2388 ((Rtc *)hw)->MODE2.DBGCTRL.reg = data;
2389 RTC_CRITICAL_SECTION_LEAVE();
2390 }
2391
hri_rtcmode2_clear_DBGCTRL_reg(const void * const hw,hri_rtcmode2_dbgctrl_reg_t mask)2392 static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
2393 {
2394 RTC_CRITICAL_SECTION_ENTER();
2395 ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask;
2396 RTC_CRITICAL_SECTION_LEAVE();
2397 }
2398
hri_rtcmode2_toggle_DBGCTRL_reg(const void * const hw,hri_rtcmode2_dbgctrl_reg_t mask)2399 static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask)
2400 {
2401 RTC_CRITICAL_SECTION_ENTER();
2402 ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask;
2403 RTC_CRITICAL_SECTION_LEAVE();
2404 }
2405
hri_rtcmode2_read_DBGCTRL_reg(const void * const hw)2406 static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw)
2407 {
2408 return ((Rtc *)hw)->MODE2.DBGCTRL.reg;
2409 }
2410
hri_rtcmode2_set_FREQCORR_SIGN_bit(const void * const hw)2411 static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw)
2412 {
2413 RTC_CRITICAL_SECTION_ENTER();
2414 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2415 ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN;
2416 RTC_CRITICAL_SECTION_LEAVE();
2417 }
2418
hri_rtcmode2_get_FREQCORR_SIGN_bit(const void * const hw)2419 static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw)
2420 {
2421 uint8_t tmp;
2422 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2423 tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
2424 return (bool)tmp;
2425 }
2426
hri_rtcmode2_write_FREQCORR_SIGN_bit(const void * const hw,bool value)2427 static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
2428 {
2429 uint8_t tmp;
2430 RTC_CRITICAL_SECTION_ENTER();
2431 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2432 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2433 tmp &= ~RTC_FREQCORR_SIGN;
2434 tmp |= value << RTC_FREQCORR_SIGN_Pos;
2435 ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp;
2436 RTC_CRITICAL_SECTION_LEAVE();
2437 }
2438
hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void * const hw)2439 static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw)
2440 {
2441 RTC_CRITICAL_SECTION_ENTER();
2442 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2443 ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
2444 RTC_CRITICAL_SECTION_LEAVE();
2445 }
2446
hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void * const hw)2447 static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw)
2448 {
2449 RTC_CRITICAL_SECTION_ENTER();
2450 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2451 ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
2452 RTC_CRITICAL_SECTION_LEAVE();
2453 }
2454
hri_rtcmode2_set_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2455 static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2456 {
2457 RTC_CRITICAL_SECTION_ENTER();
2458 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2459 ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
2460 RTC_CRITICAL_SECTION_LEAVE();
2461 }
2462
hri_rtcmode2_get_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2463 static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const hw,
2464 hri_rtcmode2_freqcorr_reg_t mask)
2465 {
2466 uint8_t tmp;
2467 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2468 tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
2469 return tmp;
2470 }
2471
hri_rtcmode2_write_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode2_freqcorr_reg_t data)2472 static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data)
2473 {
2474 uint8_t tmp;
2475 RTC_CRITICAL_SECTION_ENTER();
2476 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2477 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2478 tmp &= ~RTC_FREQCORR_VALUE_Msk;
2479 tmp |= RTC_FREQCORR_VALUE(data);
2480 ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp;
2481 RTC_CRITICAL_SECTION_LEAVE();
2482 }
2483
hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2484 static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2485 {
2486 RTC_CRITICAL_SECTION_ENTER();
2487 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2488 ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
2489 RTC_CRITICAL_SECTION_LEAVE();
2490 }
2491
hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2492 static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2493 {
2494 RTC_CRITICAL_SECTION_ENTER();
2495 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2496 ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
2497 RTC_CRITICAL_SECTION_LEAVE();
2498 }
2499
hri_rtcmode2_read_FREQCORR_VALUE_bf(const void * const hw)2500 static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw)
2501 {
2502 uint8_t tmp;
2503 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2504 tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
2505 return tmp;
2506 }
2507
hri_rtcmode2_set_FREQCORR_reg(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2508 static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2509 {
2510 RTC_CRITICAL_SECTION_ENTER();
2511 ((Rtc *)hw)->MODE2.FREQCORR.reg |= mask;
2512 RTC_CRITICAL_SECTION_LEAVE();
2513 }
2514
hri_rtcmode2_get_FREQCORR_reg(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2515 static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const hw,
2516 hri_rtcmode2_freqcorr_reg_t mask)
2517 {
2518 uint8_t tmp;
2519 tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg;
2520 tmp &= mask;
2521 return tmp;
2522 }
2523
hri_rtcmode2_write_FREQCORR_reg(const void * const hw,hri_rtcmode2_freqcorr_reg_t data)2524 static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data)
2525 {
2526 RTC_CRITICAL_SECTION_ENTER();
2527 ((Rtc *)hw)->MODE2.FREQCORR.reg = data;
2528 RTC_CRITICAL_SECTION_LEAVE();
2529 }
2530
hri_rtcmode2_clear_FREQCORR_reg(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2531 static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2532 {
2533 RTC_CRITICAL_SECTION_ENTER();
2534 ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask;
2535 RTC_CRITICAL_SECTION_LEAVE();
2536 }
2537
hri_rtcmode2_toggle_FREQCORR_reg(const void * const hw,hri_rtcmode2_freqcorr_reg_t mask)2538 static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask)
2539 {
2540 RTC_CRITICAL_SECTION_ENTER();
2541 ((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask;
2542 RTC_CRITICAL_SECTION_LEAVE();
2543 }
2544
hri_rtcmode2_read_FREQCORR_reg(const void * const hw)2545 static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw)
2546 {
2547 return ((Rtc *)hw)->MODE2.FREQCORR.reg;
2548 }
2549
hri_rtcmode2_set_CLOCK_SECOND_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2550 static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2551 {
2552 RTC_CRITICAL_SECTION_ENTER();
2553 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2554 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
2555 RTC_CRITICAL_SECTION_LEAVE();
2556 }
2557
hri_rtcmode2_get_CLOCK_SECOND_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2558 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw,
2559 hri_rtcmode2_clock_reg_t mask)
2560 {
2561 uint32_t tmp;
2562 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2563 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2564 tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
2565 return tmp;
2566 }
2567
hri_rtcmode2_write_CLOCK_SECOND_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2568 static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2569 {
2570 uint32_t tmp;
2571 RTC_CRITICAL_SECTION_ENTER();
2572 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2573 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2574 tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
2575 tmp |= RTC_MODE2_CLOCK_SECOND(data);
2576 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2577 RTC_CRITICAL_SECTION_LEAVE();
2578 }
2579
hri_rtcmode2_clear_CLOCK_SECOND_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2580 static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2581 {
2582 RTC_CRITICAL_SECTION_ENTER();
2583 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2584 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
2585 RTC_CRITICAL_SECTION_LEAVE();
2586 }
2587
hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2588 static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2589 {
2590 RTC_CRITICAL_SECTION_ENTER();
2591 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2592 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
2593 RTC_CRITICAL_SECTION_LEAVE();
2594 }
2595
hri_rtcmode2_read_CLOCK_SECOND_bf(const void * const hw)2596 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
2597 {
2598 uint32_t tmp;
2599 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2600 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2601 tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
2602 return tmp;
2603 }
2604
hri_rtcmode2_set_CLOCK_MINUTE_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2605 static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2606 {
2607 RTC_CRITICAL_SECTION_ENTER();
2608 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2609 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
2610 RTC_CRITICAL_SECTION_LEAVE();
2611 }
2612
hri_rtcmode2_get_CLOCK_MINUTE_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2613 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw,
2614 hri_rtcmode2_clock_reg_t mask)
2615 {
2616 uint32_t tmp;
2617 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2618 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2619 tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
2620 return tmp;
2621 }
2622
hri_rtcmode2_write_CLOCK_MINUTE_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2623 static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2624 {
2625 uint32_t tmp;
2626 RTC_CRITICAL_SECTION_ENTER();
2627 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2628 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2629 tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
2630 tmp |= RTC_MODE2_CLOCK_MINUTE(data);
2631 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2632 RTC_CRITICAL_SECTION_LEAVE();
2633 }
2634
hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2635 static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2636 {
2637 RTC_CRITICAL_SECTION_ENTER();
2638 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2639 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
2640 RTC_CRITICAL_SECTION_LEAVE();
2641 }
2642
hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2643 static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2644 {
2645 RTC_CRITICAL_SECTION_ENTER();
2646 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2647 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
2648 RTC_CRITICAL_SECTION_LEAVE();
2649 }
2650
hri_rtcmode2_read_CLOCK_MINUTE_bf(const void * const hw)2651 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
2652 {
2653 uint32_t tmp;
2654 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2655 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2656 tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
2657 return tmp;
2658 }
2659
hri_rtcmode2_set_CLOCK_HOUR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2660 static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2661 {
2662 RTC_CRITICAL_SECTION_ENTER();
2663 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2664 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
2665 RTC_CRITICAL_SECTION_LEAVE();
2666 }
2667
hri_rtcmode2_get_CLOCK_HOUR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2668 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw,
2669 hri_rtcmode2_clock_reg_t mask)
2670 {
2671 uint32_t tmp;
2672 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2673 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2674 tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
2675 return tmp;
2676 }
2677
hri_rtcmode2_write_CLOCK_HOUR_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2678 static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2679 {
2680 uint32_t tmp;
2681 RTC_CRITICAL_SECTION_ENTER();
2682 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2683 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2684 tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
2685 tmp |= RTC_MODE2_CLOCK_HOUR(data);
2686 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2687 RTC_CRITICAL_SECTION_LEAVE();
2688 }
2689
hri_rtcmode2_clear_CLOCK_HOUR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2690 static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2691 {
2692 RTC_CRITICAL_SECTION_ENTER();
2693 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2694 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
2695 RTC_CRITICAL_SECTION_LEAVE();
2696 }
2697
hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2698 static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2699 {
2700 RTC_CRITICAL_SECTION_ENTER();
2701 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2702 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
2703 RTC_CRITICAL_SECTION_LEAVE();
2704 }
2705
hri_rtcmode2_read_CLOCK_HOUR_bf(const void * const hw)2706 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
2707 {
2708 uint32_t tmp;
2709 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2710 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2711 tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
2712 return tmp;
2713 }
2714
hri_rtcmode2_set_CLOCK_DAY_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2715 static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2716 {
2717 RTC_CRITICAL_SECTION_ENTER();
2718 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2719 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
2720 RTC_CRITICAL_SECTION_LEAVE();
2721 }
2722
hri_rtcmode2_get_CLOCK_DAY_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2723 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw,
2724 hri_rtcmode2_clock_reg_t mask)
2725 {
2726 uint32_t tmp;
2727 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2728 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2729 tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
2730 return tmp;
2731 }
2732
hri_rtcmode2_write_CLOCK_DAY_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2733 static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2734 {
2735 uint32_t tmp;
2736 RTC_CRITICAL_SECTION_ENTER();
2737 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2738 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2739 tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
2740 tmp |= RTC_MODE2_CLOCK_DAY(data);
2741 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2742 RTC_CRITICAL_SECTION_LEAVE();
2743 }
2744
hri_rtcmode2_clear_CLOCK_DAY_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2745 static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2746 {
2747 RTC_CRITICAL_SECTION_ENTER();
2748 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2749 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
2750 RTC_CRITICAL_SECTION_LEAVE();
2751 }
2752
hri_rtcmode2_toggle_CLOCK_DAY_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2753 static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2754 {
2755 RTC_CRITICAL_SECTION_ENTER();
2756 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2757 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
2758 RTC_CRITICAL_SECTION_LEAVE();
2759 }
2760
hri_rtcmode2_read_CLOCK_DAY_bf(const void * const hw)2761 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
2762 {
2763 uint32_t tmp;
2764 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2765 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2766 tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
2767 return tmp;
2768 }
2769
hri_rtcmode2_set_CLOCK_MONTH_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2770 static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2771 {
2772 RTC_CRITICAL_SECTION_ENTER();
2773 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2774 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
2775 RTC_CRITICAL_SECTION_LEAVE();
2776 }
2777
hri_rtcmode2_get_CLOCK_MONTH_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2778 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw,
2779 hri_rtcmode2_clock_reg_t mask)
2780 {
2781 uint32_t tmp;
2782 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2783 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2784 tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
2785 return tmp;
2786 }
2787
hri_rtcmode2_write_CLOCK_MONTH_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2788 static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2789 {
2790 uint32_t tmp;
2791 RTC_CRITICAL_SECTION_ENTER();
2792 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2793 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2794 tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
2795 tmp |= RTC_MODE2_CLOCK_MONTH(data);
2796 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2797 RTC_CRITICAL_SECTION_LEAVE();
2798 }
2799
hri_rtcmode2_clear_CLOCK_MONTH_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2800 static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2801 {
2802 RTC_CRITICAL_SECTION_ENTER();
2803 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2804 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
2805 RTC_CRITICAL_SECTION_LEAVE();
2806 }
2807
hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2808 static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2809 {
2810 RTC_CRITICAL_SECTION_ENTER();
2811 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2812 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
2813 RTC_CRITICAL_SECTION_LEAVE();
2814 }
2815
hri_rtcmode2_read_CLOCK_MONTH_bf(const void * const hw)2816 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
2817 {
2818 uint32_t tmp;
2819 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2820 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2821 tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
2822 return tmp;
2823 }
2824
hri_rtcmode2_set_CLOCK_YEAR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2825 static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2826 {
2827 RTC_CRITICAL_SECTION_ENTER();
2828 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2829 ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
2830 RTC_CRITICAL_SECTION_LEAVE();
2831 }
2832
hri_rtcmode2_get_CLOCK_YEAR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2833 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw,
2834 hri_rtcmode2_clock_reg_t mask)
2835 {
2836 uint32_t tmp;
2837 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2838 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2839 tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
2840 return tmp;
2841 }
2842
hri_rtcmode2_write_CLOCK_YEAR_bf(const void * const hw,hri_rtcmode2_clock_reg_t data)2843 static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
2844 {
2845 uint32_t tmp;
2846 RTC_CRITICAL_SECTION_ENTER();
2847 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2848 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2849 tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
2850 tmp |= RTC_MODE2_CLOCK_YEAR(data);
2851 ((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
2852 RTC_CRITICAL_SECTION_LEAVE();
2853 }
2854
hri_rtcmode2_clear_CLOCK_YEAR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2855 static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2856 {
2857 RTC_CRITICAL_SECTION_ENTER();
2858 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2859 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
2860 RTC_CRITICAL_SECTION_LEAVE();
2861 }
2862
hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void * const hw,hri_rtcmode2_clock_reg_t mask)2863 static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2864 {
2865 RTC_CRITICAL_SECTION_ENTER();
2866 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2867 ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
2868 RTC_CRITICAL_SECTION_LEAVE();
2869 }
2870
hri_rtcmode2_read_CLOCK_YEAR_bf(const void * const hw)2871 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
2872 {
2873 uint32_t tmp;
2874 hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
2875 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2876 tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
2877 return tmp;
2878 }
2879
hri_rtcmode2_set_CLOCK_reg(const void * const hw,hri_rtcmode2_clock_reg_t mask)2880 static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2881 {
2882 RTC_CRITICAL_SECTION_ENTER();
2883 ((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
2884 RTC_CRITICAL_SECTION_LEAVE();
2885 }
2886
hri_rtcmode2_get_CLOCK_reg(const void * const hw,hri_rtcmode2_clock_reg_t mask)2887 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2888 {
2889 uint32_t tmp;
2890 tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
2891 tmp &= mask;
2892 return tmp;
2893 }
2894
hri_rtcmode2_write_CLOCK_reg(const void * const hw,hri_rtcmode2_clock_reg_t data)2895 static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
2896 {
2897 RTC_CRITICAL_SECTION_ENTER();
2898 ((Rtc *)hw)->MODE2.CLOCK.reg = data;
2899 RTC_CRITICAL_SECTION_LEAVE();
2900 }
2901
hri_rtcmode2_clear_CLOCK_reg(const void * const hw,hri_rtcmode2_clock_reg_t mask)2902 static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2903 {
2904 RTC_CRITICAL_SECTION_ENTER();
2905 ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
2906 RTC_CRITICAL_SECTION_LEAVE();
2907 }
2908
hri_rtcmode2_toggle_CLOCK_reg(const void * const hw,hri_rtcmode2_clock_reg_t mask)2909 static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
2910 {
2911 RTC_CRITICAL_SECTION_ENTER();
2912 ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
2913 RTC_CRITICAL_SECTION_LEAVE();
2914 }
2915
hri_rtcmode2_read_CLOCK_reg(const void * const hw)2916 static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
2917 {
2918 return ((Rtc *)hw)->MODE2.CLOCK.reg;
2919 }
2920
hri_rtcmode2_set_GP_reg(const void * const hw,uint8_t index,hri_rtcmode2_gp_reg_t mask)2921 static inline void hri_rtcmode2_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask)
2922 {
2923 RTC_CRITICAL_SECTION_ENTER();
2924 ((Rtc *)hw)->MODE2.GP[index].reg |= mask;
2925 RTC_CRITICAL_SECTION_LEAVE();
2926 }
2927
hri_rtcmode2_get_GP_reg(const void * const hw,uint8_t index,hri_rtcmode2_gp_reg_t mask)2928 static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_reg(const void *const hw, uint8_t index,
2929 hri_rtcmode2_gp_reg_t mask)
2930 {
2931 uint32_t tmp;
2932 tmp = ((Rtc *)hw)->MODE2.GP[index].reg;
2933 tmp &= mask;
2934 return tmp;
2935 }
2936
hri_rtcmode2_write_GP_reg(const void * const hw,uint8_t index,hri_rtcmode2_gp_reg_t data)2937 static inline void hri_rtcmode2_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t data)
2938 {
2939 RTC_CRITICAL_SECTION_ENTER();
2940 ((Rtc *)hw)->MODE2.GP[index].reg = data;
2941 RTC_CRITICAL_SECTION_LEAVE();
2942 }
2943
hri_rtcmode2_clear_GP_reg(const void * const hw,uint8_t index,hri_rtcmode2_gp_reg_t mask)2944 static inline void hri_rtcmode2_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask)
2945 {
2946 RTC_CRITICAL_SECTION_ENTER();
2947 ((Rtc *)hw)->MODE2.GP[index].reg &= ~mask;
2948 RTC_CRITICAL_SECTION_LEAVE();
2949 }
2950
hri_rtcmode2_toggle_GP_reg(const void * const hw,uint8_t index,hri_rtcmode2_gp_reg_t mask)2951 static inline void hri_rtcmode2_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask)
2952 {
2953 RTC_CRITICAL_SECTION_ENTER();
2954 ((Rtc *)hw)->MODE2.GP[index].reg ^= mask;
2955 RTC_CRITICAL_SECTION_LEAVE();
2956 }
2957
hri_rtcmode2_read_GP_reg(const void * const hw,uint8_t index)2958 static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_read_GP_reg(const void *const hw, uint8_t index)
2959 {
2960 return ((Rtc *)hw)->MODE2.GP[index].reg;
2961 }
2962
hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void * const hw)2963 static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
2964 {
2965 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
2966 }
2967
hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void * const hw)2968 static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
2969 {
2970 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
2971 }
2972
hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void * const hw)2973 static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
2974 {
2975 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
2976 }
2977
hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void * const hw)2978 static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
2979 {
2980 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
2981 }
2982
hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void * const hw)2983 static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
2984 {
2985 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
2986 }
2987
hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void * const hw)2988 static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
2989 {
2990 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
2991 }
2992
hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void * const hw)2993 static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
2994 {
2995 return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
2996 }
2997
hri_rtcmode2_get_SYNCBUSY_reg(const void * const hw,hri_rtcmode2_syncbusy_reg_t mask)2998 static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw,
2999 hri_rtcmode2_syncbusy_reg_t mask)
3000 {
3001 uint32_t tmp;
3002 tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
3003 tmp &= mask;
3004 return tmp;
3005 }
3006
hri_rtcmode2_read_SYNCBUSY_reg(const void * const hw)3007 static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
3008 {
3009 return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
3010 }
3011
hri_rtcmode0_set_INTEN_PER0_bit(const void * const hw)3012 static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
3013 {
3014 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
3015 }
3016
hri_rtcmode0_get_INTEN_PER0_bit(const void * const hw)3017 static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
3018 {
3019 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
3020 }
3021
hri_rtcmode0_write_INTEN_PER0_bit(const void * const hw,bool value)3022 static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
3023 {
3024 if (value == 0x0) {
3025 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
3026 } else {
3027 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
3028 }
3029 }
3030
hri_rtcmode0_clear_INTEN_PER0_bit(const void * const hw)3031 static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
3032 {
3033 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
3034 }
3035
hri_rtcmode0_set_INTEN_PER1_bit(const void * const hw)3036 static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
3037 {
3038 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
3039 }
3040
hri_rtcmode0_get_INTEN_PER1_bit(const void * const hw)3041 static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
3042 {
3043 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
3044 }
3045
hri_rtcmode0_write_INTEN_PER1_bit(const void * const hw,bool value)3046 static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
3047 {
3048 if (value == 0x0) {
3049 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
3050 } else {
3051 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
3052 }
3053 }
3054
hri_rtcmode0_clear_INTEN_PER1_bit(const void * const hw)3055 static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
3056 {
3057 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
3058 }
3059
hri_rtcmode0_set_INTEN_PER2_bit(const void * const hw)3060 static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
3061 {
3062 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
3063 }
3064
hri_rtcmode0_get_INTEN_PER2_bit(const void * const hw)3065 static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
3066 {
3067 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
3068 }
3069
hri_rtcmode0_write_INTEN_PER2_bit(const void * const hw,bool value)3070 static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
3071 {
3072 if (value == 0x0) {
3073 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
3074 } else {
3075 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
3076 }
3077 }
3078
hri_rtcmode0_clear_INTEN_PER2_bit(const void * const hw)3079 static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
3080 {
3081 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
3082 }
3083
hri_rtcmode0_set_INTEN_PER3_bit(const void * const hw)3084 static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
3085 {
3086 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
3087 }
3088
hri_rtcmode0_get_INTEN_PER3_bit(const void * const hw)3089 static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
3090 {
3091 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
3092 }
3093
hri_rtcmode0_write_INTEN_PER3_bit(const void * const hw,bool value)3094 static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
3095 {
3096 if (value == 0x0) {
3097 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
3098 } else {
3099 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
3100 }
3101 }
3102
hri_rtcmode0_clear_INTEN_PER3_bit(const void * const hw)3103 static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
3104 {
3105 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
3106 }
3107
hri_rtcmode0_set_INTEN_PER4_bit(const void * const hw)3108 static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
3109 {
3110 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
3111 }
3112
hri_rtcmode0_get_INTEN_PER4_bit(const void * const hw)3113 static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
3114 {
3115 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
3116 }
3117
hri_rtcmode0_write_INTEN_PER4_bit(const void * const hw,bool value)3118 static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
3119 {
3120 if (value == 0x0) {
3121 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
3122 } else {
3123 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
3124 }
3125 }
3126
hri_rtcmode0_clear_INTEN_PER4_bit(const void * const hw)3127 static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
3128 {
3129 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
3130 }
3131
hri_rtcmode0_set_INTEN_PER5_bit(const void * const hw)3132 static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
3133 {
3134 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
3135 }
3136
hri_rtcmode0_get_INTEN_PER5_bit(const void * const hw)3137 static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
3138 {
3139 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
3140 }
3141
hri_rtcmode0_write_INTEN_PER5_bit(const void * const hw,bool value)3142 static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
3143 {
3144 if (value == 0x0) {
3145 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
3146 } else {
3147 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
3148 }
3149 }
3150
hri_rtcmode0_clear_INTEN_PER5_bit(const void * const hw)3151 static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
3152 {
3153 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
3154 }
3155
hri_rtcmode0_set_INTEN_PER6_bit(const void * const hw)3156 static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
3157 {
3158 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
3159 }
3160
hri_rtcmode0_get_INTEN_PER6_bit(const void * const hw)3161 static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
3162 {
3163 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
3164 }
3165
hri_rtcmode0_write_INTEN_PER6_bit(const void * const hw,bool value)3166 static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
3167 {
3168 if (value == 0x0) {
3169 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
3170 } else {
3171 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
3172 }
3173 }
3174
hri_rtcmode0_clear_INTEN_PER6_bit(const void * const hw)3175 static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
3176 {
3177 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
3178 }
3179
hri_rtcmode0_set_INTEN_PER7_bit(const void * const hw)3180 static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
3181 {
3182 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
3183 }
3184
hri_rtcmode0_get_INTEN_PER7_bit(const void * const hw)3185 static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
3186 {
3187 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
3188 }
3189
hri_rtcmode0_write_INTEN_PER7_bit(const void * const hw,bool value)3190 static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
3191 {
3192 if (value == 0x0) {
3193 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
3194 } else {
3195 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
3196 }
3197 }
3198
hri_rtcmode0_clear_INTEN_PER7_bit(const void * const hw)3199 static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
3200 {
3201 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
3202 }
3203
hri_rtcmode0_set_INTEN_CMP0_bit(const void * const hw)3204 static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
3205 {
3206 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
3207 }
3208
hri_rtcmode0_get_INTEN_CMP0_bit(const void * const hw)3209 static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
3210 {
3211 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
3212 }
3213
hri_rtcmode0_write_INTEN_CMP0_bit(const void * const hw,bool value)3214 static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
3215 {
3216 if (value == 0x0) {
3217 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
3218 } else {
3219 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
3220 }
3221 }
3222
hri_rtcmode0_clear_INTEN_CMP0_bit(const void * const hw)3223 static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
3224 {
3225 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
3226 }
3227
hri_rtcmode0_set_INTEN_OVF_bit(const void * const hw)3228 static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
3229 {
3230 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
3231 }
3232
hri_rtcmode0_get_INTEN_OVF_bit(const void * const hw)3233 static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
3234 {
3235 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
3236 }
3237
hri_rtcmode0_write_INTEN_OVF_bit(const void * const hw,bool value)3238 static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
3239 {
3240 if (value == 0x0) {
3241 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
3242 } else {
3243 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
3244 }
3245 }
3246
hri_rtcmode0_clear_INTEN_OVF_bit(const void * const hw)3247 static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
3248 {
3249 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
3250 }
3251
hri_rtcmode0_set_INTEN_reg(const void * const hw,hri_rtcmode0_intenset_reg_t mask)3252 static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
3253 {
3254 ((Rtc *)hw)->MODE0.INTENSET.reg = mask;
3255 }
3256
hri_rtcmode0_get_INTEN_reg(const void * const hw,hri_rtcmode0_intenset_reg_t mask)3257 static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw,
3258 hri_rtcmode0_intenset_reg_t mask)
3259 {
3260 uint16_t tmp;
3261 tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
3262 tmp &= mask;
3263 return tmp;
3264 }
3265
hri_rtcmode0_read_INTEN_reg(const void * const hw)3266 static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
3267 {
3268 return ((Rtc *)hw)->MODE0.INTENSET.reg;
3269 }
3270
hri_rtcmode0_write_INTEN_reg(const void * const hw,hri_rtcmode0_intenset_reg_t data)3271 static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
3272 {
3273 ((Rtc *)hw)->MODE0.INTENSET.reg = data;
3274 ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
3275 }
3276
hri_rtcmode0_clear_INTEN_reg(const void * const hw,hri_rtcmode0_intenset_reg_t mask)3277 static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
3278 {
3279 ((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
3280 }
3281
hri_rtcmode0_get_INTFLAG_PER0_bit(const void * const hw)3282 static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
3283 {
3284 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
3285 }
3286
hri_rtcmode0_clear_INTFLAG_PER0_bit(const void * const hw)3287 static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
3288 {
3289 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
3290 }
3291
hri_rtcmode0_get_INTFLAG_PER1_bit(const void * const hw)3292 static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
3293 {
3294 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
3295 }
3296
hri_rtcmode0_clear_INTFLAG_PER1_bit(const void * const hw)3297 static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
3298 {
3299 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
3300 }
3301
hri_rtcmode0_get_INTFLAG_PER2_bit(const void * const hw)3302 static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
3303 {
3304 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
3305 }
3306
hri_rtcmode0_clear_INTFLAG_PER2_bit(const void * const hw)3307 static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
3308 {
3309 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
3310 }
3311
hri_rtcmode0_get_INTFLAG_PER3_bit(const void * const hw)3312 static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
3313 {
3314 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
3315 }
3316
hri_rtcmode0_clear_INTFLAG_PER3_bit(const void * const hw)3317 static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
3318 {
3319 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
3320 }
3321
hri_rtcmode0_get_INTFLAG_PER4_bit(const void * const hw)3322 static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
3323 {
3324 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
3325 }
3326
hri_rtcmode0_clear_INTFLAG_PER4_bit(const void * const hw)3327 static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
3328 {
3329 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
3330 }
3331
hri_rtcmode0_get_INTFLAG_PER5_bit(const void * const hw)3332 static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
3333 {
3334 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
3335 }
3336
hri_rtcmode0_clear_INTFLAG_PER5_bit(const void * const hw)3337 static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
3338 {
3339 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
3340 }
3341
hri_rtcmode0_get_INTFLAG_PER6_bit(const void * const hw)3342 static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
3343 {
3344 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
3345 }
3346
hri_rtcmode0_clear_INTFLAG_PER6_bit(const void * const hw)3347 static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
3348 {
3349 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
3350 }
3351
hri_rtcmode0_get_INTFLAG_PER7_bit(const void * const hw)3352 static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
3353 {
3354 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
3355 }
3356
hri_rtcmode0_clear_INTFLAG_PER7_bit(const void * const hw)3357 static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
3358 {
3359 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
3360 }
3361
hri_rtcmode0_get_INTFLAG_CMP0_bit(const void * const hw)3362 static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
3363 {
3364 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
3365 }
3366
hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void * const hw)3367 static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
3368 {
3369 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
3370 }
3371
hri_rtcmode0_get_INTFLAG_OVF_bit(const void * const hw)3372 static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
3373 {
3374 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
3375 }
3376
hri_rtcmode0_clear_INTFLAG_OVF_bit(const void * const hw)3377 static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
3378 {
3379 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
3380 }
3381
hri_rtcmode0_get_interrupt_PER0_bit(const void * const hw)3382 static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
3383 {
3384 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
3385 }
3386
hri_rtcmode0_clear_interrupt_PER0_bit(const void * const hw)3387 static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
3388 {
3389 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
3390 }
3391
hri_rtcmode0_get_interrupt_PER1_bit(const void * const hw)3392 static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
3393 {
3394 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
3395 }
3396
hri_rtcmode0_clear_interrupt_PER1_bit(const void * const hw)3397 static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
3398 {
3399 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
3400 }
3401
hri_rtcmode0_get_interrupt_PER2_bit(const void * const hw)3402 static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
3403 {
3404 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
3405 }
3406
hri_rtcmode0_clear_interrupt_PER2_bit(const void * const hw)3407 static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
3408 {
3409 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
3410 }
3411
hri_rtcmode0_get_interrupt_PER3_bit(const void * const hw)3412 static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
3413 {
3414 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
3415 }
3416
hri_rtcmode0_clear_interrupt_PER3_bit(const void * const hw)3417 static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
3418 {
3419 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
3420 }
3421
hri_rtcmode0_get_interrupt_PER4_bit(const void * const hw)3422 static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
3423 {
3424 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
3425 }
3426
hri_rtcmode0_clear_interrupt_PER4_bit(const void * const hw)3427 static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
3428 {
3429 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
3430 }
3431
hri_rtcmode0_get_interrupt_PER5_bit(const void * const hw)3432 static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
3433 {
3434 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
3435 }
3436
hri_rtcmode0_clear_interrupt_PER5_bit(const void * const hw)3437 static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
3438 {
3439 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
3440 }
3441
hri_rtcmode0_get_interrupt_PER6_bit(const void * const hw)3442 static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
3443 {
3444 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
3445 }
3446
hri_rtcmode0_clear_interrupt_PER6_bit(const void * const hw)3447 static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
3448 {
3449 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
3450 }
3451
hri_rtcmode0_get_interrupt_PER7_bit(const void * const hw)3452 static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
3453 {
3454 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
3455 }
3456
hri_rtcmode0_clear_interrupt_PER7_bit(const void * const hw)3457 static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
3458 {
3459 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
3460 }
3461
hri_rtcmode0_get_interrupt_CMP0_bit(const void * const hw)3462 static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
3463 {
3464 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
3465 }
3466
hri_rtcmode0_clear_interrupt_CMP0_bit(const void * const hw)3467 static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
3468 {
3469 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
3470 }
3471
hri_rtcmode0_get_interrupt_OVF_bit(const void * const hw)3472 static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
3473 {
3474 return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
3475 }
3476
hri_rtcmode0_clear_interrupt_OVF_bit(const void * const hw)3477 static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
3478 {
3479 ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
3480 }
3481
hri_rtcmode0_get_INTFLAG_reg(const void * const hw,hri_rtcmode0_intflag_reg_t mask)3482 static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw,
3483 hri_rtcmode0_intflag_reg_t mask)
3484 {
3485 uint16_t tmp;
3486 tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
3487 tmp &= mask;
3488 return tmp;
3489 }
3490
hri_rtcmode0_read_INTFLAG_reg(const void * const hw)3491 static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
3492 {
3493 return ((Rtc *)hw)->MODE0.INTFLAG.reg;
3494 }
3495
hri_rtcmode0_clear_INTFLAG_reg(const void * const hw,hri_rtcmode0_intflag_reg_t mask)3496 static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
3497 {
3498 ((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
3499 }
3500
hri_rtcmode0_set_CTRLA_SWRST_bit(const void * const hw)3501 static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
3502 {
3503 RTC_CRITICAL_SECTION_ENTER();
3504 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
3505 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
3506 RTC_CRITICAL_SECTION_LEAVE();
3507 }
3508
hri_rtcmode0_get_CTRLA_SWRST_bit(const void * const hw)3509 static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
3510 {
3511 uint16_t tmp;
3512 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
3513 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3514 tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
3515 return (bool)tmp;
3516 }
3517
hri_rtcmode0_set_CTRLA_ENABLE_bit(const void * const hw)3518 static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
3519 {
3520 RTC_CRITICAL_SECTION_ENTER();
3521 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3522 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
3523 RTC_CRITICAL_SECTION_LEAVE();
3524 }
3525
hri_rtcmode0_get_CTRLA_ENABLE_bit(const void * const hw)3526 static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
3527 {
3528 uint16_t tmp;
3529 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3530 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3531 tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
3532 return (bool)tmp;
3533 }
3534
hri_rtcmode0_write_CTRLA_ENABLE_bit(const void * const hw,bool value)3535 static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
3536 {
3537 uint16_t tmp;
3538 RTC_CRITICAL_SECTION_ENTER();
3539 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3540 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3541 tmp &= ~RTC_MODE0_CTRLA_ENABLE;
3542 tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
3543 ((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
3544 RTC_CRITICAL_SECTION_LEAVE();
3545 }
3546
hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void * const hw)3547 static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
3548 {
3549 RTC_CRITICAL_SECTION_ENTER();
3550 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3551 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
3552 RTC_CRITICAL_SECTION_LEAVE();
3553 }
3554
hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void * const hw)3555 static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
3556 {
3557 RTC_CRITICAL_SECTION_ENTER();
3558 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3559 ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
3560 RTC_CRITICAL_SECTION_LEAVE();
3561 }
3562
hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void * const hw)3563 static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
3564 {
3565 RTC_CRITICAL_SECTION_ENTER();
3566 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3567 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
3568 RTC_CRITICAL_SECTION_LEAVE();
3569 }
3570
hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void * const hw)3571 static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
3572 {
3573 uint16_t tmp;
3574 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3575 tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
3576 return (bool)tmp;
3577 }
3578
hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void * const hw,bool value)3579 static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
3580 {
3581 uint16_t tmp;
3582 RTC_CRITICAL_SECTION_ENTER();
3583 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3584 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3585 tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
3586 tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
3587 ((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
3588 RTC_CRITICAL_SECTION_LEAVE();
3589 }
3590
hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void * const hw)3591 static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
3592 {
3593 RTC_CRITICAL_SECTION_ENTER();
3594 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3595 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
3596 RTC_CRITICAL_SECTION_LEAVE();
3597 }
3598
hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void * const hw)3599 static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
3600 {
3601 RTC_CRITICAL_SECTION_ENTER();
3602 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3603 ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
3604 RTC_CRITICAL_SECTION_LEAVE();
3605 }
3606
hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void * const hw)3607 static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
3608 {
3609 RTC_CRITICAL_SECTION_ENTER();
3610 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3611 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
3612 RTC_CRITICAL_SECTION_LEAVE();
3613 }
3614
hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void * const hw)3615 static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
3616 {
3617 uint16_t tmp;
3618 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3619 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3620 tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
3621 return (bool)tmp;
3622 }
3623
hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void * const hw,bool value)3624 static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
3625 {
3626 uint16_t tmp;
3627 RTC_CRITICAL_SECTION_ENTER();
3628 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3629 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3630 tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
3631 tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
3632 ((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
3633 RTC_CRITICAL_SECTION_LEAVE();
3634 }
3635
hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void * const hw)3636 static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
3637 {
3638 RTC_CRITICAL_SECTION_ENTER();
3639 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3640 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
3641 RTC_CRITICAL_SECTION_LEAVE();
3642 }
3643
hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void * const hw)3644 static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
3645 {
3646 RTC_CRITICAL_SECTION_ENTER();
3647 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
3648 ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
3649 RTC_CRITICAL_SECTION_LEAVE();
3650 }
3651
hri_rtcmode0_set_CTRLA_MODE_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3652 static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3653 {
3654 RTC_CRITICAL_SECTION_ENTER();
3655 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3656 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
3657 RTC_CRITICAL_SECTION_LEAVE();
3658 }
3659
hri_rtcmode0_get_CTRLA_MODE_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3660 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw,
3661 hri_rtcmode0_ctrla_reg_t mask)
3662 {
3663 uint16_t tmp;
3664 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3665 tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
3666 return tmp;
3667 }
3668
hri_rtcmode0_write_CTRLA_MODE_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t data)3669 static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
3670 {
3671 uint16_t tmp;
3672 RTC_CRITICAL_SECTION_ENTER();
3673 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3674 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3675 tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
3676 tmp |= RTC_MODE0_CTRLA_MODE(data);
3677 ((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
3678 RTC_CRITICAL_SECTION_LEAVE();
3679 }
3680
hri_rtcmode0_clear_CTRLA_MODE_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3681 static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3682 {
3683 RTC_CRITICAL_SECTION_ENTER();
3684 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3685 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
3686 RTC_CRITICAL_SECTION_LEAVE();
3687 }
3688
hri_rtcmode0_toggle_CTRLA_MODE_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3689 static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3690 {
3691 RTC_CRITICAL_SECTION_ENTER();
3692 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3693 ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
3694 RTC_CRITICAL_SECTION_LEAVE();
3695 }
3696
hri_rtcmode0_read_CTRLA_MODE_bf(const void * const hw)3697 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
3698 {
3699 uint16_t tmp;
3700 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3701 tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
3702 return tmp;
3703 }
3704
hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3705 static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3706 {
3707 RTC_CRITICAL_SECTION_ENTER();
3708 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3709 ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
3710 RTC_CRITICAL_SECTION_LEAVE();
3711 }
3712
hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3713 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw,
3714 hri_rtcmode0_ctrla_reg_t mask)
3715 {
3716 uint16_t tmp;
3717 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3718 tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
3719 return tmp;
3720 }
3721
hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t data)3722 static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
3723 {
3724 uint16_t tmp;
3725 RTC_CRITICAL_SECTION_ENTER();
3726 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3727 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3728 tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
3729 tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
3730 ((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
3731 RTC_CRITICAL_SECTION_LEAVE();
3732 }
3733
hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3734 static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3735 {
3736 RTC_CRITICAL_SECTION_ENTER();
3737 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3738 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
3739 RTC_CRITICAL_SECTION_LEAVE();
3740 }
3741
hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3742 static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3743 {
3744 RTC_CRITICAL_SECTION_ENTER();
3745 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
3746 ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
3747 RTC_CRITICAL_SECTION_LEAVE();
3748 }
3749
hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void * const hw)3750 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
3751 {
3752 uint16_t tmp;
3753 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3754 tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
3755 return tmp;
3756 }
3757
hri_rtcmode0_set_CTRLA_reg(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3758 static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3759 {
3760 RTC_CRITICAL_SECTION_ENTER();
3761 ((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
3762 RTC_CRITICAL_SECTION_LEAVE();
3763 }
3764
hri_rtcmode0_get_CTRLA_reg(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3765 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3766 {
3767 uint16_t tmp;
3768 tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
3769 tmp &= mask;
3770 return tmp;
3771 }
3772
hri_rtcmode0_write_CTRLA_reg(const void * const hw,hri_rtcmode0_ctrla_reg_t data)3773 static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
3774 {
3775 RTC_CRITICAL_SECTION_ENTER();
3776 ((Rtc *)hw)->MODE0.CTRLA.reg = data;
3777 RTC_CRITICAL_SECTION_LEAVE();
3778 }
3779
hri_rtcmode0_clear_CTRLA_reg(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3780 static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3781 {
3782 RTC_CRITICAL_SECTION_ENTER();
3783 ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
3784 RTC_CRITICAL_SECTION_LEAVE();
3785 }
3786
hri_rtcmode0_toggle_CTRLA_reg(const void * const hw,hri_rtcmode0_ctrla_reg_t mask)3787 static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
3788 {
3789 RTC_CRITICAL_SECTION_ENTER();
3790 ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
3791 RTC_CRITICAL_SECTION_LEAVE();
3792 }
3793
hri_rtcmode0_read_CTRLA_reg(const void * const hw)3794 static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
3795 {
3796 return ((Rtc *)hw)->MODE0.CTRLA.reg;
3797 }
3798
hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void * const hw)3799 static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
3800 {
3801 RTC_CRITICAL_SECTION_ENTER();
3802 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
3803 RTC_CRITICAL_SECTION_LEAVE();
3804 }
3805
hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void * const hw)3806 static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
3807 {
3808 uint32_t tmp;
3809 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3810 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
3811 return (bool)tmp;
3812 }
3813
hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void * const hw,bool value)3814 static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
3815 {
3816 uint32_t tmp;
3817 RTC_CRITICAL_SECTION_ENTER();
3818 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3819 tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
3820 tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
3821 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
3822 RTC_CRITICAL_SECTION_LEAVE();
3823 }
3824
hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void * const hw)3825 static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
3826 {
3827 RTC_CRITICAL_SECTION_ENTER();
3828 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
3829 RTC_CRITICAL_SECTION_LEAVE();
3830 }
3831
hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void * const hw)3832 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
3833 {
3834 RTC_CRITICAL_SECTION_ENTER();
3835 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
3836 RTC_CRITICAL_SECTION_LEAVE();
3837 }
3838
hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void * const hw)3839 static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
3840 {
3841 RTC_CRITICAL_SECTION_ENTER();
3842 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
3843 RTC_CRITICAL_SECTION_LEAVE();
3844 }
3845
hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void * const hw)3846 static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
3847 {
3848 uint32_t tmp;
3849 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3850 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
3851 return (bool)tmp;
3852 }
3853
hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void * const hw,bool value)3854 static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
3855 {
3856 uint32_t tmp;
3857 RTC_CRITICAL_SECTION_ENTER();
3858 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3859 tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
3860 tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
3861 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
3862 RTC_CRITICAL_SECTION_LEAVE();
3863 }
3864
hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void * const hw)3865 static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
3866 {
3867 RTC_CRITICAL_SECTION_ENTER();
3868 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
3869 RTC_CRITICAL_SECTION_LEAVE();
3870 }
3871
hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void * const hw)3872 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
3873 {
3874 RTC_CRITICAL_SECTION_ENTER();
3875 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
3876 RTC_CRITICAL_SECTION_LEAVE();
3877 }
3878
hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void * const hw)3879 static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
3880 {
3881 RTC_CRITICAL_SECTION_ENTER();
3882 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
3883 RTC_CRITICAL_SECTION_LEAVE();
3884 }
3885
hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void * const hw)3886 static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
3887 {
3888 uint32_t tmp;
3889 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3890 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
3891 return (bool)tmp;
3892 }
3893
hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void * const hw,bool value)3894 static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
3895 {
3896 uint32_t tmp;
3897 RTC_CRITICAL_SECTION_ENTER();
3898 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3899 tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
3900 tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
3901 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
3902 RTC_CRITICAL_SECTION_LEAVE();
3903 }
3904
hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void * const hw)3905 static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
3906 {
3907 RTC_CRITICAL_SECTION_ENTER();
3908 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
3909 RTC_CRITICAL_SECTION_LEAVE();
3910 }
3911
hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void * const hw)3912 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
3913 {
3914 RTC_CRITICAL_SECTION_ENTER();
3915 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
3916 RTC_CRITICAL_SECTION_LEAVE();
3917 }
3918
hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void * const hw)3919 static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
3920 {
3921 RTC_CRITICAL_SECTION_ENTER();
3922 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
3923 RTC_CRITICAL_SECTION_LEAVE();
3924 }
3925
hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void * const hw)3926 static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
3927 {
3928 uint32_t tmp;
3929 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3930 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
3931 return (bool)tmp;
3932 }
3933
hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void * const hw,bool value)3934 static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
3935 {
3936 uint32_t tmp;
3937 RTC_CRITICAL_SECTION_ENTER();
3938 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3939 tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
3940 tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
3941 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
3942 RTC_CRITICAL_SECTION_LEAVE();
3943 }
3944
hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void * const hw)3945 static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
3946 {
3947 RTC_CRITICAL_SECTION_ENTER();
3948 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
3949 RTC_CRITICAL_SECTION_LEAVE();
3950 }
3951
hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void * const hw)3952 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
3953 {
3954 RTC_CRITICAL_SECTION_ENTER();
3955 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
3956 RTC_CRITICAL_SECTION_LEAVE();
3957 }
3958
hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void * const hw)3959 static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
3960 {
3961 RTC_CRITICAL_SECTION_ENTER();
3962 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
3963 RTC_CRITICAL_SECTION_LEAVE();
3964 }
3965
hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void * const hw)3966 static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
3967 {
3968 uint32_t tmp;
3969 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3970 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
3971 return (bool)tmp;
3972 }
3973
hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void * const hw,bool value)3974 static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
3975 {
3976 uint32_t tmp;
3977 RTC_CRITICAL_SECTION_ENTER();
3978 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
3979 tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
3980 tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
3981 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
3982 RTC_CRITICAL_SECTION_LEAVE();
3983 }
3984
hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void * const hw)3985 static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
3986 {
3987 RTC_CRITICAL_SECTION_ENTER();
3988 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
3989 RTC_CRITICAL_SECTION_LEAVE();
3990 }
3991
hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void * const hw)3992 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
3993 {
3994 RTC_CRITICAL_SECTION_ENTER();
3995 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
3996 RTC_CRITICAL_SECTION_LEAVE();
3997 }
3998
hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void * const hw)3999 static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
4000 {
4001 RTC_CRITICAL_SECTION_ENTER();
4002 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
4003 RTC_CRITICAL_SECTION_LEAVE();
4004 }
4005
hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void * const hw)4006 static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
4007 {
4008 uint32_t tmp;
4009 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4010 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
4011 return (bool)tmp;
4012 }
4013
hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void * const hw,bool value)4014 static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
4015 {
4016 uint32_t tmp;
4017 RTC_CRITICAL_SECTION_ENTER();
4018 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4019 tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
4020 tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
4021 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
4022 RTC_CRITICAL_SECTION_LEAVE();
4023 }
4024
hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void * const hw)4025 static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
4026 {
4027 RTC_CRITICAL_SECTION_ENTER();
4028 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
4029 RTC_CRITICAL_SECTION_LEAVE();
4030 }
4031
hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void * const hw)4032 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
4033 {
4034 RTC_CRITICAL_SECTION_ENTER();
4035 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
4036 RTC_CRITICAL_SECTION_LEAVE();
4037 }
4038
hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void * const hw)4039 static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
4040 {
4041 RTC_CRITICAL_SECTION_ENTER();
4042 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
4043 RTC_CRITICAL_SECTION_LEAVE();
4044 }
4045
hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void * const hw)4046 static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
4047 {
4048 uint32_t tmp;
4049 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4050 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
4051 return (bool)tmp;
4052 }
4053
hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void * const hw,bool value)4054 static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
4055 {
4056 uint32_t tmp;
4057 RTC_CRITICAL_SECTION_ENTER();
4058 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4059 tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
4060 tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
4061 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
4062 RTC_CRITICAL_SECTION_LEAVE();
4063 }
4064
hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void * const hw)4065 static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
4066 {
4067 RTC_CRITICAL_SECTION_ENTER();
4068 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
4069 RTC_CRITICAL_SECTION_LEAVE();
4070 }
4071
hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void * const hw)4072 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
4073 {
4074 RTC_CRITICAL_SECTION_ENTER();
4075 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
4076 RTC_CRITICAL_SECTION_LEAVE();
4077 }
4078
hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void * const hw)4079 static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
4080 {
4081 RTC_CRITICAL_SECTION_ENTER();
4082 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
4083 RTC_CRITICAL_SECTION_LEAVE();
4084 }
4085
hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void * const hw)4086 static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
4087 {
4088 uint32_t tmp;
4089 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4090 tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
4091 return (bool)tmp;
4092 }
4093
hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void * const hw,bool value)4094 static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
4095 {
4096 uint32_t tmp;
4097 RTC_CRITICAL_SECTION_ENTER();
4098 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4099 tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
4100 tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
4101 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
4102 RTC_CRITICAL_SECTION_LEAVE();
4103 }
4104
hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void * const hw)4105 static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
4106 {
4107 RTC_CRITICAL_SECTION_ENTER();
4108 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
4109 RTC_CRITICAL_SECTION_LEAVE();
4110 }
4111
hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void * const hw)4112 static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
4113 {
4114 RTC_CRITICAL_SECTION_ENTER();
4115 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
4116 RTC_CRITICAL_SECTION_LEAVE();
4117 }
4118
hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void * const hw)4119 static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
4120 {
4121 RTC_CRITICAL_SECTION_ENTER();
4122 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
4123 RTC_CRITICAL_SECTION_LEAVE();
4124 }
4125
hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void * const hw)4126 static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
4127 {
4128 uint32_t tmp;
4129 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4130 tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
4131 return (bool)tmp;
4132 }
4133
hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void * const hw,bool value)4134 static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
4135 {
4136 uint32_t tmp;
4137 RTC_CRITICAL_SECTION_ENTER();
4138 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4139 tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
4140 tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
4141 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
4142 RTC_CRITICAL_SECTION_LEAVE();
4143 }
4144
hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void * const hw)4145 static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
4146 {
4147 RTC_CRITICAL_SECTION_ENTER();
4148 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
4149 RTC_CRITICAL_SECTION_LEAVE();
4150 }
4151
hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void * const hw)4152 static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
4153 {
4154 RTC_CRITICAL_SECTION_ENTER();
4155 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
4156 RTC_CRITICAL_SECTION_LEAVE();
4157 }
4158
hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void * const hw)4159 static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
4160 {
4161 RTC_CRITICAL_SECTION_ENTER();
4162 ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
4163 RTC_CRITICAL_SECTION_LEAVE();
4164 }
4165
hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void * const hw)4166 static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
4167 {
4168 uint32_t tmp;
4169 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4170 tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
4171 return (bool)tmp;
4172 }
4173
hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void * const hw,bool value)4174 static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
4175 {
4176 uint32_t tmp;
4177 RTC_CRITICAL_SECTION_ENTER();
4178 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4179 tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
4180 tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
4181 ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
4182 RTC_CRITICAL_SECTION_LEAVE();
4183 }
4184
hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void * const hw)4185 static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
4186 {
4187 RTC_CRITICAL_SECTION_ENTER();
4188 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
4189 RTC_CRITICAL_SECTION_LEAVE();
4190 }
4191
hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void * const hw)4192 static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
4193 {
4194 RTC_CRITICAL_SECTION_ENTER();
4195 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
4196 RTC_CRITICAL_SECTION_LEAVE();
4197 }
4198
hri_rtcmode0_set_EVCTRL_reg(const void * const hw,hri_rtcmode0_evctrl_reg_t mask)4199 static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
4200 {
4201 RTC_CRITICAL_SECTION_ENTER();
4202 ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
4203 RTC_CRITICAL_SECTION_LEAVE();
4204 }
4205
hri_rtcmode0_get_EVCTRL_reg(const void * const hw,hri_rtcmode0_evctrl_reg_t mask)4206 static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw,
4207 hri_rtcmode0_evctrl_reg_t mask)
4208 {
4209 uint32_t tmp;
4210 tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
4211 tmp &= mask;
4212 return tmp;
4213 }
4214
hri_rtcmode0_write_EVCTRL_reg(const void * const hw,hri_rtcmode0_evctrl_reg_t data)4215 static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
4216 {
4217 RTC_CRITICAL_SECTION_ENTER();
4218 ((Rtc *)hw)->MODE0.EVCTRL.reg = data;
4219 RTC_CRITICAL_SECTION_LEAVE();
4220 }
4221
hri_rtcmode0_clear_EVCTRL_reg(const void * const hw,hri_rtcmode0_evctrl_reg_t mask)4222 static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
4223 {
4224 RTC_CRITICAL_SECTION_ENTER();
4225 ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
4226 RTC_CRITICAL_SECTION_LEAVE();
4227 }
4228
hri_rtcmode0_toggle_EVCTRL_reg(const void * const hw,hri_rtcmode0_evctrl_reg_t mask)4229 static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
4230 {
4231 RTC_CRITICAL_SECTION_ENTER();
4232 ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
4233 RTC_CRITICAL_SECTION_LEAVE();
4234 }
4235
hri_rtcmode0_read_EVCTRL_reg(const void * const hw)4236 static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
4237 {
4238 return ((Rtc *)hw)->MODE0.EVCTRL.reg;
4239 }
4240
hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void * const hw)4241 static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw)
4242 {
4243 RTC_CRITICAL_SECTION_ENTER();
4244 ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
4245 RTC_CRITICAL_SECTION_LEAVE();
4246 }
4247
hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void * const hw)4248 static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw)
4249 {
4250 uint8_t tmp;
4251 tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
4252 tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
4253 return (bool)tmp;
4254 }
4255
hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)4256 static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
4257 {
4258 uint8_t tmp;
4259 RTC_CRITICAL_SECTION_ENTER();
4260 tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
4261 tmp &= ~RTC_DBGCTRL_DBGRUN;
4262 tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
4263 ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
4264 RTC_CRITICAL_SECTION_LEAVE();
4265 }
4266
hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void * const hw)4267 static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
4268 {
4269 RTC_CRITICAL_SECTION_ENTER();
4270 ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
4271 RTC_CRITICAL_SECTION_LEAVE();
4272 }
4273
hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)4274 static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
4275 {
4276 RTC_CRITICAL_SECTION_ENTER();
4277 ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
4278 RTC_CRITICAL_SECTION_LEAVE();
4279 }
4280
hri_rtcmode0_set_DBGCTRL_reg(const void * const hw,hri_rtcmode0_dbgctrl_reg_t mask)4281 static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
4282 {
4283 RTC_CRITICAL_SECTION_ENTER();
4284 ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
4285 RTC_CRITICAL_SECTION_LEAVE();
4286 }
4287
hri_rtcmode0_get_DBGCTRL_reg(const void * const hw,hri_rtcmode0_dbgctrl_reg_t mask)4288 static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const hw,
4289 hri_rtcmode0_dbgctrl_reg_t mask)
4290 {
4291 uint8_t tmp;
4292 tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
4293 tmp &= mask;
4294 return tmp;
4295 }
4296
hri_rtcmode0_write_DBGCTRL_reg(const void * const hw,hri_rtcmode0_dbgctrl_reg_t data)4297 static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data)
4298 {
4299 RTC_CRITICAL_SECTION_ENTER();
4300 ((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
4301 RTC_CRITICAL_SECTION_LEAVE();
4302 }
4303
hri_rtcmode0_clear_DBGCTRL_reg(const void * const hw,hri_rtcmode0_dbgctrl_reg_t mask)4304 static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
4305 {
4306 RTC_CRITICAL_SECTION_ENTER();
4307 ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
4308 RTC_CRITICAL_SECTION_LEAVE();
4309 }
4310
hri_rtcmode0_toggle_DBGCTRL_reg(const void * const hw,hri_rtcmode0_dbgctrl_reg_t mask)4311 static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask)
4312 {
4313 RTC_CRITICAL_SECTION_ENTER();
4314 ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
4315 RTC_CRITICAL_SECTION_LEAVE();
4316 }
4317
hri_rtcmode0_read_DBGCTRL_reg(const void * const hw)4318 static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw)
4319 {
4320 return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
4321 }
4322
hri_rtcmode0_set_FREQCORR_SIGN_bit(const void * const hw)4323 static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw)
4324 {
4325 RTC_CRITICAL_SECTION_ENTER();
4326 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4327 ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
4328 RTC_CRITICAL_SECTION_LEAVE();
4329 }
4330
hri_rtcmode0_get_FREQCORR_SIGN_bit(const void * const hw)4331 static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw)
4332 {
4333 uint8_t tmp;
4334 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4335 tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
4336 return (bool)tmp;
4337 }
4338
hri_rtcmode0_write_FREQCORR_SIGN_bit(const void * const hw,bool value)4339 static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
4340 {
4341 uint8_t tmp;
4342 RTC_CRITICAL_SECTION_ENTER();
4343 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4344 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4345 tmp &= ~RTC_FREQCORR_SIGN;
4346 tmp |= value << RTC_FREQCORR_SIGN_Pos;
4347 ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
4348 RTC_CRITICAL_SECTION_LEAVE();
4349 }
4350
hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void * const hw)4351 static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw)
4352 {
4353 RTC_CRITICAL_SECTION_ENTER();
4354 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4355 ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
4356 RTC_CRITICAL_SECTION_LEAVE();
4357 }
4358
hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void * const hw)4359 static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw)
4360 {
4361 RTC_CRITICAL_SECTION_ENTER();
4362 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4363 ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
4364 RTC_CRITICAL_SECTION_LEAVE();
4365 }
4366
hri_rtcmode0_set_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4367 static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4368 {
4369 RTC_CRITICAL_SECTION_ENTER();
4370 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4371 ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
4372 RTC_CRITICAL_SECTION_LEAVE();
4373 }
4374
hri_rtcmode0_get_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4375 static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const hw,
4376 hri_rtcmode0_freqcorr_reg_t mask)
4377 {
4378 uint8_t tmp;
4379 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4380 tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
4381 return tmp;
4382 }
4383
hri_rtcmode0_write_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode0_freqcorr_reg_t data)4384 static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data)
4385 {
4386 uint8_t tmp;
4387 RTC_CRITICAL_SECTION_ENTER();
4388 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4389 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4390 tmp &= ~RTC_FREQCORR_VALUE_Msk;
4391 tmp |= RTC_FREQCORR_VALUE(data);
4392 ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
4393 RTC_CRITICAL_SECTION_LEAVE();
4394 }
4395
hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4396 static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4397 {
4398 RTC_CRITICAL_SECTION_ENTER();
4399 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4400 ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
4401 RTC_CRITICAL_SECTION_LEAVE();
4402 }
4403
hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4404 static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4405 {
4406 RTC_CRITICAL_SECTION_ENTER();
4407 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4408 ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
4409 RTC_CRITICAL_SECTION_LEAVE();
4410 }
4411
hri_rtcmode0_read_FREQCORR_VALUE_bf(const void * const hw)4412 static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw)
4413 {
4414 uint8_t tmp;
4415 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4416 tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
4417 return tmp;
4418 }
4419
hri_rtcmode0_set_FREQCORR_reg(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4420 static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4421 {
4422 RTC_CRITICAL_SECTION_ENTER();
4423 ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
4424 RTC_CRITICAL_SECTION_LEAVE();
4425 }
4426
hri_rtcmode0_get_FREQCORR_reg(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4427 static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const hw,
4428 hri_rtcmode0_freqcorr_reg_t mask)
4429 {
4430 uint8_t tmp;
4431 tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
4432 tmp &= mask;
4433 return tmp;
4434 }
4435
hri_rtcmode0_write_FREQCORR_reg(const void * const hw,hri_rtcmode0_freqcorr_reg_t data)4436 static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data)
4437 {
4438 RTC_CRITICAL_SECTION_ENTER();
4439 ((Rtc *)hw)->MODE0.FREQCORR.reg = data;
4440 RTC_CRITICAL_SECTION_LEAVE();
4441 }
4442
hri_rtcmode0_clear_FREQCORR_reg(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4443 static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4444 {
4445 RTC_CRITICAL_SECTION_ENTER();
4446 ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
4447 RTC_CRITICAL_SECTION_LEAVE();
4448 }
4449
hri_rtcmode0_toggle_FREQCORR_reg(const void * const hw,hri_rtcmode0_freqcorr_reg_t mask)4450 static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask)
4451 {
4452 RTC_CRITICAL_SECTION_ENTER();
4453 ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
4454 RTC_CRITICAL_SECTION_LEAVE();
4455 }
4456
hri_rtcmode0_read_FREQCORR_reg(const void * const hw)4457 static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw)
4458 {
4459 return ((Rtc *)hw)->MODE0.FREQCORR.reg;
4460 }
4461
hri_rtcmode0_set_COUNT_COUNT_bf(const void * const hw,hri_rtcmode0_count_reg_t mask)4462 static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
4463 {
4464 RTC_CRITICAL_SECTION_ENTER();
4465 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4466 ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
4467 RTC_CRITICAL_SECTION_LEAVE();
4468 }
4469
hri_rtcmode0_get_COUNT_COUNT_bf(const void * const hw,hri_rtcmode0_count_reg_t mask)4470 static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw,
4471 hri_rtcmode0_count_reg_t mask)
4472 {
4473 uint32_t tmp;
4474 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4475 tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
4476 tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
4477 return tmp;
4478 }
4479
hri_rtcmode0_write_COUNT_COUNT_bf(const void * const hw,hri_rtcmode0_count_reg_t data)4480 static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
4481 {
4482 uint32_t tmp;
4483 RTC_CRITICAL_SECTION_ENTER();
4484 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4485 tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
4486 tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
4487 tmp |= RTC_MODE0_COUNT_COUNT(data);
4488 ((Rtc *)hw)->MODE0.COUNT.reg = tmp;
4489 RTC_CRITICAL_SECTION_LEAVE();
4490 }
4491
hri_rtcmode0_clear_COUNT_COUNT_bf(const void * const hw,hri_rtcmode0_count_reg_t mask)4492 static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
4493 {
4494 RTC_CRITICAL_SECTION_ENTER();
4495 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4496 ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
4497 RTC_CRITICAL_SECTION_LEAVE();
4498 }
4499
hri_rtcmode0_toggle_COUNT_COUNT_bf(const void * const hw,hri_rtcmode0_count_reg_t mask)4500 static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
4501 {
4502 RTC_CRITICAL_SECTION_ENTER();
4503 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4504 ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
4505 RTC_CRITICAL_SECTION_LEAVE();
4506 }
4507
hri_rtcmode0_read_COUNT_COUNT_bf(const void * const hw)4508 static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
4509 {
4510 uint32_t tmp;
4511 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
4512 tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
4513 tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
4514 return tmp;
4515 }
4516
hri_rtcmode0_set_COUNT_reg(const void * const hw,hri_rtcmode0_count_reg_t mask)4517 static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
4518 {
4519 RTC_CRITICAL_SECTION_ENTER();
4520 ((Rtc *)hw)->MODE0.COUNT.reg |= mask;
4521 RTC_CRITICAL_SECTION_LEAVE();
4522 }
4523
hri_rtcmode0_get_COUNT_reg(const void * const hw,hri_rtcmode0_count_reg_t mask)4524 static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
4525 {
4526 uint32_t tmp;
4527 tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
4528 tmp &= mask;
4529 return tmp;
4530 }
4531
hri_rtcmode0_write_COUNT_reg(const void * const hw,hri_rtcmode0_count_reg_t data)4532 static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
4533 {
4534 RTC_CRITICAL_SECTION_ENTER();
4535 ((Rtc *)hw)->MODE0.COUNT.reg = data;
4536 RTC_CRITICAL_SECTION_LEAVE();
4537 }
4538
hri_rtcmode0_clear_COUNT_reg(const void * const hw,hri_rtcmode0_count_reg_t mask)4539 static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
4540 {
4541 RTC_CRITICAL_SECTION_ENTER();
4542 ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
4543 RTC_CRITICAL_SECTION_LEAVE();
4544 }
4545
hri_rtcmode0_toggle_COUNT_reg(const void * const hw,hri_rtcmode0_count_reg_t mask)4546 static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
4547 {
4548 RTC_CRITICAL_SECTION_ENTER();
4549 ((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
4550 RTC_CRITICAL_SECTION_LEAVE();
4551 }
4552
hri_rtcmode0_read_COUNT_reg(const void * const hw)4553 static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
4554 {
4555 return ((Rtc *)hw)->MODE0.COUNT.reg;
4556 }
4557
hri_rtcmode0_set_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4558 static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4559 {
4560 RTC_CRITICAL_SECTION_ENTER();
4561 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4562 ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
4563 RTC_CRITICAL_SECTION_LEAVE();
4564 }
4565
hri_rtcmode0_get_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4566 static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
4567 hri_rtcmode0_comp_reg_t mask)
4568 {
4569 uint32_t tmp;
4570 tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
4571 tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
4572 return tmp;
4573 }
4574
hri_rtcmode0_write_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t data)4575 static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
4576 {
4577 uint32_t tmp;
4578 RTC_CRITICAL_SECTION_ENTER();
4579 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4580 tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
4581 tmp &= ~RTC_MODE0_COMP_COMP_Msk;
4582 tmp |= RTC_MODE0_COMP_COMP(data);
4583 ((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
4584 RTC_CRITICAL_SECTION_LEAVE();
4585 }
4586
hri_rtcmode0_clear_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4587 static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4588 {
4589 RTC_CRITICAL_SECTION_ENTER();
4590 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4591 ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
4592 RTC_CRITICAL_SECTION_LEAVE();
4593 }
4594
hri_rtcmode0_toggle_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4595 static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4596 {
4597 RTC_CRITICAL_SECTION_ENTER();
4598 hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
4599 ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
4600 RTC_CRITICAL_SECTION_LEAVE();
4601 }
4602
hri_rtcmode0_read_COMP_COMP_bf(const void * const hw,uint8_t index)4603 static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
4604 {
4605 uint32_t tmp;
4606 tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
4607 tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
4608 return tmp;
4609 }
4610
hri_rtcmode0_set_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4611 static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4612 {
4613 RTC_CRITICAL_SECTION_ENTER();
4614 ((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
4615 RTC_CRITICAL_SECTION_LEAVE();
4616 }
4617
hri_rtcmode0_get_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4618 static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
4619 hri_rtcmode0_comp_reg_t mask)
4620 {
4621 uint32_t tmp;
4622 tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
4623 tmp &= mask;
4624 return tmp;
4625 }
4626
hri_rtcmode0_write_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t data)4627 static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
4628 {
4629 RTC_CRITICAL_SECTION_ENTER();
4630 ((Rtc *)hw)->MODE0.COMP[index].reg = data;
4631 RTC_CRITICAL_SECTION_LEAVE();
4632 }
4633
hri_rtcmode0_clear_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4634 static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4635 {
4636 RTC_CRITICAL_SECTION_ENTER();
4637 ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
4638 RTC_CRITICAL_SECTION_LEAVE();
4639 }
4640
hri_rtcmode0_toggle_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode0_comp_reg_t mask)4641 static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
4642 {
4643 RTC_CRITICAL_SECTION_ENTER();
4644 ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
4645 RTC_CRITICAL_SECTION_LEAVE();
4646 }
4647
hri_rtcmode0_read_COMP_reg(const void * const hw,uint8_t index)4648 static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
4649 {
4650 return ((Rtc *)hw)->MODE0.COMP[index].reg;
4651 }
4652
hri_rtcmode0_set_GP_reg(const void * const hw,uint8_t index,hri_rtcmode0_gp_reg_t mask)4653 static inline void hri_rtcmode0_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask)
4654 {
4655 RTC_CRITICAL_SECTION_ENTER();
4656 ((Rtc *)hw)->MODE0.GP[index].reg |= mask;
4657 RTC_CRITICAL_SECTION_LEAVE();
4658 }
4659
hri_rtcmode0_get_GP_reg(const void * const hw,uint8_t index,hri_rtcmode0_gp_reg_t mask)4660 static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_get_GP_reg(const void *const hw, uint8_t index,
4661 hri_rtcmode0_gp_reg_t mask)
4662 {
4663 uint32_t tmp;
4664 tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
4665 tmp &= mask;
4666 return tmp;
4667 }
4668
hri_rtcmode0_write_GP_reg(const void * const hw,uint8_t index,hri_rtcmode0_gp_reg_t data)4669 static inline void hri_rtcmode0_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t data)
4670 {
4671 RTC_CRITICAL_SECTION_ENTER();
4672 ((Rtc *)hw)->MODE0.GP[index].reg = data;
4673 RTC_CRITICAL_SECTION_LEAVE();
4674 }
4675
hri_rtcmode0_clear_GP_reg(const void * const hw,uint8_t index,hri_rtcmode0_gp_reg_t mask)4676 static inline void hri_rtcmode0_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask)
4677 {
4678 RTC_CRITICAL_SECTION_ENTER();
4679 ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
4680 RTC_CRITICAL_SECTION_LEAVE();
4681 }
4682
hri_rtcmode0_toggle_GP_reg(const void * const hw,uint8_t index,hri_rtcmode0_gp_reg_t mask)4683 static inline void hri_rtcmode0_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask)
4684 {
4685 RTC_CRITICAL_SECTION_ENTER();
4686 ((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
4687 RTC_CRITICAL_SECTION_LEAVE();
4688 }
4689
hri_rtcmode0_read_GP_reg(const void * const hw,uint8_t index)4690 static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_read_GP_reg(const void *const hw, uint8_t index)
4691 {
4692 return ((Rtc *)hw)->MODE0.GP[index].reg;
4693 }
4694
hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void * const hw)4695 static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
4696 {
4697 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
4698 }
4699
hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void * const hw)4700 static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
4701 {
4702 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
4703 }
4704
hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void * const hw)4705 static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
4706 {
4707 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
4708 }
4709
hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void * const hw)4710 static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
4711 {
4712 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
4713 }
4714
hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void * const hw)4715 static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
4716 {
4717 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
4718 }
4719
hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void * const hw)4720 static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
4721 {
4722 return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
4723 }
4724
hri_rtcmode0_get_SYNCBUSY_reg(const void * const hw,hri_rtcmode0_syncbusy_reg_t mask)4725 static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw,
4726 hri_rtcmode0_syncbusy_reg_t mask)
4727 {
4728 uint32_t tmp;
4729 tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
4730 tmp &= mask;
4731 return tmp;
4732 }
4733
hri_rtcmode0_read_SYNCBUSY_reg(const void * const hw)4734 static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
4735 {
4736 return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
4737 }
4738
hri_rtcmode1_set_INTEN_PER0_bit(const void * const hw)4739 static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
4740 {
4741 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
4742 }
4743
hri_rtcmode1_get_INTEN_PER0_bit(const void * const hw)4744 static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
4745 {
4746 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
4747 }
4748
hri_rtcmode1_write_INTEN_PER0_bit(const void * const hw,bool value)4749 static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
4750 {
4751 if (value == 0x0) {
4752 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
4753 } else {
4754 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
4755 }
4756 }
4757
hri_rtcmode1_clear_INTEN_PER0_bit(const void * const hw)4758 static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
4759 {
4760 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
4761 }
4762
hri_rtcmode1_set_INTEN_PER1_bit(const void * const hw)4763 static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
4764 {
4765 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
4766 }
4767
hri_rtcmode1_get_INTEN_PER1_bit(const void * const hw)4768 static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
4769 {
4770 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
4771 }
4772
hri_rtcmode1_write_INTEN_PER1_bit(const void * const hw,bool value)4773 static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
4774 {
4775 if (value == 0x0) {
4776 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
4777 } else {
4778 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
4779 }
4780 }
4781
hri_rtcmode1_clear_INTEN_PER1_bit(const void * const hw)4782 static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
4783 {
4784 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
4785 }
4786
hri_rtcmode1_set_INTEN_PER2_bit(const void * const hw)4787 static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
4788 {
4789 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
4790 }
4791
hri_rtcmode1_get_INTEN_PER2_bit(const void * const hw)4792 static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
4793 {
4794 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
4795 }
4796
hri_rtcmode1_write_INTEN_PER2_bit(const void * const hw,bool value)4797 static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
4798 {
4799 if (value == 0x0) {
4800 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
4801 } else {
4802 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
4803 }
4804 }
4805
hri_rtcmode1_clear_INTEN_PER2_bit(const void * const hw)4806 static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
4807 {
4808 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
4809 }
4810
hri_rtcmode1_set_INTEN_PER3_bit(const void * const hw)4811 static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
4812 {
4813 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
4814 }
4815
hri_rtcmode1_get_INTEN_PER3_bit(const void * const hw)4816 static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
4817 {
4818 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
4819 }
4820
hri_rtcmode1_write_INTEN_PER3_bit(const void * const hw,bool value)4821 static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
4822 {
4823 if (value == 0x0) {
4824 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
4825 } else {
4826 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
4827 }
4828 }
4829
hri_rtcmode1_clear_INTEN_PER3_bit(const void * const hw)4830 static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
4831 {
4832 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
4833 }
4834
hri_rtcmode1_set_INTEN_PER4_bit(const void * const hw)4835 static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
4836 {
4837 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
4838 }
4839
hri_rtcmode1_get_INTEN_PER4_bit(const void * const hw)4840 static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
4841 {
4842 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
4843 }
4844
hri_rtcmode1_write_INTEN_PER4_bit(const void * const hw,bool value)4845 static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
4846 {
4847 if (value == 0x0) {
4848 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
4849 } else {
4850 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
4851 }
4852 }
4853
hri_rtcmode1_clear_INTEN_PER4_bit(const void * const hw)4854 static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
4855 {
4856 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
4857 }
4858
hri_rtcmode1_set_INTEN_PER5_bit(const void * const hw)4859 static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
4860 {
4861 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
4862 }
4863
hri_rtcmode1_get_INTEN_PER5_bit(const void * const hw)4864 static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
4865 {
4866 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
4867 }
4868
hri_rtcmode1_write_INTEN_PER5_bit(const void * const hw,bool value)4869 static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
4870 {
4871 if (value == 0x0) {
4872 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
4873 } else {
4874 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
4875 }
4876 }
4877
hri_rtcmode1_clear_INTEN_PER5_bit(const void * const hw)4878 static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
4879 {
4880 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
4881 }
4882
hri_rtcmode1_set_INTEN_PER6_bit(const void * const hw)4883 static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
4884 {
4885 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
4886 }
4887
hri_rtcmode1_get_INTEN_PER6_bit(const void * const hw)4888 static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
4889 {
4890 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
4891 }
4892
hri_rtcmode1_write_INTEN_PER6_bit(const void * const hw,bool value)4893 static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
4894 {
4895 if (value == 0x0) {
4896 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
4897 } else {
4898 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
4899 }
4900 }
4901
hri_rtcmode1_clear_INTEN_PER6_bit(const void * const hw)4902 static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
4903 {
4904 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
4905 }
4906
hri_rtcmode1_set_INTEN_PER7_bit(const void * const hw)4907 static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
4908 {
4909 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
4910 }
4911
hri_rtcmode1_get_INTEN_PER7_bit(const void * const hw)4912 static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
4913 {
4914 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
4915 }
4916
hri_rtcmode1_write_INTEN_PER7_bit(const void * const hw,bool value)4917 static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
4918 {
4919 if (value == 0x0) {
4920 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
4921 } else {
4922 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
4923 }
4924 }
4925
hri_rtcmode1_clear_INTEN_PER7_bit(const void * const hw)4926 static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
4927 {
4928 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
4929 }
4930
hri_rtcmode1_set_INTEN_CMP0_bit(const void * const hw)4931 static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
4932 {
4933 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
4934 }
4935
hri_rtcmode1_get_INTEN_CMP0_bit(const void * const hw)4936 static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
4937 {
4938 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
4939 }
4940
hri_rtcmode1_write_INTEN_CMP0_bit(const void * const hw,bool value)4941 static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
4942 {
4943 if (value == 0x0) {
4944 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
4945 } else {
4946 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
4947 }
4948 }
4949
hri_rtcmode1_clear_INTEN_CMP0_bit(const void * const hw)4950 static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
4951 {
4952 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
4953 }
4954
hri_rtcmode1_set_INTEN_CMP1_bit(const void * const hw)4955 static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
4956 {
4957 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
4958 }
4959
hri_rtcmode1_get_INTEN_CMP1_bit(const void * const hw)4960 static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
4961 {
4962 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
4963 }
4964
hri_rtcmode1_write_INTEN_CMP1_bit(const void * const hw,bool value)4965 static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
4966 {
4967 if (value == 0x0) {
4968 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
4969 } else {
4970 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
4971 }
4972 }
4973
hri_rtcmode1_clear_INTEN_CMP1_bit(const void * const hw)4974 static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
4975 {
4976 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
4977 }
4978
hri_rtcmode1_set_INTEN_OVF_bit(const void * const hw)4979 static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
4980 {
4981 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
4982 }
4983
hri_rtcmode1_get_INTEN_OVF_bit(const void * const hw)4984 static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
4985 {
4986 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
4987 }
4988
hri_rtcmode1_write_INTEN_OVF_bit(const void * const hw,bool value)4989 static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
4990 {
4991 if (value == 0x0) {
4992 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
4993 } else {
4994 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
4995 }
4996 }
4997
hri_rtcmode1_clear_INTEN_OVF_bit(const void * const hw)4998 static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
4999 {
5000 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
5001 }
5002
hri_rtcmode1_set_INTEN_reg(const void * const hw,hri_rtcmode1_intenset_reg_t mask)5003 static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
5004 {
5005 ((Rtc *)hw)->MODE1.INTENSET.reg = mask;
5006 }
5007
hri_rtcmode1_get_INTEN_reg(const void * const hw,hri_rtcmode1_intenset_reg_t mask)5008 static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw,
5009 hri_rtcmode1_intenset_reg_t mask)
5010 {
5011 uint16_t tmp;
5012 tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
5013 tmp &= mask;
5014 return tmp;
5015 }
5016
hri_rtcmode1_read_INTEN_reg(const void * const hw)5017 static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
5018 {
5019 return ((Rtc *)hw)->MODE1.INTENSET.reg;
5020 }
5021
hri_rtcmode1_write_INTEN_reg(const void * const hw,hri_rtcmode1_intenset_reg_t data)5022 static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
5023 {
5024 ((Rtc *)hw)->MODE1.INTENSET.reg = data;
5025 ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
5026 }
5027
hri_rtcmode1_clear_INTEN_reg(const void * const hw,hri_rtcmode1_intenset_reg_t mask)5028 static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
5029 {
5030 ((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
5031 }
5032
hri_rtcmode1_get_INTFLAG_PER0_bit(const void * const hw)5033 static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
5034 {
5035 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
5036 }
5037
hri_rtcmode1_clear_INTFLAG_PER0_bit(const void * const hw)5038 static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
5039 {
5040 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
5041 }
5042
hri_rtcmode1_get_INTFLAG_PER1_bit(const void * const hw)5043 static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
5044 {
5045 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
5046 }
5047
hri_rtcmode1_clear_INTFLAG_PER1_bit(const void * const hw)5048 static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
5049 {
5050 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
5051 }
5052
hri_rtcmode1_get_INTFLAG_PER2_bit(const void * const hw)5053 static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
5054 {
5055 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
5056 }
5057
hri_rtcmode1_clear_INTFLAG_PER2_bit(const void * const hw)5058 static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
5059 {
5060 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
5061 }
5062
hri_rtcmode1_get_INTFLAG_PER3_bit(const void * const hw)5063 static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
5064 {
5065 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
5066 }
5067
hri_rtcmode1_clear_INTFLAG_PER3_bit(const void * const hw)5068 static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
5069 {
5070 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
5071 }
5072
hri_rtcmode1_get_INTFLAG_PER4_bit(const void * const hw)5073 static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
5074 {
5075 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
5076 }
5077
hri_rtcmode1_clear_INTFLAG_PER4_bit(const void * const hw)5078 static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
5079 {
5080 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
5081 }
5082
hri_rtcmode1_get_INTFLAG_PER5_bit(const void * const hw)5083 static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
5084 {
5085 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
5086 }
5087
hri_rtcmode1_clear_INTFLAG_PER5_bit(const void * const hw)5088 static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
5089 {
5090 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
5091 }
5092
hri_rtcmode1_get_INTFLAG_PER6_bit(const void * const hw)5093 static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
5094 {
5095 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
5096 }
5097
hri_rtcmode1_clear_INTFLAG_PER6_bit(const void * const hw)5098 static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
5099 {
5100 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
5101 }
5102
hri_rtcmode1_get_INTFLAG_PER7_bit(const void * const hw)5103 static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
5104 {
5105 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
5106 }
5107
hri_rtcmode1_clear_INTFLAG_PER7_bit(const void * const hw)5108 static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
5109 {
5110 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
5111 }
5112
hri_rtcmode1_get_INTFLAG_CMP0_bit(const void * const hw)5113 static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
5114 {
5115 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
5116 }
5117
hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void * const hw)5118 static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
5119 {
5120 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
5121 }
5122
hri_rtcmode1_get_INTFLAG_CMP1_bit(const void * const hw)5123 static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
5124 {
5125 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
5126 }
5127
hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void * const hw)5128 static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
5129 {
5130 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
5131 }
5132
hri_rtcmode1_get_INTFLAG_OVF_bit(const void * const hw)5133 static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
5134 {
5135 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
5136 }
5137
hri_rtcmode1_clear_INTFLAG_OVF_bit(const void * const hw)5138 static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
5139 {
5140 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
5141 }
5142
hri_rtcmode1_get_interrupt_PER0_bit(const void * const hw)5143 static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
5144 {
5145 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
5146 }
5147
hri_rtcmode1_clear_interrupt_PER0_bit(const void * const hw)5148 static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
5149 {
5150 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
5151 }
5152
hri_rtcmode1_get_interrupt_PER1_bit(const void * const hw)5153 static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
5154 {
5155 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
5156 }
5157
hri_rtcmode1_clear_interrupt_PER1_bit(const void * const hw)5158 static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
5159 {
5160 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
5161 }
5162
hri_rtcmode1_get_interrupt_PER2_bit(const void * const hw)5163 static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
5164 {
5165 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
5166 }
5167
hri_rtcmode1_clear_interrupt_PER2_bit(const void * const hw)5168 static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
5169 {
5170 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
5171 }
5172
hri_rtcmode1_get_interrupt_PER3_bit(const void * const hw)5173 static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
5174 {
5175 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
5176 }
5177
hri_rtcmode1_clear_interrupt_PER3_bit(const void * const hw)5178 static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
5179 {
5180 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
5181 }
5182
hri_rtcmode1_get_interrupt_PER4_bit(const void * const hw)5183 static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
5184 {
5185 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
5186 }
5187
hri_rtcmode1_clear_interrupt_PER4_bit(const void * const hw)5188 static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
5189 {
5190 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
5191 }
5192
hri_rtcmode1_get_interrupt_PER5_bit(const void * const hw)5193 static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
5194 {
5195 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
5196 }
5197
hri_rtcmode1_clear_interrupt_PER5_bit(const void * const hw)5198 static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
5199 {
5200 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
5201 }
5202
hri_rtcmode1_get_interrupt_PER6_bit(const void * const hw)5203 static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
5204 {
5205 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
5206 }
5207
hri_rtcmode1_clear_interrupt_PER6_bit(const void * const hw)5208 static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
5209 {
5210 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
5211 }
5212
hri_rtcmode1_get_interrupt_PER7_bit(const void * const hw)5213 static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
5214 {
5215 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
5216 }
5217
hri_rtcmode1_clear_interrupt_PER7_bit(const void * const hw)5218 static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
5219 {
5220 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
5221 }
5222
hri_rtcmode1_get_interrupt_CMP0_bit(const void * const hw)5223 static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
5224 {
5225 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
5226 }
5227
hri_rtcmode1_clear_interrupt_CMP0_bit(const void * const hw)5228 static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
5229 {
5230 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
5231 }
5232
hri_rtcmode1_get_interrupt_CMP1_bit(const void * const hw)5233 static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
5234 {
5235 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
5236 }
5237
hri_rtcmode1_clear_interrupt_CMP1_bit(const void * const hw)5238 static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
5239 {
5240 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
5241 }
5242
hri_rtcmode1_get_interrupt_OVF_bit(const void * const hw)5243 static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
5244 {
5245 return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
5246 }
5247
hri_rtcmode1_clear_interrupt_OVF_bit(const void * const hw)5248 static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
5249 {
5250 ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
5251 }
5252
hri_rtcmode1_get_INTFLAG_reg(const void * const hw,hri_rtcmode1_intflag_reg_t mask)5253 static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw,
5254 hri_rtcmode1_intflag_reg_t mask)
5255 {
5256 uint16_t tmp;
5257 tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
5258 tmp &= mask;
5259 return tmp;
5260 }
5261
hri_rtcmode1_read_INTFLAG_reg(const void * const hw)5262 static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
5263 {
5264 return ((Rtc *)hw)->MODE1.INTFLAG.reg;
5265 }
5266
hri_rtcmode1_clear_INTFLAG_reg(const void * const hw,hri_rtcmode1_intflag_reg_t mask)5267 static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
5268 {
5269 ((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
5270 }
5271
hri_rtcmode1_set_CTRLA_SWRST_bit(const void * const hw)5272 static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
5273 {
5274 RTC_CRITICAL_SECTION_ENTER();
5275 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
5276 ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
5277 RTC_CRITICAL_SECTION_LEAVE();
5278 }
5279
hri_rtcmode1_get_CTRLA_SWRST_bit(const void * const hw)5280 static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
5281 {
5282 uint16_t tmp;
5283 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
5284 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5285 tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
5286 return (bool)tmp;
5287 }
5288
hri_rtcmode1_set_CTRLA_ENABLE_bit(const void * const hw)5289 static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
5290 {
5291 RTC_CRITICAL_SECTION_ENTER();
5292 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5293 ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
5294 RTC_CRITICAL_SECTION_LEAVE();
5295 }
5296
hri_rtcmode1_get_CTRLA_ENABLE_bit(const void * const hw)5297 static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
5298 {
5299 uint16_t tmp;
5300 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5301 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5302 tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
5303 return (bool)tmp;
5304 }
5305
hri_rtcmode1_write_CTRLA_ENABLE_bit(const void * const hw,bool value)5306 static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
5307 {
5308 uint16_t tmp;
5309 RTC_CRITICAL_SECTION_ENTER();
5310 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5311 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5312 tmp &= ~RTC_MODE1_CTRLA_ENABLE;
5313 tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
5314 ((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
5315 RTC_CRITICAL_SECTION_LEAVE();
5316 }
5317
hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void * const hw)5318 static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
5319 {
5320 RTC_CRITICAL_SECTION_ENTER();
5321 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5322 ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
5323 RTC_CRITICAL_SECTION_LEAVE();
5324 }
5325
hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void * const hw)5326 static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
5327 {
5328 RTC_CRITICAL_SECTION_ENTER();
5329 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5330 ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
5331 RTC_CRITICAL_SECTION_LEAVE();
5332 }
5333
hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void * const hw)5334 static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
5335 {
5336 RTC_CRITICAL_SECTION_ENTER();
5337 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5338 ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
5339 RTC_CRITICAL_SECTION_LEAVE();
5340 }
5341
hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void * const hw)5342 static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
5343 {
5344 uint16_t tmp;
5345 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5346 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5347 tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
5348 return (bool)tmp;
5349 }
5350
hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void * const hw,bool value)5351 static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
5352 {
5353 uint16_t tmp;
5354 RTC_CRITICAL_SECTION_ENTER();
5355 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5356 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5357 tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
5358 tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
5359 ((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
5360 RTC_CRITICAL_SECTION_LEAVE();
5361 }
5362
hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void * const hw)5363 static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
5364 {
5365 RTC_CRITICAL_SECTION_ENTER();
5366 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5367 ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
5368 RTC_CRITICAL_SECTION_LEAVE();
5369 }
5370
hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void * const hw)5371 static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
5372 {
5373 RTC_CRITICAL_SECTION_ENTER();
5374 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
5375 ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
5376 RTC_CRITICAL_SECTION_LEAVE();
5377 }
5378
hri_rtcmode1_set_CTRLA_MODE_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5379 static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5380 {
5381 RTC_CRITICAL_SECTION_ENTER();
5382 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5383 ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
5384 RTC_CRITICAL_SECTION_LEAVE();
5385 }
5386
hri_rtcmode1_get_CTRLA_MODE_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5387 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw,
5388 hri_rtcmode1_ctrla_reg_t mask)
5389 {
5390 uint16_t tmp;
5391 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5392 tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
5393 return tmp;
5394 }
5395
hri_rtcmode1_write_CTRLA_MODE_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t data)5396 static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
5397 {
5398 uint16_t tmp;
5399 RTC_CRITICAL_SECTION_ENTER();
5400 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5401 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5402 tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
5403 tmp |= RTC_MODE1_CTRLA_MODE(data);
5404 ((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
5405 RTC_CRITICAL_SECTION_LEAVE();
5406 }
5407
hri_rtcmode1_clear_CTRLA_MODE_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5408 static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5409 {
5410 RTC_CRITICAL_SECTION_ENTER();
5411 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5412 ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
5413 RTC_CRITICAL_SECTION_LEAVE();
5414 }
5415
hri_rtcmode1_toggle_CTRLA_MODE_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5416 static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5417 {
5418 RTC_CRITICAL_SECTION_ENTER();
5419 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5420 ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
5421 RTC_CRITICAL_SECTION_LEAVE();
5422 }
5423
hri_rtcmode1_read_CTRLA_MODE_bf(const void * const hw)5424 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
5425 {
5426 uint16_t tmp;
5427 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5428 tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
5429 return tmp;
5430 }
5431
hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5432 static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5433 {
5434 RTC_CRITICAL_SECTION_ENTER();
5435 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5436 ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
5437 RTC_CRITICAL_SECTION_LEAVE();
5438 }
5439
hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5440 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw,
5441 hri_rtcmode1_ctrla_reg_t mask)
5442 {
5443 uint16_t tmp;
5444 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5445 tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
5446 return tmp;
5447 }
5448
hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t data)5449 static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
5450 {
5451 uint16_t tmp;
5452 RTC_CRITICAL_SECTION_ENTER();
5453 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5454 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5455 tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
5456 tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
5457 ((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
5458 RTC_CRITICAL_SECTION_LEAVE();
5459 }
5460
hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5461 static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5462 {
5463 RTC_CRITICAL_SECTION_ENTER();
5464 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5465 ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
5466 RTC_CRITICAL_SECTION_LEAVE();
5467 }
5468
hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5469 static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5470 {
5471 RTC_CRITICAL_SECTION_ENTER();
5472 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
5473 ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
5474 RTC_CRITICAL_SECTION_LEAVE();
5475 }
5476
hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void * const hw)5477 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
5478 {
5479 uint16_t tmp;
5480 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5481 tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
5482 return tmp;
5483 }
5484
hri_rtcmode1_set_CTRLA_reg(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5485 static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5486 {
5487 RTC_CRITICAL_SECTION_ENTER();
5488 ((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
5489 RTC_CRITICAL_SECTION_LEAVE();
5490 }
5491
hri_rtcmode1_get_CTRLA_reg(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5492 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5493 {
5494 uint16_t tmp;
5495 tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
5496 tmp &= mask;
5497 return tmp;
5498 }
5499
hri_rtcmode1_write_CTRLA_reg(const void * const hw,hri_rtcmode1_ctrla_reg_t data)5500 static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
5501 {
5502 RTC_CRITICAL_SECTION_ENTER();
5503 ((Rtc *)hw)->MODE1.CTRLA.reg = data;
5504 RTC_CRITICAL_SECTION_LEAVE();
5505 }
5506
hri_rtcmode1_clear_CTRLA_reg(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5507 static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5508 {
5509 RTC_CRITICAL_SECTION_ENTER();
5510 ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
5511 RTC_CRITICAL_SECTION_LEAVE();
5512 }
5513
hri_rtcmode1_toggle_CTRLA_reg(const void * const hw,hri_rtcmode1_ctrla_reg_t mask)5514 static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
5515 {
5516 RTC_CRITICAL_SECTION_ENTER();
5517 ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
5518 RTC_CRITICAL_SECTION_LEAVE();
5519 }
5520
hri_rtcmode1_read_CTRLA_reg(const void * const hw)5521 static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
5522 {
5523 return ((Rtc *)hw)->MODE1.CTRLA.reg;
5524 }
5525
hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void * const hw)5526 static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
5527 {
5528 RTC_CRITICAL_SECTION_ENTER();
5529 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
5530 RTC_CRITICAL_SECTION_LEAVE();
5531 }
5532
hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void * const hw)5533 static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
5534 {
5535 uint32_t tmp;
5536 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5537 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
5538 return (bool)tmp;
5539 }
5540
hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void * const hw,bool value)5541 static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
5542 {
5543 uint32_t tmp;
5544 RTC_CRITICAL_SECTION_ENTER();
5545 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5546 tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
5547 tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
5548 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5549 RTC_CRITICAL_SECTION_LEAVE();
5550 }
5551
hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void * const hw)5552 static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
5553 {
5554 RTC_CRITICAL_SECTION_ENTER();
5555 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
5556 RTC_CRITICAL_SECTION_LEAVE();
5557 }
5558
hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void * const hw)5559 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
5560 {
5561 RTC_CRITICAL_SECTION_ENTER();
5562 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
5563 RTC_CRITICAL_SECTION_LEAVE();
5564 }
5565
hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void * const hw)5566 static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
5567 {
5568 RTC_CRITICAL_SECTION_ENTER();
5569 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
5570 RTC_CRITICAL_SECTION_LEAVE();
5571 }
5572
hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void * const hw)5573 static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
5574 {
5575 uint32_t tmp;
5576 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5577 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
5578 return (bool)tmp;
5579 }
5580
hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void * const hw,bool value)5581 static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
5582 {
5583 uint32_t tmp;
5584 RTC_CRITICAL_SECTION_ENTER();
5585 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5586 tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
5587 tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
5588 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5589 RTC_CRITICAL_SECTION_LEAVE();
5590 }
5591
hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void * const hw)5592 static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
5593 {
5594 RTC_CRITICAL_SECTION_ENTER();
5595 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
5596 RTC_CRITICAL_SECTION_LEAVE();
5597 }
5598
hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void * const hw)5599 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
5600 {
5601 RTC_CRITICAL_SECTION_ENTER();
5602 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
5603 RTC_CRITICAL_SECTION_LEAVE();
5604 }
5605
hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void * const hw)5606 static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
5607 {
5608 RTC_CRITICAL_SECTION_ENTER();
5609 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
5610 RTC_CRITICAL_SECTION_LEAVE();
5611 }
5612
hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void * const hw)5613 static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
5614 {
5615 uint32_t tmp;
5616 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5617 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
5618 return (bool)tmp;
5619 }
5620
hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void * const hw,bool value)5621 static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
5622 {
5623 uint32_t tmp;
5624 RTC_CRITICAL_SECTION_ENTER();
5625 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5626 tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
5627 tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
5628 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5629 RTC_CRITICAL_SECTION_LEAVE();
5630 }
5631
hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void * const hw)5632 static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
5633 {
5634 RTC_CRITICAL_SECTION_ENTER();
5635 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
5636 RTC_CRITICAL_SECTION_LEAVE();
5637 }
5638
hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void * const hw)5639 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
5640 {
5641 RTC_CRITICAL_SECTION_ENTER();
5642 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
5643 RTC_CRITICAL_SECTION_LEAVE();
5644 }
5645
hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void * const hw)5646 static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
5647 {
5648 RTC_CRITICAL_SECTION_ENTER();
5649 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
5650 RTC_CRITICAL_SECTION_LEAVE();
5651 }
5652
hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void * const hw)5653 static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
5654 {
5655 uint32_t tmp;
5656 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5657 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
5658 return (bool)tmp;
5659 }
5660
hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void * const hw,bool value)5661 static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
5662 {
5663 uint32_t tmp;
5664 RTC_CRITICAL_SECTION_ENTER();
5665 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5666 tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
5667 tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
5668 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5669 RTC_CRITICAL_SECTION_LEAVE();
5670 }
5671
hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void * const hw)5672 static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
5673 {
5674 RTC_CRITICAL_SECTION_ENTER();
5675 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
5676 RTC_CRITICAL_SECTION_LEAVE();
5677 }
5678
hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void * const hw)5679 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
5680 {
5681 RTC_CRITICAL_SECTION_ENTER();
5682 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
5683 RTC_CRITICAL_SECTION_LEAVE();
5684 }
5685
hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void * const hw)5686 static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
5687 {
5688 RTC_CRITICAL_SECTION_ENTER();
5689 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
5690 RTC_CRITICAL_SECTION_LEAVE();
5691 }
5692
hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void * const hw)5693 static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
5694 {
5695 uint32_t tmp;
5696 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5697 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
5698 return (bool)tmp;
5699 }
5700
hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void * const hw,bool value)5701 static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
5702 {
5703 uint32_t tmp;
5704 RTC_CRITICAL_SECTION_ENTER();
5705 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5706 tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
5707 tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
5708 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5709 RTC_CRITICAL_SECTION_LEAVE();
5710 }
5711
hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void * const hw)5712 static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
5713 {
5714 RTC_CRITICAL_SECTION_ENTER();
5715 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
5716 RTC_CRITICAL_SECTION_LEAVE();
5717 }
5718
hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void * const hw)5719 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
5720 {
5721 RTC_CRITICAL_SECTION_ENTER();
5722 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
5723 RTC_CRITICAL_SECTION_LEAVE();
5724 }
5725
hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void * const hw)5726 static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
5727 {
5728 RTC_CRITICAL_SECTION_ENTER();
5729 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
5730 RTC_CRITICAL_SECTION_LEAVE();
5731 }
5732
hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void * const hw)5733 static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
5734 {
5735 uint32_t tmp;
5736 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5737 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
5738 return (bool)tmp;
5739 }
5740
hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void * const hw,bool value)5741 static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
5742 {
5743 uint32_t tmp;
5744 RTC_CRITICAL_SECTION_ENTER();
5745 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5746 tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
5747 tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
5748 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5749 RTC_CRITICAL_SECTION_LEAVE();
5750 }
5751
hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void * const hw)5752 static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
5753 {
5754 RTC_CRITICAL_SECTION_ENTER();
5755 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
5756 RTC_CRITICAL_SECTION_LEAVE();
5757 }
5758
hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void * const hw)5759 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
5760 {
5761 RTC_CRITICAL_SECTION_ENTER();
5762 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
5763 RTC_CRITICAL_SECTION_LEAVE();
5764 }
5765
hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void * const hw)5766 static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
5767 {
5768 RTC_CRITICAL_SECTION_ENTER();
5769 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
5770 RTC_CRITICAL_SECTION_LEAVE();
5771 }
5772
hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void * const hw)5773 static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
5774 {
5775 uint32_t tmp;
5776 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5777 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
5778 return (bool)tmp;
5779 }
5780
hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void * const hw,bool value)5781 static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
5782 {
5783 uint32_t tmp;
5784 RTC_CRITICAL_SECTION_ENTER();
5785 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5786 tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
5787 tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
5788 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5789 RTC_CRITICAL_SECTION_LEAVE();
5790 }
5791
hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void * const hw)5792 static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
5793 {
5794 RTC_CRITICAL_SECTION_ENTER();
5795 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
5796 RTC_CRITICAL_SECTION_LEAVE();
5797 }
5798
hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void * const hw)5799 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
5800 {
5801 RTC_CRITICAL_SECTION_ENTER();
5802 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
5803 RTC_CRITICAL_SECTION_LEAVE();
5804 }
5805
hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void * const hw)5806 static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
5807 {
5808 RTC_CRITICAL_SECTION_ENTER();
5809 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
5810 RTC_CRITICAL_SECTION_LEAVE();
5811 }
5812
hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void * const hw)5813 static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
5814 {
5815 uint32_t tmp;
5816 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5817 tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
5818 return (bool)tmp;
5819 }
5820
hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void * const hw,bool value)5821 static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
5822 {
5823 uint32_t tmp;
5824 RTC_CRITICAL_SECTION_ENTER();
5825 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5826 tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
5827 tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
5828 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5829 RTC_CRITICAL_SECTION_LEAVE();
5830 }
5831
hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void * const hw)5832 static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
5833 {
5834 RTC_CRITICAL_SECTION_ENTER();
5835 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
5836 RTC_CRITICAL_SECTION_LEAVE();
5837 }
5838
hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void * const hw)5839 static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
5840 {
5841 RTC_CRITICAL_SECTION_ENTER();
5842 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
5843 RTC_CRITICAL_SECTION_LEAVE();
5844 }
5845
hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void * const hw)5846 static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
5847 {
5848 RTC_CRITICAL_SECTION_ENTER();
5849 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
5850 RTC_CRITICAL_SECTION_LEAVE();
5851 }
5852
hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void * const hw)5853 static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
5854 {
5855 uint32_t tmp;
5856 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5857 tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
5858 return (bool)tmp;
5859 }
5860
hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void * const hw,bool value)5861 static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
5862 {
5863 uint32_t tmp;
5864 RTC_CRITICAL_SECTION_ENTER();
5865 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5866 tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
5867 tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
5868 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5869 RTC_CRITICAL_SECTION_LEAVE();
5870 }
5871
hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void * const hw)5872 static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
5873 {
5874 RTC_CRITICAL_SECTION_ENTER();
5875 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
5876 RTC_CRITICAL_SECTION_LEAVE();
5877 }
5878
hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void * const hw)5879 static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
5880 {
5881 RTC_CRITICAL_SECTION_ENTER();
5882 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
5883 RTC_CRITICAL_SECTION_LEAVE();
5884 }
5885
hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void * const hw)5886 static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
5887 {
5888 RTC_CRITICAL_SECTION_ENTER();
5889 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
5890 RTC_CRITICAL_SECTION_LEAVE();
5891 }
5892
hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void * const hw)5893 static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
5894 {
5895 uint32_t tmp;
5896 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5897 tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
5898 return (bool)tmp;
5899 }
5900
hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void * const hw,bool value)5901 static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
5902 {
5903 uint32_t tmp;
5904 RTC_CRITICAL_SECTION_ENTER();
5905 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5906 tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
5907 tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
5908 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5909 RTC_CRITICAL_SECTION_LEAVE();
5910 }
5911
hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void * const hw)5912 static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
5913 {
5914 RTC_CRITICAL_SECTION_ENTER();
5915 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
5916 RTC_CRITICAL_SECTION_LEAVE();
5917 }
5918
hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void * const hw)5919 static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
5920 {
5921 RTC_CRITICAL_SECTION_ENTER();
5922 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
5923 RTC_CRITICAL_SECTION_LEAVE();
5924 }
5925
hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void * const hw)5926 static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
5927 {
5928 RTC_CRITICAL_SECTION_ENTER();
5929 ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
5930 RTC_CRITICAL_SECTION_LEAVE();
5931 }
5932
hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void * const hw)5933 static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
5934 {
5935 uint32_t tmp;
5936 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5937 tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
5938 return (bool)tmp;
5939 }
5940
hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void * const hw,bool value)5941 static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
5942 {
5943 uint32_t tmp;
5944 RTC_CRITICAL_SECTION_ENTER();
5945 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5946 tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
5947 tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
5948 ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
5949 RTC_CRITICAL_SECTION_LEAVE();
5950 }
5951
hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void * const hw)5952 static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
5953 {
5954 RTC_CRITICAL_SECTION_ENTER();
5955 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
5956 RTC_CRITICAL_SECTION_LEAVE();
5957 }
5958
hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void * const hw)5959 static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
5960 {
5961 RTC_CRITICAL_SECTION_ENTER();
5962 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
5963 RTC_CRITICAL_SECTION_LEAVE();
5964 }
5965
hri_rtcmode1_set_EVCTRL_reg(const void * const hw,hri_rtcmode1_evctrl_reg_t mask)5966 static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
5967 {
5968 RTC_CRITICAL_SECTION_ENTER();
5969 ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
5970 RTC_CRITICAL_SECTION_LEAVE();
5971 }
5972
hri_rtcmode1_get_EVCTRL_reg(const void * const hw,hri_rtcmode1_evctrl_reg_t mask)5973 static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw,
5974 hri_rtcmode1_evctrl_reg_t mask)
5975 {
5976 uint32_t tmp;
5977 tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
5978 tmp &= mask;
5979 return tmp;
5980 }
5981
hri_rtcmode1_write_EVCTRL_reg(const void * const hw,hri_rtcmode1_evctrl_reg_t data)5982 static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
5983 {
5984 RTC_CRITICAL_SECTION_ENTER();
5985 ((Rtc *)hw)->MODE1.EVCTRL.reg = data;
5986 RTC_CRITICAL_SECTION_LEAVE();
5987 }
5988
hri_rtcmode1_clear_EVCTRL_reg(const void * const hw,hri_rtcmode1_evctrl_reg_t mask)5989 static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
5990 {
5991 RTC_CRITICAL_SECTION_ENTER();
5992 ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
5993 RTC_CRITICAL_SECTION_LEAVE();
5994 }
5995
hri_rtcmode1_toggle_EVCTRL_reg(const void * const hw,hri_rtcmode1_evctrl_reg_t mask)5996 static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
5997 {
5998 RTC_CRITICAL_SECTION_ENTER();
5999 ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
6000 RTC_CRITICAL_SECTION_LEAVE();
6001 }
6002
hri_rtcmode1_read_EVCTRL_reg(const void * const hw)6003 static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
6004 {
6005 return ((Rtc *)hw)->MODE1.EVCTRL.reg;
6006 }
6007
hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void * const hw)6008 static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw)
6009 {
6010 RTC_CRITICAL_SECTION_ENTER();
6011 ((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
6012 RTC_CRITICAL_SECTION_LEAVE();
6013 }
6014
hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void * const hw)6015 static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw)
6016 {
6017 uint8_t tmp;
6018 tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
6019 tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
6020 return (bool)tmp;
6021 }
6022
hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)6023 static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
6024 {
6025 uint8_t tmp;
6026 RTC_CRITICAL_SECTION_ENTER();
6027 tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
6028 tmp &= ~RTC_DBGCTRL_DBGRUN;
6029 tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
6030 ((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp;
6031 RTC_CRITICAL_SECTION_LEAVE();
6032 }
6033
hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void * const hw)6034 static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
6035 {
6036 RTC_CRITICAL_SECTION_ENTER();
6037 ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
6038 RTC_CRITICAL_SECTION_LEAVE();
6039 }
6040
hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)6041 static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
6042 {
6043 RTC_CRITICAL_SECTION_ENTER();
6044 ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
6045 RTC_CRITICAL_SECTION_LEAVE();
6046 }
6047
hri_rtcmode1_set_DBGCTRL_reg(const void * const hw,hri_rtcmode1_dbgctrl_reg_t mask)6048 static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
6049 {
6050 RTC_CRITICAL_SECTION_ENTER();
6051 ((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask;
6052 RTC_CRITICAL_SECTION_LEAVE();
6053 }
6054
hri_rtcmode1_get_DBGCTRL_reg(const void * const hw,hri_rtcmode1_dbgctrl_reg_t mask)6055 static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const hw,
6056 hri_rtcmode1_dbgctrl_reg_t mask)
6057 {
6058 uint8_t tmp;
6059 tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg;
6060 tmp &= mask;
6061 return tmp;
6062 }
6063
hri_rtcmode1_write_DBGCTRL_reg(const void * const hw,hri_rtcmode1_dbgctrl_reg_t data)6064 static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data)
6065 {
6066 RTC_CRITICAL_SECTION_ENTER();
6067 ((Rtc *)hw)->MODE1.DBGCTRL.reg = data;
6068 RTC_CRITICAL_SECTION_LEAVE();
6069 }
6070
hri_rtcmode1_clear_DBGCTRL_reg(const void * const hw,hri_rtcmode1_dbgctrl_reg_t mask)6071 static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
6072 {
6073 RTC_CRITICAL_SECTION_ENTER();
6074 ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask;
6075 RTC_CRITICAL_SECTION_LEAVE();
6076 }
6077
hri_rtcmode1_toggle_DBGCTRL_reg(const void * const hw,hri_rtcmode1_dbgctrl_reg_t mask)6078 static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask)
6079 {
6080 RTC_CRITICAL_SECTION_ENTER();
6081 ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask;
6082 RTC_CRITICAL_SECTION_LEAVE();
6083 }
6084
hri_rtcmode1_read_DBGCTRL_reg(const void * const hw)6085 static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw)
6086 {
6087 return ((Rtc *)hw)->MODE1.DBGCTRL.reg;
6088 }
6089
hri_rtcmode1_set_FREQCORR_SIGN_bit(const void * const hw)6090 static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw)
6091 {
6092 RTC_CRITICAL_SECTION_ENTER();
6093 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6094 ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN;
6095 RTC_CRITICAL_SECTION_LEAVE();
6096 }
6097
hri_rtcmode1_get_FREQCORR_SIGN_bit(const void * const hw)6098 static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw)
6099 {
6100 uint8_t tmp;
6101 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6102 tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
6103 return (bool)tmp;
6104 }
6105
hri_rtcmode1_write_FREQCORR_SIGN_bit(const void * const hw,bool value)6106 static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
6107 {
6108 uint8_t tmp;
6109 RTC_CRITICAL_SECTION_ENTER();
6110 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6111 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6112 tmp &= ~RTC_FREQCORR_SIGN;
6113 tmp |= value << RTC_FREQCORR_SIGN_Pos;
6114 ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp;
6115 RTC_CRITICAL_SECTION_LEAVE();
6116 }
6117
hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void * const hw)6118 static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw)
6119 {
6120 RTC_CRITICAL_SECTION_ENTER();
6121 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6122 ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
6123 RTC_CRITICAL_SECTION_LEAVE();
6124 }
6125
hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void * const hw)6126 static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw)
6127 {
6128 RTC_CRITICAL_SECTION_ENTER();
6129 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6130 ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
6131 RTC_CRITICAL_SECTION_LEAVE();
6132 }
6133
hri_rtcmode1_set_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6134 static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6135 {
6136 RTC_CRITICAL_SECTION_ENTER();
6137 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6138 ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
6139 RTC_CRITICAL_SECTION_LEAVE();
6140 }
6141
hri_rtcmode1_get_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6142 static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const hw,
6143 hri_rtcmode1_freqcorr_reg_t mask)
6144 {
6145 uint8_t tmp;
6146 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6147 tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
6148 return tmp;
6149 }
6150
hri_rtcmode1_write_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode1_freqcorr_reg_t data)6151 static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data)
6152 {
6153 uint8_t tmp;
6154 RTC_CRITICAL_SECTION_ENTER();
6155 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6156 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6157 tmp &= ~RTC_FREQCORR_VALUE_Msk;
6158 tmp |= RTC_FREQCORR_VALUE(data);
6159 ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp;
6160 RTC_CRITICAL_SECTION_LEAVE();
6161 }
6162
hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6163 static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6164 {
6165 RTC_CRITICAL_SECTION_ENTER();
6166 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6167 ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
6168 RTC_CRITICAL_SECTION_LEAVE();
6169 }
6170
hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6171 static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6172 {
6173 RTC_CRITICAL_SECTION_ENTER();
6174 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6175 ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
6176 RTC_CRITICAL_SECTION_LEAVE();
6177 }
6178
hri_rtcmode1_read_FREQCORR_VALUE_bf(const void * const hw)6179 static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw)
6180 {
6181 uint8_t tmp;
6182 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6183 tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
6184 return tmp;
6185 }
6186
hri_rtcmode1_set_FREQCORR_reg(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6187 static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6188 {
6189 RTC_CRITICAL_SECTION_ENTER();
6190 ((Rtc *)hw)->MODE1.FREQCORR.reg |= mask;
6191 RTC_CRITICAL_SECTION_LEAVE();
6192 }
6193
hri_rtcmode1_get_FREQCORR_reg(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6194 static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const hw,
6195 hri_rtcmode1_freqcorr_reg_t mask)
6196 {
6197 uint8_t tmp;
6198 tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg;
6199 tmp &= mask;
6200 return tmp;
6201 }
6202
hri_rtcmode1_write_FREQCORR_reg(const void * const hw,hri_rtcmode1_freqcorr_reg_t data)6203 static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data)
6204 {
6205 RTC_CRITICAL_SECTION_ENTER();
6206 ((Rtc *)hw)->MODE1.FREQCORR.reg = data;
6207 RTC_CRITICAL_SECTION_LEAVE();
6208 }
6209
hri_rtcmode1_clear_FREQCORR_reg(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6210 static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6211 {
6212 RTC_CRITICAL_SECTION_ENTER();
6213 ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask;
6214 RTC_CRITICAL_SECTION_LEAVE();
6215 }
6216
hri_rtcmode1_toggle_FREQCORR_reg(const void * const hw,hri_rtcmode1_freqcorr_reg_t mask)6217 static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask)
6218 {
6219 RTC_CRITICAL_SECTION_ENTER();
6220 ((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask;
6221 RTC_CRITICAL_SECTION_LEAVE();
6222 }
6223
hri_rtcmode1_read_FREQCORR_reg(const void * const hw)6224 static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw)
6225 {
6226 return ((Rtc *)hw)->MODE1.FREQCORR.reg;
6227 }
6228
hri_rtcmode1_set_COUNT_COUNT_bf(const void * const hw,hri_rtcmode1_count_reg_t mask)6229 static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
6230 {
6231 RTC_CRITICAL_SECTION_ENTER();
6232 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6233 ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
6234 RTC_CRITICAL_SECTION_LEAVE();
6235 }
6236
hri_rtcmode1_get_COUNT_COUNT_bf(const void * const hw,hri_rtcmode1_count_reg_t mask)6237 static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw,
6238 hri_rtcmode1_count_reg_t mask)
6239 {
6240 uint16_t tmp;
6241 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6242 tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
6243 tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
6244 return tmp;
6245 }
6246
hri_rtcmode1_write_COUNT_COUNT_bf(const void * const hw,hri_rtcmode1_count_reg_t data)6247 static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
6248 {
6249 uint16_t tmp;
6250 RTC_CRITICAL_SECTION_ENTER();
6251 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6252 tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
6253 tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
6254 tmp |= RTC_MODE1_COUNT_COUNT(data);
6255 ((Rtc *)hw)->MODE1.COUNT.reg = tmp;
6256 RTC_CRITICAL_SECTION_LEAVE();
6257 }
6258
hri_rtcmode1_clear_COUNT_COUNT_bf(const void * const hw,hri_rtcmode1_count_reg_t mask)6259 static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
6260 {
6261 RTC_CRITICAL_SECTION_ENTER();
6262 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6263 ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
6264 RTC_CRITICAL_SECTION_LEAVE();
6265 }
6266
hri_rtcmode1_toggle_COUNT_COUNT_bf(const void * const hw,hri_rtcmode1_count_reg_t mask)6267 static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
6268 {
6269 RTC_CRITICAL_SECTION_ENTER();
6270 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6271 ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
6272 RTC_CRITICAL_SECTION_LEAVE();
6273 }
6274
hri_rtcmode1_read_COUNT_COUNT_bf(const void * const hw)6275 static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
6276 {
6277 uint16_t tmp;
6278 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
6279 tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
6280 tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
6281 return tmp;
6282 }
6283
hri_rtcmode1_set_COUNT_reg(const void * const hw,hri_rtcmode1_count_reg_t mask)6284 static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
6285 {
6286 RTC_CRITICAL_SECTION_ENTER();
6287 ((Rtc *)hw)->MODE1.COUNT.reg |= mask;
6288 RTC_CRITICAL_SECTION_LEAVE();
6289 }
6290
hri_rtcmode1_get_COUNT_reg(const void * const hw,hri_rtcmode1_count_reg_t mask)6291 static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
6292 {
6293 uint16_t tmp;
6294 tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
6295 tmp &= mask;
6296 return tmp;
6297 }
6298
hri_rtcmode1_write_COUNT_reg(const void * const hw,hri_rtcmode1_count_reg_t data)6299 static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
6300 {
6301 RTC_CRITICAL_SECTION_ENTER();
6302 ((Rtc *)hw)->MODE1.COUNT.reg = data;
6303 RTC_CRITICAL_SECTION_LEAVE();
6304 }
6305
hri_rtcmode1_clear_COUNT_reg(const void * const hw,hri_rtcmode1_count_reg_t mask)6306 static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
6307 {
6308 RTC_CRITICAL_SECTION_ENTER();
6309 ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
6310 RTC_CRITICAL_SECTION_LEAVE();
6311 }
6312
hri_rtcmode1_toggle_COUNT_reg(const void * const hw,hri_rtcmode1_count_reg_t mask)6313 static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
6314 {
6315 RTC_CRITICAL_SECTION_ENTER();
6316 ((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
6317 RTC_CRITICAL_SECTION_LEAVE();
6318 }
6319
hri_rtcmode1_read_COUNT_reg(const void * const hw)6320 static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
6321 {
6322 return ((Rtc *)hw)->MODE1.COUNT.reg;
6323 }
6324
hri_rtcmode1_set_PER_PER_bf(const void * const hw,hri_rtcmode1_per_reg_t mask)6325 static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
6326 {
6327 RTC_CRITICAL_SECTION_ENTER();
6328 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6329 ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
6330 RTC_CRITICAL_SECTION_LEAVE();
6331 }
6332
hri_rtcmode1_get_PER_PER_bf(const void * const hw,hri_rtcmode1_per_reg_t mask)6333 static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
6334 {
6335 uint16_t tmp;
6336 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6337 tmp = ((Rtc *)hw)->MODE1.PER.reg;
6338 tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
6339 return tmp;
6340 }
6341
hri_rtcmode1_write_PER_PER_bf(const void * const hw,hri_rtcmode1_per_reg_t data)6342 static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
6343 {
6344 uint16_t tmp;
6345 RTC_CRITICAL_SECTION_ENTER();
6346 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6347 tmp = ((Rtc *)hw)->MODE1.PER.reg;
6348 tmp &= ~RTC_MODE1_PER_PER_Msk;
6349 tmp |= RTC_MODE1_PER_PER(data);
6350 ((Rtc *)hw)->MODE1.PER.reg = tmp;
6351 RTC_CRITICAL_SECTION_LEAVE();
6352 }
6353
hri_rtcmode1_clear_PER_PER_bf(const void * const hw,hri_rtcmode1_per_reg_t mask)6354 static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
6355 {
6356 RTC_CRITICAL_SECTION_ENTER();
6357 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6358 ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
6359 RTC_CRITICAL_SECTION_LEAVE();
6360 }
6361
hri_rtcmode1_toggle_PER_PER_bf(const void * const hw,hri_rtcmode1_per_reg_t mask)6362 static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
6363 {
6364 RTC_CRITICAL_SECTION_ENTER();
6365 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6366 ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
6367 RTC_CRITICAL_SECTION_LEAVE();
6368 }
6369
hri_rtcmode1_read_PER_PER_bf(const void * const hw)6370 static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
6371 {
6372 uint16_t tmp;
6373 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
6374 tmp = ((Rtc *)hw)->MODE1.PER.reg;
6375 tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
6376 return tmp;
6377 }
6378
hri_rtcmode1_set_PER_reg(const void * const hw,hri_rtcmode1_per_reg_t mask)6379 static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
6380 {
6381 RTC_CRITICAL_SECTION_ENTER();
6382 ((Rtc *)hw)->MODE1.PER.reg |= mask;
6383 RTC_CRITICAL_SECTION_LEAVE();
6384 }
6385
hri_rtcmode1_get_PER_reg(const void * const hw,hri_rtcmode1_per_reg_t mask)6386 static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
6387 {
6388 uint16_t tmp;
6389 tmp = ((Rtc *)hw)->MODE1.PER.reg;
6390 tmp &= mask;
6391 return tmp;
6392 }
6393
hri_rtcmode1_write_PER_reg(const void * const hw,hri_rtcmode1_per_reg_t data)6394 static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
6395 {
6396 RTC_CRITICAL_SECTION_ENTER();
6397 ((Rtc *)hw)->MODE1.PER.reg = data;
6398 RTC_CRITICAL_SECTION_LEAVE();
6399 }
6400
hri_rtcmode1_clear_PER_reg(const void * const hw,hri_rtcmode1_per_reg_t mask)6401 static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
6402 {
6403 RTC_CRITICAL_SECTION_ENTER();
6404 ((Rtc *)hw)->MODE1.PER.reg &= ~mask;
6405 RTC_CRITICAL_SECTION_LEAVE();
6406 }
6407
hri_rtcmode1_toggle_PER_reg(const void * const hw,hri_rtcmode1_per_reg_t mask)6408 static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
6409 {
6410 RTC_CRITICAL_SECTION_ENTER();
6411 ((Rtc *)hw)->MODE1.PER.reg ^= mask;
6412 RTC_CRITICAL_SECTION_LEAVE();
6413 }
6414
hri_rtcmode1_read_PER_reg(const void * const hw)6415 static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
6416 {
6417 return ((Rtc *)hw)->MODE1.PER.reg;
6418 }
6419
hri_rtcmode1_set_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6420 static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6421 {
6422 RTC_CRITICAL_SECTION_ENTER();
6423 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6424 ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
6425 RTC_CRITICAL_SECTION_LEAVE();
6426 }
6427
hri_rtcmode1_get_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6428 static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
6429 hri_rtcmode1_comp_reg_t mask)
6430 {
6431 uint16_t tmp;
6432 tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
6433 tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
6434 return tmp;
6435 }
6436
hri_rtcmode1_write_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t data)6437 static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
6438 {
6439 uint16_t tmp;
6440 RTC_CRITICAL_SECTION_ENTER();
6441 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6442 tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
6443 tmp &= ~RTC_MODE1_COMP_COMP_Msk;
6444 tmp |= RTC_MODE1_COMP_COMP(data);
6445 ((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
6446 RTC_CRITICAL_SECTION_LEAVE();
6447 }
6448
hri_rtcmode1_clear_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6449 static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6450 {
6451 RTC_CRITICAL_SECTION_ENTER();
6452 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6453 ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
6454 RTC_CRITICAL_SECTION_LEAVE();
6455 }
6456
hri_rtcmode1_toggle_COMP_COMP_bf(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6457 static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6458 {
6459 RTC_CRITICAL_SECTION_ENTER();
6460 hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
6461 ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
6462 RTC_CRITICAL_SECTION_LEAVE();
6463 }
6464
hri_rtcmode1_read_COMP_COMP_bf(const void * const hw,uint8_t index)6465 static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
6466 {
6467 uint16_t tmp;
6468 tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
6469 tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
6470 return tmp;
6471 }
6472
hri_rtcmode1_set_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6473 static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6474 {
6475 RTC_CRITICAL_SECTION_ENTER();
6476 ((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
6477 RTC_CRITICAL_SECTION_LEAVE();
6478 }
6479
hri_rtcmode1_get_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6480 static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
6481 hri_rtcmode1_comp_reg_t mask)
6482 {
6483 uint16_t tmp;
6484 tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
6485 tmp &= mask;
6486 return tmp;
6487 }
6488
hri_rtcmode1_write_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t data)6489 static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
6490 {
6491 RTC_CRITICAL_SECTION_ENTER();
6492 ((Rtc *)hw)->MODE1.COMP[index].reg = data;
6493 RTC_CRITICAL_SECTION_LEAVE();
6494 }
6495
hri_rtcmode1_clear_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6496 static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6497 {
6498 RTC_CRITICAL_SECTION_ENTER();
6499 ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
6500 RTC_CRITICAL_SECTION_LEAVE();
6501 }
6502
hri_rtcmode1_toggle_COMP_reg(const void * const hw,uint8_t index,hri_rtcmode1_comp_reg_t mask)6503 static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
6504 {
6505 RTC_CRITICAL_SECTION_ENTER();
6506 ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
6507 RTC_CRITICAL_SECTION_LEAVE();
6508 }
6509
hri_rtcmode1_read_COMP_reg(const void * const hw,uint8_t index)6510 static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
6511 {
6512 return ((Rtc *)hw)->MODE1.COMP[index].reg;
6513 }
6514
hri_rtcmode1_set_GP_reg(const void * const hw,uint8_t index,hri_rtcmode1_gp_reg_t mask)6515 static inline void hri_rtcmode1_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask)
6516 {
6517 RTC_CRITICAL_SECTION_ENTER();
6518 ((Rtc *)hw)->MODE1.GP[index].reg |= mask;
6519 RTC_CRITICAL_SECTION_LEAVE();
6520 }
6521
hri_rtcmode1_get_GP_reg(const void * const hw,uint8_t index,hri_rtcmode1_gp_reg_t mask)6522 static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_get_GP_reg(const void *const hw, uint8_t index,
6523 hri_rtcmode1_gp_reg_t mask)
6524 {
6525 uint32_t tmp;
6526 tmp = ((Rtc *)hw)->MODE1.GP[index].reg;
6527 tmp &= mask;
6528 return tmp;
6529 }
6530
hri_rtcmode1_write_GP_reg(const void * const hw,uint8_t index,hri_rtcmode1_gp_reg_t data)6531 static inline void hri_rtcmode1_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t data)
6532 {
6533 RTC_CRITICAL_SECTION_ENTER();
6534 ((Rtc *)hw)->MODE1.GP[index].reg = data;
6535 RTC_CRITICAL_SECTION_LEAVE();
6536 }
6537
hri_rtcmode1_clear_GP_reg(const void * const hw,uint8_t index,hri_rtcmode1_gp_reg_t mask)6538 static inline void hri_rtcmode1_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask)
6539 {
6540 RTC_CRITICAL_SECTION_ENTER();
6541 ((Rtc *)hw)->MODE1.GP[index].reg &= ~mask;
6542 RTC_CRITICAL_SECTION_LEAVE();
6543 }
6544
hri_rtcmode1_toggle_GP_reg(const void * const hw,uint8_t index,hri_rtcmode1_gp_reg_t mask)6545 static inline void hri_rtcmode1_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask)
6546 {
6547 RTC_CRITICAL_SECTION_ENTER();
6548 ((Rtc *)hw)->MODE1.GP[index].reg ^= mask;
6549 RTC_CRITICAL_SECTION_LEAVE();
6550 }
6551
hri_rtcmode1_read_GP_reg(const void * const hw,uint8_t index)6552 static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_read_GP_reg(const void *const hw, uint8_t index)
6553 {
6554 return ((Rtc *)hw)->MODE1.GP[index].reg;
6555 }
6556
hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void * const hw)6557 static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
6558 {
6559 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
6560 }
6561
hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void * const hw)6562 static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
6563 {
6564 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
6565 }
6566
hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void * const hw)6567 static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
6568 {
6569 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
6570 }
6571
hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void * const hw)6572 static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
6573 {
6574 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
6575 }
6576
hri_rtcmode1_get_SYNCBUSY_PER_bit(const void * const hw)6577 static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
6578 {
6579 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
6580 }
6581
hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void * const hw)6582 static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
6583 {
6584 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
6585 }
6586
hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void * const hw)6587 static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
6588 {
6589 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
6590 }
6591
hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void * const hw)6592 static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
6593 {
6594 return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
6595 }
6596
hri_rtcmode1_get_SYNCBUSY_reg(const void * const hw,hri_rtcmode1_syncbusy_reg_t mask)6597 static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw,
6598 hri_rtcmode1_syncbusy_reg_t mask)
6599 {
6600 uint32_t tmp;
6601 tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
6602 tmp &= mask;
6603 return tmp;
6604 }
6605
hri_rtcmode1_read_SYNCBUSY_reg(const void * const hw)6606 static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
6607 {
6608 return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
6609 }
6610
6611 #ifdef __cplusplus
6612 }
6613 #endif
6614
6615 #endif /* _HRI_RTC_L21_H_INCLUDED */
6616 #endif /* _SAML21_RTC_COMPONENT_ */
6617
