1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_RCC_H 38 #define __STM32L4xx_HAL_RCC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup RCC 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup RCC_Exported_Types RCC Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief RCC PLL configuration structure definition 62 */ 63 typedef struct 64 { 65 uint32_t PLLState; /*!< The new state of the PLL. 66 This parameter can be a value of @ref RCC_PLL_Config */ 67 68 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 69 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 70 71 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 72 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ 74 75 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 76 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 77 78 #if defined(RCC_PLLP_SUPPORT) 79 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 81 #endif /* RCC_PLLP_SUPPORT */ 82 83 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 84 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 85 86 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 87 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ 88 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. 89 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 90 91 }RCC_PLLInitTypeDef; 92 93 /** 94 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 95 */ 96 typedef struct 97 { 98 uint32_t OscillatorType; /*!< The oscillators to be configured. 99 This parameter can be a value of @ref RCC_Oscillator_Type */ 100 101 uint32_t HSEState; /*!< The new state of the HSE. 102 This parameter can be a value of @ref RCC_HSE_Config */ 103 104 uint32_t LSEState; /*!< The new state of the LSE. 105 This parameter can be a value of @ref RCC_LSE_Config */ 106 107 uint32_t HSIState; /*!< The new state of the HSI. 108 This parameter can be a value of @ref RCC_HSI_Config */ 109 110 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 111 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ 113 114 uint32_t LSIState; /*!< The new state of the LSI. 115 This parameter can be a value of @ref RCC_LSI_Config */ 116 #if defined(RCC_CSR_LSIPREDIV) 117 118 uint32_t LSIDiv; /*!< The division factor of the LSI. 119 This parameter can be a value of @ref RCC_LSI_Div */ 120 #endif /* RCC_CSR_LSIPREDIV */ 121 122 uint32_t MSIState; /*!< The new state of the MSI. 123 This parameter can be a value of @ref RCC_MSI_Config */ 124 125 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 126 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 127 128 uint32_t MSIClockRange; /*!< The MSI frequency range. 129 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 130 131 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 132 This parameter can be a value of @ref RCC_HSI48_Config */ 133 134 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 135 136 }RCC_OscInitTypeDef; 137 138 /** 139 * @brief RCC System, AHB and APB busses clock configuration structure definition 140 */ 141 typedef struct 142 { 143 uint32_t ClockType; /*!< The clock to be configured. 144 This parameter can be a value of @ref RCC_System_Clock_Type */ 145 146 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 147 This parameter can be a value of @ref RCC_System_Clock_Source */ 148 149 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 150 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 151 152 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 153 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 154 155 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 156 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 157 158 }RCC_ClkInitTypeDef; 159 160 /** 161 * @} 162 */ 163 164 /* Exported constants --------------------------------------------------------*/ 165 /** @defgroup RCC_Exported_Constants RCC Exported Constants 166 * @{ 167 */ 168 169 /** @defgroup RCC_Timeout_Value Timeout Values 170 * @{ 171 */ 172 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 173 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 174 /** 175 * @} 176 */ 177 178 /** @defgroup RCC_Oscillator_Type Oscillator Type 179 * @{ 180 */ 181 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 182 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 183 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 184 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 185 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 186 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 187 #if defined(RCC_HSI48_SUPPORT) 188 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 189 #endif /* RCC_HSI48_SUPPORT */ 190 /** 191 * @} 192 */ 193 194 /** @defgroup RCC_HSE_Config HSE Config 195 * @{ 196 */ 197 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 198 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 199 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 200 /** 201 * @} 202 */ 203 204 /** @defgroup RCC_LSE_Config LSE Config 205 * @{ 206 */ 207 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 208 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 209 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 210 #if defined(RCC_BDCR_LSESYSDIS) 211 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ 212 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ 213 #endif /* RCC_BDCR_LSESYSDIS */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup RCC_HSI_Config HSI Config 219 * @{ 220 */ 221 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 222 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 223 224 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ 225 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 226 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 227 #else 228 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ 229 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ 230 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup RCC_LSI_Config LSI Config 236 * @{ 237 */ 238 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 239 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 240 /** 241 * @} 242 */ 243 #if defined(RCC_CSR_LSIPREDIV) 244 245 /** @defgroup RCC_LSI_Div LSI Div 246 * @{ 247 */ 248 #define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ 249 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ 250 /** 251 * @} 252 */ 253 #endif /* RCC_CSR_LSIPREDIV */ 254 255 /** @defgroup RCC_MSI_Config MSI Config 256 * @{ 257 */ 258 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 259 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 260 261 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 262 /** 263 * @} 264 */ 265 266 #if defined(RCC_HSI48_SUPPORT) 267 /** @defgroup RCC_HSI48_Config HSI48 Config 268 * @{ 269 */ 270 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 271 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 272 /** 273 * @} 274 */ 275 #else 276 /** @defgroup RCC_HSI48_Config HSI48 Config 277 * @{ 278 */ 279 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 280 /** 281 * @} 282 */ 283 #endif /* RCC_HSI48_SUPPORT */ 284 285 /** @defgroup RCC_PLL_Config PLL Config 286 * @{ 287 */ 288 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 289 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 290 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 291 /** 292 * @} 293 */ 294 295 #if defined(RCC_PLLP_SUPPORT) 296 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 297 * @{ 298 */ 299 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 300 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 301 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 302 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 303 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 304 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 305 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 306 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 307 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 308 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 309 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 310 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 311 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 312 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 313 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 314 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 315 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 316 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 317 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 318 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 319 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 320 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 321 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 322 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 323 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 324 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 325 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 326 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 327 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 328 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 329 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 330 #else 331 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 332 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 333 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 334 /** 335 * @} 336 */ 337 #endif /* RCC_PLLP_SUPPORT */ 338 339 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 340 * @{ 341 */ 342 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 343 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 344 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 345 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 351 * @{ 352 */ 353 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 354 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 355 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 356 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 362 * @{ 363 */ 364 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 365 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 366 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 367 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 373 * @{ 374 */ 375 #if defined(RCC_PLLSAI2_SUPPORT) 376 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 377 #elif defined(RCC_PLLSAI1_SUPPORT) 378 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 379 #endif /* RCC_PLLSAI2_SUPPORT */ 380 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 381 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 382 /** 383 * @} 384 */ 385 #if defined(RCC_PLLSAI1_SUPPORT) 386 387 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 388 * @{ 389 */ 390 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 391 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 392 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 393 /** 394 * @} 395 */ 396 #endif /* RCC_PLLSAI1_SUPPORT */ 397 398 #if defined(RCC_PLLSAI2_SUPPORT) 399 400 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 401 * @{ 402 */ 403 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 404 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 405 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ 406 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 407 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 408 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 409 #else 410 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ 411 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 412 /** 413 * @} 414 */ 415 416 #endif /* RCC_PLLSAI2_SUPPORT */ 417 418 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 419 * @{ 420 */ 421 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 422 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 423 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 424 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 425 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 426 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 427 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 428 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 429 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 430 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 431 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 432 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 433 /** 434 * @} 435 */ 436 437 /** @defgroup RCC_System_Clock_Type System Clock Type 438 * @{ 439 */ 440 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 441 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 442 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 443 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup RCC_System_Clock_Source System Clock Source 449 * @{ 450 */ 451 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 452 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 453 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 454 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 460 * @{ 461 */ 462 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 463 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 464 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 465 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 466 /** 467 * @} 468 */ 469 470 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 471 * @{ 472 */ 473 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 474 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 475 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 476 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 477 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 478 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 479 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 480 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 481 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 487 * @{ 488 */ 489 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 490 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 491 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 492 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 493 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 499 * @{ 500 */ 501 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 502 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 503 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 504 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCC_MCO_Index MCO Index 510 * @{ 511 */ 512 #define RCC_MCO1 0x00000000U 513 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 514 /** 515 * @} 516 */ 517 518 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 519 * @{ 520 */ 521 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 522 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 523 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 524 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 525 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 526 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 527 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 528 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 529 #if defined(RCC_HSI48_SUPPORT) 530 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 531 #endif /* RCC_HSI48_SUPPORT */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 537 * @{ 538 */ 539 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 540 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 541 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 542 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 543 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup RCC_Interrupt Interrupts 549 * @{ 550 */ 551 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 552 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 553 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 554 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 555 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 556 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 557 #if defined(RCC_PLLSAI1_SUPPORT) 558 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 559 #endif /* RCC_PLLSAI1_SUPPORT */ 560 #if defined(RCC_PLLSAI2_SUPPORT) 561 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 562 #endif /* RCC_PLLSAI2_SUPPORT */ 563 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 564 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 565 #if defined(RCC_HSI48_SUPPORT) 566 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 567 #endif /* RCC_HSI48_SUPPORT */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup RCC_Flag Flags 573 * Elements values convention: XXXYYYYYb 574 * - YYYYY : Flag position in the register 575 * - XXX : Register index 576 * - 001: CR register 577 * - 010: BDCR register 578 * - 011: CSR register 579 * - 100: CRRCR register 580 * @{ 581 */ 582 /* Flags in the CR register */ 583 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 584 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 585 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 586 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 587 #if defined(RCC_PLLSAI1_SUPPORT) 588 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 589 #endif /* RCC_PLLSAI1_SUPPORT */ 590 #if defined(RCC_PLLSAI2_SUPPORT) 591 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 592 #endif /* RCC_PLLSAI2_SUPPORT */ 593 594 /* Flags in the BDCR register */ 595 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 596 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 597 598 /* Flags in the CSR register */ 599 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 600 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ 601 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 602 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 603 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 604 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 605 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 606 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 607 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 608 609 #if defined(RCC_HSI48_SUPPORT) 610 /* Flags in the CRRCR register */ 611 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 612 #endif /* RCC_HSI48_SUPPORT */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 618 * @{ 619 */ 620 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 621 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 622 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 623 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 629 * @{ 630 */ 631 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 632 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 633 /** 634 * @} 635 */ 636 637 /** 638 * @} 639 */ 640 641 /* Exported macros -----------------------------------------------------------*/ 642 643 /** @defgroup RCC_Exported_Macros RCC Exported Macros 644 * @{ 645 */ 646 647 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 648 * @brief Enable or disable the AHB1 peripheral clock. 649 * @note After reset, the peripheral clock (used for registers read/write access) 650 * is disabled and the application software has to enable this clock before 651 * using it. 652 * @{ 653 */ 654 655 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 656 __IO uint32_t tmpreg; \ 657 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 658 /* Delay after an RCC peripheral clock enabling */ \ 659 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 660 UNUSED(tmpreg); \ 661 } while(0) 662 663 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 664 __IO uint32_t tmpreg; \ 665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 666 /* Delay after an RCC peripheral clock enabling */ \ 667 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 668 UNUSED(tmpreg); \ 669 } while(0) 670 671 #if defined(DMAMUX1) 672 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 673 __IO uint32_t tmpreg; \ 674 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 675 /* Delay after an RCC peripheral clock enabling */ \ 676 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 677 UNUSED(tmpreg); \ 678 } while(0) 679 #endif /* DMAMUX1 */ 680 681 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 682 __IO uint32_t tmpreg; \ 683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 684 /* Delay after an RCC peripheral clock enabling */ \ 685 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 686 UNUSED(tmpreg); \ 687 } while(0) 688 689 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 690 __IO uint32_t tmpreg; \ 691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 692 /* Delay after an RCC peripheral clock enabling */ \ 693 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 694 UNUSED(tmpreg); \ 695 } while(0) 696 697 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 698 __IO uint32_t tmpreg; \ 699 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 700 /* Delay after an RCC peripheral clock enabling */ \ 701 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 702 UNUSED(tmpreg); \ 703 } while(0) 704 705 #if defined(DMA2D) 706 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 707 __IO uint32_t tmpreg; \ 708 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 709 /* Delay after an RCC peripheral clock enabling */ \ 710 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 711 UNUSED(tmpreg); \ 712 } while(0) 713 #endif /* DMA2D */ 714 715 #if defined(GFXMMU) 716 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 717 __IO uint32_t tmpreg; \ 718 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 719 /* Delay after an RCC peripheral clock enabling */ \ 720 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 721 UNUSED(tmpreg); \ 722 } while(0) 723 #endif /* GFXMMU */ 724 725 726 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 727 728 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 729 730 #if defined(DMAMUX1) 731 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 732 #endif /* DMAMUX1 */ 733 734 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 735 736 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 737 738 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 739 740 #if defined(DMA2D) 741 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 742 #endif /* DMA2D */ 743 744 #if defined(GFXMMU) 745 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 746 #endif /* GFXMMU */ 747 748 /** 749 * @} 750 */ 751 752 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 753 * @brief Enable or disable the AHB2 peripheral clock. 754 * @note After reset, the peripheral clock (used for registers read/write access) 755 * is disabled and the application software has to enable this clock before 756 * using it. 757 * @{ 758 */ 759 760 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 761 __IO uint32_t tmpreg; \ 762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 763 /* Delay after an RCC peripheral clock enabling */ \ 764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 765 UNUSED(tmpreg); \ 766 } while(0) 767 768 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 769 __IO uint32_t tmpreg; \ 770 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 771 /* Delay after an RCC peripheral clock enabling */ \ 772 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 773 UNUSED(tmpreg); \ 774 } while(0) 775 776 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 777 __IO uint32_t tmpreg; \ 778 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 779 /* Delay after an RCC peripheral clock enabling */ \ 780 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 781 UNUSED(tmpreg); \ 782 } while(0) 783 784 #if defined(GPIOD) 785 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 786 __IO uint32_t tmpreg; \ 787 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 788 /* Delay after an RCC peripheral clock enabling */ \ 789 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 790 UNUSED(tmpreg); \ 791 } while(0) 792 #endif /* GPIOD */ 793 794 #if defined(GPIOE) 795 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 796 __IO uint32_t tmpreg; \ 797 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 798 /* Delay after an RCC peripheral clock enabling */ \ 799 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 800 UNUSED(tmpreg); \ 801 } while(0) 802 #endif /* GPIOE */ 803 804 #if defined(GPIOF) 805 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 806 __IO uint32_t tmpreg; \ 807 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 808 /* Delay after an RCC peripheral clock enabling */ \ 809 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 810 UNUSED(tmpreg); \ 811 } while(0) 812 #endif /* GPIOF */ 813 814 #if defined(GPIOG) 815 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 816 __IO uint32_t tmpreg; \ 817 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 818 /* Delay after an RCC peripheral clock enabling */ \ 819 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 820 UNUSED(tmpreg); \ 821 } while(0) 822 #endif /* GPIOG */ 823 824 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 825 __IO uint32_t tmpreg; \ 826 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 827 /* Delay after an RCC peripheral clock enabling */ \ 828 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 829 UNUSED(tmpreg); \ 830 } while(0) 831 832 #if defined(GPIOI) 833 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 834 __IO uint32_t tmpreg; \ 835 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 836 /* Delay after an RCC peripheral clock enabling */ \ 837 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 838 UNUSED(tmpreg); \ 839 } while(0) 840 #endif /* GPIOI */ 841 842 #if defined(USB_OTG_FS) 843 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 844 __IO uint32_t tmpreg; \ 845 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 846 /* Delay after an RCC peripheral clock enabling */ \ 847 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 848 UNUSED(tmpreg); \ 849 } while(0) 850 #endif /* USB_OTG_FS */ 851 852 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 853 __IO uint32_t tmpreg; \ 854 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 855 /* Delay after an RCC peripheral clock enabling */ \ 856 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 857 UNUSED(tmpreg); \ 858 } while(0) 859 860 #if defined(DCMI) 861 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 862 __IO uint32_t tmpreg; \ 863 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 864 /* Delay after an RCC peripheral clock enabling */ \ 865 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 866 UNUSED(tmpreg); \ 867 } while(0) 868 #endif /* DCMI */ 869 870 #if defined(AES) 871 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 872 __IO uint32_t tmpreg; \ 873 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 874 /* Delay after an RCC peripheral clock enabling */ \ 875 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 876 UNUSED(tmpreg); \ 877 } while(0) 878 #endif /* AES */ 879 880 #if defined(HASH) 881 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 882 __IO uint32_t tmpreg; \ 883 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 884 /* Delay after an RCC peripheral clock enabling */ \ 885 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 886 UNUSED(tmpreg); \ 887 } while(0) 888 #endif /* HASH */ 889 890 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 891 __IO uint32_t tmpreg; \ 892 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 893 /* Delay after an RCC peripheral clock enabling */ \ 894 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 895 UNUSED(tmpreg); \ 896 } while(0) 897 898 #if defined(OCTOSPIM) 899 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 900 __IO uint32_t tmpreg; \ 901 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 902 /* Delay after an RCC peripheral clock enabling */ \ 903 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 904 UNUSED(tmpreg); \ 905 } while(0) 906 #endif /* OCTOSPIM */ 907 908 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 909 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 910 __IO uint32_t tmpreg; \ 911 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 912 /* Delay after an RCC peripheral clock enabling */ \ 913 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 914 UNUSED(tmpreg); \ 915 } while(0) 916 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 917 918 919 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 920 921 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 922 923 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 924 925 #if defined(GPIOD) 926 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 927 #endif /* GPIOD */ 928 929 #if defined(GPIOE) 930 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 931 #endif /* GPIOE */ 932 933 #if defined(GPIOF) 934 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 935 #endif /* GPIOF */ 936 937 #if defined(GPIOG) 938 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 939 #endif /* GPIOG */ 940 941 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 942 943 #if defined(GPIOI) 944 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 945 #endif /* GPIOI */ 946 947 #if defined(USB_OTG_FS) 948 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 949 #endif /* USB_OTG_FS */ 950 951 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 952 953 #if defined(DCMI) 954 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) 955 #endif /* DCMI */ 956 957 #if defined(AES) 958 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 959 #endif /* AES */ 960 961 #if defined(HASH) 962 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 963 #endif /* HASH */ 964 965 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 966 967 #if defined(OCTOSPIM) 968 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) 969 #endif /* OCTOSPIM */ 970 971 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 972 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 973 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 974 975 /** 976 * @} 977 */ 978 979 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 980 * @brief Enable or disable the AHB3 peripheral clock. 981 * @note After reset, the peripheral clock (used for registers read/write access) 982 * is disabled and the application software has to enable this clock before 983 * using it. 984 * @{ 985 */ 986 987 #if defined(FMC_BANK1) 988 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 989 __IO uint32_t tmpreg; \ 990 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 991 /* Delay after an RCC peripheral clock enabling */ \ 992 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 993 UNUSED(tmpreg); \ 994 } while(0) 995 #endif /* FMC_BANK1 */ 996 997 #if defined(QUADSPI) 998 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 999 __IO uint32_t tmpreg; \ 1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1001 /* Delay after an RCC peripheral clock enabling */ \ 1002 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1003 UNUSED(tmpreg); \ 1004 } while(0) 1005 #endif /* QUADSPI */ 1006 1007 #if defined(OCTOSPI1) 1008 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1009 __IO uint32_t tmpreg; \ 1010 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1011 /* Delay after an RCC peripheral clock enabling */ \ 1012 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1013 UNUSED(tmpreg); \ 1014 } while(0) 1015 #endif /* OCTOSPI1 */ 1016 1017 #if defined(OCTOSPI2) 1018 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1019 __IO uint32_t tmpreg; \ 1020 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1021 /* Delay after an RCC peripheral clock enabling */ \ 1022 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1023 UNUSED(tmpreg); \ 1024 } while(0) 1025 #endif /* OCTOSPI2 */ 1026 1027 #if defined(FMC_BANK1) 1028 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 1029 #endif /* FMC_BANK1 */ 1030 1031 #if defined(QUADSPI) 1032 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 1033 #endif /* QUADSPI */ 1034 1035 #if defined(OCTOSPI1) 1036 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 1037 #endif /* OCTOSPI1 */ 1038 1039 #if defined(OCTOSPI2) 1040 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) 1041 #endif /* OCTOSPI2 */ 1042 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1048 * @brief Enable or disable the APB1 peripheral clock. 1049 * @note After reset, the peripheral clock (used for registers read/write access) 1050 * is disabled and the application software has to enable this clock before 1051 * using it. 1052 * @{ 1053 */ 1054 1055 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1056 __IO uint32_t tmpreg; \ 1057 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1058 /* Delay after an RCC peripheral clock enabling */ \ 1059 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1060 UNUSED(tmpreg); \ 1061 } while(0) 1062 1063 #if defined(TIM3) 1064 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1065 __IO uint32_t tmpreg; \ 1066 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1067 /* Delay after an RCC peripheral clock enabling */ \ 1068 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1069 UNUSED(tmpreg); \ 1070 } while(0) 1071 #endif /* TIM3 */ 1072 1073 #if defined(TIM4) 1074 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1075 __IO uint32_t tmpreg; \ 1076 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1077 /* Delay after an RCC peripheral clock enabling */ \ 1078 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1079 UNUSED(tmpreg); \ 1080 } while(0) 1081 #endif /* TIM4 */ 1082 1083 #if defined(TIM5) 1084 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1085 __IO uint32_t tmpreg; \ 1086 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1087 /* Delay after an RCC peripheral clock enabling */ \ 1088 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1089 UNUSED(tmpreg); \ 1090 } while(0) 1091 #endif /* TIM5 */ 1092 1093 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1094 __IO uint32_t tmpreg; \ 1095 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1096 /* Delay after an RCC peripheral clock enabling */ \ 1097 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1098 UNUSED(tmpreg); \ 1099 } while(0) 1100 1101 #if defined(TIM7) 1102 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1103 __IO uint32_t tmpreg; \ 1104 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1105 /* Delay after an RCC peripheral clock enabling */ \ 1106 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1107 UNUSED(tmpreg); \ 1108 } while(0) 1109 #endif /* TIM7 */ 1110 1111 #if defined(LCD) 1112 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 1113 __IO uint32_t tmpreg; \ 1114 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1115 /* Delay after an RCC peripheral clock enabling */ \ 1116 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1117 UNUSED(tmpreg); \ 1118 } while(0) 1119 #endif /* LCD */ 1120 1121 #if defined(RCC_APB1ENR1_RTCAPBEN) 1122 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1123 __IO uint32_t tmpreg; \ 1124 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1125 /* Delay after an RCC peripheral clock enabling */ \ 1126 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1127 UNUSED(tmpreg); \ 1128 } while(0) 1129 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1130 1131 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1132 __IO uint32_t tmpreg; \ 1133 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1134 /* Delay after an RCC peripheral clock enabling */ \ 1135 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1136 UNUSED(tmpreg); \ 1137 } while(0) 1138 1139 #if defined(SPI2) 1140 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1141 __IO uint32_t tmpreg; \ 1142 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1143 /* Delay after an RCC peripheral clock enabling */ \ 1144 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1145 UNUSED(tmpreg); \ 1146 } while(0) 1147 #endif /* SPI2 */ 1148 1149 #if defined(SPI3) 1150 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1151 __IO uint32_t tmpreg; \ 1152 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1153 /* Delay after an RCC peripheral clock enabling */ \ 1154 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1155 UNUSED(tmpreg); \ 1156 } while(0) 1157 #endif /* SPI3 */ 1158 1159 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1160 __IO uint32_t tmpreg; \ 1161 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1162 /* Delay after an RCC peripheral clock enabling */ \ 1163 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1164 UNUSED(tmpreg); \ 1165 } while(0) 1166 1167 #if defined(USART3) 1168 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1169 __IO uint32_t tmpreg; \ 1170 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1171 /* Delay after an RCC peripheral clock enabling */ \ 1172 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1173 UNUSED(tmpreg); \ 1174 } while(0) 1175 #endif /* USART3 */ 1176 1177 #if defined(UART4) 1178 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1179 __IO uint32_t tmpreg; \ 1180 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1181 /* Delay after an RCC peripheral clock enabling */ \ 1182 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1183 UNUSED(tmpreg); \ 1184 } while(0) 1185 #endif /* UART4 */ 1186 1187 #if defined(UART5) 1188 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1189 __IO uint32_t tmpreg; \ 1190 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1191 /* Delay after an RCC peripheral clock enabling */ \ 1192 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1193 UNUSED(tmpreg); \ 1194 } while(0) 1195 #endif /* UART5 */ 1196 1197 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1198 __IO uint32_t tmpreg; \ 1199 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1200 /* Delay after an RCC peripheral clock enabling */ \ 1201 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1202 UNUSED(tmpreg); \ 1203 } while(0) 1204 1205 #if defined(I2C2) 1206 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1207 __IO uint32_t tmpreg; \ 1208 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1209 /* Delay after an RCC peripheral clock enabling */ \ 1210 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1211 UNUSED(tmpreg); \ 1212 } while(0) 1213 #endif /* I2C2 */ 1214 1215 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1216 __IO uint32_t tmpreg; \ 1217 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1218 /* Delay after an RCC peripheral clock enabling */ \ 1219 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1220 UNUSED(tmpreg); \ 1221 } while(0) 1222 1223 #if defined(I2C4) 1224 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1225 __IO uint32_t tmpreg; \ 1226 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1227 /* Delay after an RCC peripheral clock enabling */ \ 1228 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1229 UNUSED(tmpreg); \ 1230 } while(0) 1231 #endif /* I2C4 */ 1232 1233 #if defined(CRS) 1234 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1235 __IO uint32_t tmpreg; \ 1236 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1237 /* Delay after an RCC peripheral clock enabling */ \ 1238 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1239 UNUSED(tmpreg); \ 1240 } while(0) 1241 #endif /* CRS */ 1242 1243 #if defined(CAN1) 1244 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1249 UNUSED(tmpreg); \ 1250 } while(0) 1251 #endif /* CAN1 */ 1252 1253 #if defined(CAN2) 1254 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1255 __IO uint32_t tmpreg; \ 1256 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1257 /* Delay after an RCC peripheral clock enabling */ \ 1258 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1259 UNUSED(tmpreg); \ 1260 } while(0) 1261 #endif /* CAN2 */ 1262 1263 #if defined(USB) 1264 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1265 __IO uint32_t tmpreg; \ 1266 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1267 /* Delay after an RCC peripheral clock enabling */ \ 1268 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1269 UNUSED(tmpreg); \ 1270 } while(0) 1271 #endif /* USB */ 1272 1273 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1274 __IO uint32_t tmpreg; \ 1275 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1276 /* Delay after an RCC peripheral clock enabling */ \ 1277 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1278 UNUSED(tmpreg); \ 1279 } while(0) 1280 1281 #if defined(DAC1) 1282 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1283 __IO uint32_t tmpreg; \ 1284 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1285 /* Delay after an RCC peripheral clock enabling */ \ 1286 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1287 UNUSED(tmpreg); \ 1288 } while(0) 1289 #endif /* DAC1 */ 1290 1291 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1292 __IO uint32_t tmpreg; \ 1293 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1294 /* Delay after an RCC peripheral clock enabling */ \ 1295 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1296 UNUSED(tmpreg); \ 1297 } while(0) 1298 1299 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1300 __IO uint32_t tmpreg; \ 1301 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1302 /* Delay after an RCC peripheral clock enabling */ \ 1303 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1304 UNUSED(tmpreg); \ 1305 } while(0) 1306 1307 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1308 __IO uint32_t tmpreg; \ 1309 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1310 /* Delay after an RCC peripheral clock enabling */ \ 1311 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1312 UNUSED(tmpreg); \ 1313 } while(0) 1314 1315 #if defined(SWPMI1) 1316 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 1317 __IO uint32_t tmpreg; \ 1318 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1319 /* Delay after an RCC peripheral clock enabling */ \ 1320 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1321 UNUSED(tmpreg); \ 1322 } while(0) 1323 #endif /* SWPMI1 */ 1324 1325 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1326 __IO uint32_t tmpreg; \ 1327 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1328 /* Delay after an RCC peripheral clock enabling */ \ 1329 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1330 UNUSED(tmpreg); \ 1331 } while(0) 1332 1333 1334 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1335 1336 #if defined(TIM3) 1337 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1338 #endif /* TIM3 */ 1339 1340 #if defined(TIM4) 1341 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1342 #endif /* TIM4 */ 1343 1344 #if defined(TIM5) 1345 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1346 #endif /* TIM5 */ 1347 1348 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1349 1350 #if defined(TIM7) 1351 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1352 #endif /* TIM7 */ 1353 1354 #if defined(LCD) 1355 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 1356 #endif /* LCD */ 1357 1358 #if defined(RCC_APB1ENR1_RTCAPBEN) 1359 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1360 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1361 1362 #if defined(SPI2) 1363 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1364 #endif /* SPI2 */ 1365 1366 #if defined(SPI3) 1367 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1368 #endif /* SPI3 */ 1369 1370 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1371 1372 #if defined(USART3) 1373 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1374 #endif /* USART3 */ 1375 1376 #if defined(UART4) 1377 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1378 #endif /* UART4 */ 1379 1380 #if defined(UART5) 1381 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1382 #endif /* UART5 */ 1383 1384 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1385 1386 #if defined(I2C2) 1387 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1388 #endif /* I2C2 */ 1389 1390 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1391 1392 #if defined(I2C4) 1393 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1394 #endif /* I2C4 */ 1395 1396 #if defined(CRS) 1397 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1398 #endif /* CRS */ 1399 1400 #if defined(CAN1) 1401 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 1402 #endif /* CAN1 */ 1403 1404 #if defined(CAN2) 1405 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) 1406 #endif /* CAN2 */ 1407 1408 #if defined(USB) 1409 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 1410 #endif /* USB */ 1411 1412 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1413 1414 #if defined(DAC1) 1415 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 1416 #endif /* DAC1 */ 1417 1418 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 1419 1420 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1421 1422 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1423 1424 #if defined(SWPMI1) 1425 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 1426 #endif /* SWPMI1 */ 1427 1428 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1429 1430 /** 1431 * @} 1432 */ 1433 1434 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1435 * @brief Enable or disable the APB2 peripheral clock. 1436 * @note After reset, the peripheral clock (used for registers read/write access) 1437 * is disabled and the application software has to enable this clock before 1438 * using it. 1439 * @{ 1440 */ 1441 1442 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1443 __IO uint32_t tmpreg; \ 1444 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1445 /* Delay after an RCC peripheral clock enabling */ \ 1446 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1447 UNUSED(tmpreg); \ 1448 } while(0) 1449 1450 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 1451 __IO uint32_t tmpreg; \ 1452 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1453 /* Delay after an RCC peripheral clock enabling */ \ 1454 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1455 UNUSED(tmpreg); \ 1456 } while(0) 1457 1458 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1459 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1460 __IO uint32_t tmpreg; \ 1461 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1462 /* Delay after an RCC peripheral clock enabling */ \ 1463 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1464 UNUSED(tmpreg); \ 1465 } while(0) 1466 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1467 1468 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1469 __IO uint32_t tmpreg; \ 1470 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1471 /* Delay after an RCC peripheral clock enabling */ \ 1472 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1473 UNUSED(tmpreg); \ 1474 } while(0) 1475 1476 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1477 __IO uint32_t tmpreg; \ 1478 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1479 /* Delay after an RCC peripheral clock enabling */ \ 1480 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1481 UNUSED(tmpreg); \ 1482 } while(0) 1483 1484 #if defined(TIM8) 1485 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1486 __IO uint32_t tmpreg; \ 1487 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1488 /* Delay after an RCC peripheral clock enabling */ \ 1489 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1490 UNUSED(tmpreg); \ 1491 } while(0) 1492 #endif /* TIM8 */ 1493 1494 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1495 __IO uint32_t tmpreg; \ 1496 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1497 /* Delay after an RCC peripheral clock enabling */ \ 1498 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1499 UNUSED(tmpreg); \ 1500 } while(0) 1501 1502 1503 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1504 __IO uint32_t tmpreg; \ 1505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1506 /* Delay after an RCC peripheral clock enabling */ \ 1507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1508 UNUSED(tmpreg); \ 1509 } while(0) 1510 1511 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1512 __IO uint32_t tmpreg; \ 1513 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1514 /* Delay after an RCC peripheral clock enabling */ \ 1515 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1516 UNUSED(tmpreg); \ 1517 } while(0) 1518 1519 #if defined(TIM17) 1520 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1521 __IO uint32_t tmpreg; \ 1522 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1523 /* Delay after an RCC peripheral clock enabling */ \ 1524 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1525 UNUSED(tmpreg); \ 1526 } while(0) 1527 #endif /* TIM17 */ 1528 1529 #if defined(SAI1) 1530 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1531 __IO uint32_t tmpreg; \ 1532 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1533 /* Delay after an RCC peripheral clock enabling */ \ 1534 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1535 UNUSED(tmpreg); \ 1536 } while(0) 1537 #endif /* SAI1 */ 1538 1539 #if defined(SAI2) 1540 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1541 __IO uint32_t tmpreg; \ 1542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1543 /* Delay after an RCC peripheral clock enabling */ \ 1544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1545 UNUSED(tmpreg); \ 1546 } while(0) 1547 #endif /* SAI2 */ 1548 1549 #if defined(DFSDM1_Filter0) 1550 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1551 __IO uint32_t tmpreg; \ 1552 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1553 /* Delay after an RCC peripheral clock enabling */ \ 1554 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1555 UNUSED(tmpreg); \ 1556 } while(0) 1557 #endif /* DFSDM1_Filter0 */ 1558 1559 #if defined(LTDC) 1560 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1561 __IO uint32_t tmpreg; \ 1562 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1563 /* Delay after an RCC peripheral clock enabling */ \ 1564 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1565 UNUSED(tmpreg); \ 1566 } while(0) 1567 #endif /* LTDC */ 1568 1569 #if defined(DSI) 1570 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1571 __IO uint32_t tmpreg; \ 1572 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1573 /* Delay after an RCC peripheral clock enabling */ \ 1574 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1575 UNUSED(tmpreg); \ 1576 } while(0) 1577 #endif /* DSI */ 1578 1579 1580 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1581 1582 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1583 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 1584 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1585 1586 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1587 1588 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1589 1590 #if defined(TIM8) 1591 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1592 #endif /* TIM8 */ 1593 1594 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1595 1596 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1597 1598 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1599 1600 #if defined(TIM17) 1601 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1602 #endif /* TIM17 */ 1603 1604 #if defined(SAI1) 1605 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1606 #endif /* SAI1 */ 1607 1608 #if defined(SAI2) 1609 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1610 #endif /* SAI2 */ 1611 1612 #if defined(DFSDM1_Filter0) 1613 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 1614 #endif /* DFSDM1_Filter0 */ 1615 1616 #if defined(LTDC) 1617 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 1618 #endif /* LTDC */ 1619 1620 #if defined(DSI) 1621 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) 1622 #endif /* DSI */ 1623 1624 /** 1625 * @} 1626 */ 1627 1628 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1629 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1630 * @note After reset, the peripheral clock (used for registers read/write access) 1631 * is disabled and the application software has to enable this clock before 1632 * using it. 1633 * @{ 1634 */ 1635 1636 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1637 1638 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1639 1640 #if defined(DMAMUX1) 1641 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1642 #endif /* DMAMUX1 */ 1643 1644 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1645 1646 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1647 1648 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1649 1650 #if defined(DMA2D) 1651 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 1652 #endif /* DMA2D */ 1653 1654 #if defined(GFXMMU) 1655 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 1656 #endif /* GFXMMU */ 1657 1658 1659 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1660 1661 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1662 1663 #if defined(DMAMUX1) 1664 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1665 #endif /* DMAMUX1 */ 1666 1667 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1668 1669 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1670 1671 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1672 1673 #if defined(DMA2D) 1674 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 1675 #endif /* DMA2D */ 1676 1677 #if defined(GFXMMU) 1678 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 1679 #endif /* GFXMMU */ 1680 1681 /** 1682 * @} 1683 */ 1684 1685 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1686 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1687 * @note After reset, the peripheral clock (used for registers read/write access) 1688 * is disabled and the application software has to enable this clock before 1689 * using it. 1690 * @{ 1691 */ 1692 1693 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1694 1695 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 1696 1697 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1698 1699 #if defined(GPIOD) 1700 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1701 #endif /* GPIOD */ 1702 1703 #if defined(GPIOE) 1704 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1705 #endif /* GPIOE */ 1706 1707 #if defined(GPIOF) 1708 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1709 #endif /* GPIOF */ 1710 1711 #if defined(GPIOG) 1712 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1713 #endif /* GPIOG */ 1714 1715 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1716 1717 #if defined(GPIOI) 1718 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 1719 #endif /* GPIOI */ 1720 1721 #if defined(USB_OTG_FS) 1722 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) 1723 #endif /* USB_OTG_FS */ 1724 1725 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 1726 1727 #if defined(DCMI) 1728 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) 1729 #endif /* DCMI */ 1730 1731 #if defined(AES) 1732 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1733 #endif /* AES */ 1734 1735 #if defined(HASH) 1736 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1737 #endif /* HASH */ 1738 1739 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1740 1741 1742 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1743 1744 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1745 1746 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1747 1748 #if defined(GPIOD) 1749 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1750 #endif /* GPIOD */ 1751 1752 #if defined(GPIOE) 1753 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1754 #endif /* GPIOE */ 1755 1756 #if defined(GPIOF) 1757 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1758 #endif /* GPIOF */ 1759 1760 #if defined(GPIOG) 1761 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1762 #endif /* GPIOG */ 1763 1764 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 1765 1766 #if defined(GPIOI) 1767 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 1768 #endif /* GPIOI */ 1769 1770 #if defined(USB_OTG_FS) 1771 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) 1772 #endif /* USB_OTG_FS */ 1773 1774 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 1775 1776 #if defined(DCMI) 1777 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) 1778 #endif /* DCMI */ 1779 1780 #if defined(AES) 1781 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1782 #endif /* AES */ 1783 1784 #if defined(HASH) 1785 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 1786 #endif /* HASH */ 1787 1788 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1789 1790 /** 1791 * @} 1792 */ 1793 1794 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1795 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1796 * @note After reset, the peripheral clock (used for registers read/write access) 1797 * is disabled and the application software has to enable this clock before 1798 * using it. 1799 * @{ 1800 */ 1801 1802 #if defined(FMC_BANK1) 1803 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1804 #endif /* FMC_BANK1 */ 1805 1806 #if defined(QUADSPI) 1807 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) 1808 #endif /* QUADSPI */ 1809 1810 #if defined(FMC_BANK1) 1811 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1812 #endif /* FMC_BANK1 */ 1813 1814 #if defined(QUADSPI) 1815 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) 1816 #endif /* QUADSPI */ 1817 1818 /** 1819 * @} 1820 */ 1821 1822 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1823 * @brief Check whether the APB1 peripheral clock is enabled or not. 1824 * @note After reset, the peripheral clock (used for registers read/write access) 1825 * is disabled and the application software has to enable this clock before 1826 * using it. 1827 * @{ 1828 */ 1829 1830 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1831 1832 #if defined(TIM3) 1833 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1834 #endif /* TIM3 */ 1835 1836 #if defined(TIM4) 1837 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1838 #endif /* TIM4 */ 1839 1840 #if defined(TIM5) 1841 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1842 #endif /* TIM5 */ 1843 1844 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1845 1846 #if defined(TIM7) 1847 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1848 #endif /* TIM7 */ 1849 1850 #if defined(LCD) 1851 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) 1852 #endif /* LCD */ 1853 1854 #if defined(RCC_APB1ENR1_RTCAPBEN) 1855 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1856 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1857 1858 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1859 1860 #if defined(SPI2) 1861 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1862 #endif /* SPI2 */ 1863 1864 #if defined(SPI3) 1865 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1866 #endif /* SPI3 */ 1867 1868 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1869 1870 #if defined(USART3) 1871 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1872 #endif /* USART3 */ 1873 1874 #if defined(UART4) 1875 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1876 #endif /* UART4 */ 1877 1878 #if defined(UART5) 1879 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1880 #endif /* UART5 */ 1881 1882 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1883 1884 #if defined(I2C2) 1885 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1886 #endif /* I2C2 */ 1887 1888 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1889 1890 #if defined(I2C4) 1891 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1892 #endif /* I2C4 */ 1893 1894 #if defined(CRS) 1895 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1896 #endif /* CRS */ 1897 1898 #if defined(CAN1) 1899 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) 1900 #endif /* CAN1 */ 1901 1902 #if defined(CAN2) 1903 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) 1904 #endif /* CAN2 */ 1905 1906 #if defined(USB) 1907 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 1908 #endif /* USB */ 1909 1910 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1911 1912 #if defined(DAC1) 1913 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 1914 #endif /* DAC1 */ 1915 1916 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 1917 1918 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1919 1920 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1921 1922 #if defined(SWPMI1) 1923 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) 1924 #endif /* SWPMI1 */ 1925 1926 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1927 1928 1929 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1930 1931 #if defined(TIM3) 1932 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1933 #endif /* TIM3 */ 1934 1935 #if defined(TIM4) 1936 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1937 #endif /* TIM4 */ 1938 1939 #if defined(TIM5) 1940 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1941 #endif /* TIM5 */ 1942 1943 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1944 1945 #if defined(TIM7) 1946 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1947 #endif /* TIM7 */ 1948 1949 #if defined(LCD) 1950 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) 1951 #endif /* LCD */ 1952 1953 #if defined(RCC_APB1ENR1_RTCAPBEN) 1954 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 1955 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1956 1957 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 1958 1959 #if defined(SPI2) 1960 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1961 #endif /* SPI2 */ 1962 1963 #if defined(SPI3) 1964 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 1965 #endif /* SPI3 */ 1966 1967 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1968 1969 #if defined(USART3) 1970 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1971 #endif /* USART3 */ 1972 1973 #if defined(UART4) 1974 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1975 #endif /* UART4 */ 1976 1977 #if defined(UART5) 1978 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1979 #endif /* UART5 */ 1980 1981 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1982 1983 #if defined(I2C2) 1984 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1985 #endif /* I2C2 */ 1986 1987 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 1988 1989 #if defined(I2C4) 1990 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1991 #endif /* I2C4 */ 1992 1993 #if defined(CRS) 1994 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1995 #endif /* CRS */ 1996 1997 #if defined(CAN1) 1998 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) 1999 #endif /* CAN1 */ 2000 2001 #if defined(CAN2) 2002 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) 2003 #endif /* CAN2 */ 2004 2005 #if defined(USB) 2006 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 2007 #endif /* USB */ 2008 2009 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 2010 2011 #if defined(DAC1) 2012 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 2013 #endif /* DAC1 */ 2014 2015 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 2016 2017 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 2018 2019 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 2020 2021 #if defined(SWPMI1) 2022 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) 2023 #endif /* SWPMI1 */ 2024 2025 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 2026 2027 /** 2028 * @} 2029 */ 2030 2031 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2032 * @brief Check whether the APB2 peripheral clock is enabled or not. 2033 * @note After reset, the peripheral clock (used for registers read/write access) 2034 * is disabled and the application software has to enable this clock before 2035 * using it. 2036 * @{ 2037 */ 2038 2039 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 2040 2041 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 2042 2043 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2044 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) 2045 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2046 2047 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2048 2049 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2050 2051 #if defined(TIM8) 2052 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2053 #endif /* TIM8 */ 2054 2055 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2056 2057 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2058 2059 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2060 2061 #if defined(TIM17) 2062 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2063 #endif /* TIM17 */ 2064 2065 #if defined(SAI1) 2066 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2067 #endif /* SAI1 */ 2068 2069 #if defined(SAI2) 2070 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2071 #endif /* SAI2 */ 2072 2073 #if defined(DFSDM1_Filter0) 2074 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 2075 #endif /* DFSDM1_Filter0 */ 2076 2077 #if defined(LTDC) 2078 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 2079 #endif /* LTDC */ 2080 2081 #if defined(DSI) 2082 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) 2083 #endif /* DSI */ 2084 2085 2086 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 2087 2088 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2089 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) 2090 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2091 2092 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2093 2094 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2095 2096 #if defined(TIM8) 2097 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2098 #endif /* TIM8 */ 2099 2100 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2101 2102 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2103 2104 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2105 2106 #if defined(TIM17) 2107 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2108 #endif /* TIM17 */ 2109 2110 #if defined(SAI1) 2111 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2112 #endif /* SAI1 */ 2113 2114 #if defined(SAI2) 2115 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2116 #endif /* SAI2 */ 2117 2118 #if defined(DFSDM1_Filter0) 2119 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 2120 #endif /* DFSDM1_Filter0 */ 2121 2122 #if defined(LTDC) 2123 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 2124 #endif /* LTDC */ 2125 2126 #if defined(DSI) 2127 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) 2128 #endif /* DSI */ 2129 2130 /** 2131 * @} 2132 */ 2133 2134 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2135 * @brief Force or release AHB1 peripheral reset. 2136 * @{ 2137 */ 2138 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 2139 2140 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2141 2142 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2143 2144 #if defined(DMAMUX1) 2145 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2146 #endif /* DMAMUX1 */ 2147 2148 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2149 2150 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2151 2152 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2153 2154 #if defined(DMA2D) 2155 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2156 #endif /* DMA2D */ 2157 2158 #if defined(GFXMMU) 2159 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2160 #endif /* GFXMMU */ 2161 2162 2163 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2164 2165 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2166 2167 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2168 2169 #if defined(DMAMUX1) 2170 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2171 #endif /* DMAMUX1 */ 2172 2173 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2174 2175 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2176 2177 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2178 2179 #if defined(DMA2D) 2180 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2181 #endif /* DMA2D */ 2182 2183 #if defined(GFXMMU) 2184 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2185 #endif /* GFXMMU */ 2186 2187 /** 2188 * @} 2189 */ 2190 2191 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2192 * @brief Force or release AHB2 peripheral reset. 2193 * @{ 2194 */ 2195 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 2196 2197 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2198 2199 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2200 2201 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2202 2203 #if defined(GPIOD) 2204 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2205 #endif /* GPIOD */ 2206 2207 #if defined(GPIOE) 2208 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2209 #endif /* GPIOE */ 2210 2211 #if defined(GPIOF) 2212 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2213 #endif /* GPIOF */ 2214 2215 #if defined(GPIOG) 2216 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2217 #endif /* GPIOG */ 2218 2219 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2220 2221 #if defined(GPIOI) 2222 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2223 #endif /* GPIOI */ 2224 2225 #if defined(USB_OTG_FS) 2226 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2227 #endif /* USB_OTG_FS */ 2228 2229 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2230 2231 #if defined(DCMI) 2232 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2233 #endif /* DCMI */ 2234 2235 #if defined(AES) 2236 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2237 #endif /* AES */ 2238 2239 #if defined(HASH) 2240 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2241 #endif /* HASH */ 2242 2243 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2244 2245 #if defined(OCTOSPIM) 2246 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2247 #endif /* OCTOSPIM */ 2248 2249 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2250 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2251 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2252 2253 2254 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 2255 2256 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2257 2258 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2259 2260 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2261 2262 #if defined(GPIOD) 2263 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2264 #endif /* GPIOD */ 2265 2266 #if defined(GPIOE) 2267 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2268 #endif /* GPIOE */ 2269 2270 #if defined(GPIOF) 2271 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2272 #endif /* GPIOF */ 2273 2274 #if defined(GPIOG) 2275 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2276 #endif /* GPIOG */ 2277 2278 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2279 2280 #if defined(GPIOI) 2281 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2282 #endif /* GPIOI */ 2283 2284 #if defined(USB_OTG_FS) 2285 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2286 #endif /* USB_OTG_FS */ 2287 2288 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2289 2290 #if defined(DCMI) 2291 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2292 #endif /* DCMI */ 2293 2294 #if defined(AES) 2295 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2296 #endif /* AES */ 2297 2298 #if defined(HASH) 2299 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2300 #endif /* HASH */ 2301 2302 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2303 2304 #if defined(OCTOSPIM) 2305 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2306 #endif /* OCTOSPIM */ 2307 2308 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2309 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2310 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2311 2312 /** 2313 * @} 2314 */ 2315 2316 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2317 * @brief Force or release AHB3 peripheral reset. 2318 * @{ 2319 */ 2320 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) 2321 2322 #if defined(FMC_BANK1) 2323 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2324 #endif /* FMC_BANK1 */ 2325 2326 #if defined(QUADSPI) 2327 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2328 #endif /* QUADSPI */ 2329 2330 #if defined(OCTOSPI1) 2331 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2332 #endif /* OCTOSPI1 */ 2333 2334 #if defined(OCTOSPI2) 2335 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2336 #endif /* OCTOSPI2 */ 2337 2338 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2339 2340 #if defined(FMC_BANK1) 2341 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2342 #endif /* FMC_BANK1 */ 2343 2344 #if defined(QUADSPI) 2345 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2346 #endif /* QUADSPI */ 2347 2348 #if defined(OCTOSPI1) 2349 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2350 #endif /* OCTOSPI1 */ 2351 2352 #if defined(OCTOSPI2) 2353 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2354 #endif /* OCTOSPI2 */ 2355 2356 /** 2357 * @} 2358 */ 2359 2360 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2361 * @brief Force or release APB1 peripheral reset. 2362 * @{ 2363 */ 2364 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) 2365 2366 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2367 2368 #if defined(TIM3) 2369 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2370 #endif /* TIM3 */ 2371 2372 #if defined(TIM4) 2373 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2374 #endif /* TIM4 */ 2375 2376 #if defined(TIM5) 2377 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2378 #endif /* TIM5 */ 2379 2380 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2381 2382 #if defined(TIM7) 2383 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2384 #endif /* TIM7 */ 2385 2386 #if defined(LCD) 2387 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2388 #endif /* LCD */ 2389 2390 #if defined(SPI2) 2391 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2392 #endif /* SPI2 */ 2393 2394 #if defined(SPI3) 2395 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2396 #endif /* SPI3 */ 2397 2398 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2399 2400 #if defined(USART3) 2401 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2402 #endif /* USART3 */ 2403 2404 #if defined(UART4) 2405 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2406 #endif /* UART4 */ 2407 2408 #if defined(UART5) 2409 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2410 #endif /* UART5 */ 2411 2412 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2413 2414 #if defined(I2C2) 2415 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2416 #endif /* I2C2 */ 2417 2418 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2419 2420 #if defined(I2C4) 2421 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2422 #endif /* I2C4 */ 2423 2424 #if defined(CRS) 2425 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2426 #endif /* CRS */ 2427 2428 #if defined(CAN1) 2429 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2430 #endif /* CAN1 */ 2431 2432 #if defined(CAN2) 2433 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2434 #endif /* CAN2 */ 2435 2436 #if defined(USB) 2437 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2438 #endif /* USB */ 2439 2440 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2441 2442 #if defined(DAC1) 2443 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2444 #endif /* DAC1 */ 2445 2446 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2447 2448 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2449 2450 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2451 2452 #if defined(SWPMI1) 2453 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2454 #endif /* SWPMI1 */ 2455 2456 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2457 2458 2459 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) 2460 2461 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2462 2463 #if defined(TIM3) 2464 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2465 #endif /* TIM3 */ 2466 2467 #if defined(TIM4) 2468 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2469 #endif /* TIM4 */ 2470 2471 #if defined(TIM5) 2472 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2473 #endif /* TIM5 */ 2474 2475 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2476 2477 #if defined(TIM7) 2478 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2479 #endif /* TIM7 */ 2480 2481 #if defined(LCD) 2482 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2483 #endif /* LCD */ 2484 2485 #if defined(SPI2) 2486 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2487 #endif /* SPI2 */ 2488 2489 #if defined(SPI3) 2490 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2491 #endif /* SPI3 */ 2492 2493 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2494 2495 #if defined(USART3) 2496 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2497 #endif /* USART3 */ 2498 2499 #if defined(UART4) 2500 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2501 #endif /* UART4 */ 2502 2503 #if defined(UART5) 2504 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2505 #endif /* UART5 */ 2506 2507 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2508 2509 #if defined(I2C2) 2510 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2511 #endif /* I2C2 */ 2512 2513 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2514 2515 #if defined(I2C4) 2516 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2517 #endif /* I2C4 */ 2518 2519 #if defined(CRS) 2520 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2521 #endif /* CRS */ 2522 2523 #if defined(CAN1) 2524 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2525 #endif /* CAN1 */ 2526 2527 #if defined(CAN2) 2528 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2529 #endif /* CAN2 */ 2530 2531 #if defined(USB) 2532 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2533 #endif /* USB */ 2534 2535 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2536 2537 #if defined(DAC1) 2538 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2539 #endif /* DAC1 */ 2540 2541 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2542 2543 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2544 2545 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2546 2547 #if defined(SWPMI1) 2548 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2549 #endif /* SWPMI1 */ 2550 2551 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2552 2553 /** 2554 * @} 2555 */ 2556 2557 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2558 * @brief Force or release APB2 peripheral reset. 2559 * @{ 2560 */ 2561 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 2562 2563 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2564 2565 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2566 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2567 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2568 2569 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2570 2571 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2572 2573 #if defined(TIM8) 2574 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2575 #endif /* TIM8 */ 2576 2577 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2578 2579 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2580 2581 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2582 2583 #if defined(TIM17) 2584 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2585 #endif /* TIM17 */ 2586 2587 #if defined(SAI1) 2588 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2589 #endif /* SAI1 */ 2590 2591 #if defined(SAI2) 2592 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2593 #endif /* SAI2 */ 2594 2595 #if defined(DFSDM1_Filter0) 2596 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2597 #endif /* DFSDM1_Filter0 */ 2598 2599 #if defined(LTDC) 2600 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2601 #endif /* LTDC */ 2602 2603 #if defined(DSI) 2604 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2605 #endif /* DSI */ 2606 2607 2608 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 2609 2610 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2611 2612 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2613 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2614 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2615 2616 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2617 2618 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2619 2620 #if defined(TIM8) 2621 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2622 #endif /* TIM8 */ 2623 2624 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2625 2626 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2627 2628 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2629 2630 #if defined(TIM17) 2631 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2632 #endif /* TIM17 */ 2633 2634 #if defined(SAI1) 2635 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2636 #endif /* SAI1 */ 2637 2638 #if defined(SAI2) 2639 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2640 #endif /* SAI2 */ 2641 2642 #if defined(DFSDM1_Filter0) 2643 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2644 #endif /* DFSDM1_Filter0 */ 2645 2646 #if defined(LTDC) 2647 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2648 #endif /* LTDC */ 2649 2650 #if defined(DSI) 2651 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2652 #endif /* DSI */ 2653 2654 /** 2655 * @} 2656 */ 2657 2658 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2659 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2660 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2661 * power consumption. 2662 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2663 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2664 * @{ 2665 */ 2666 2667 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2668 2669 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2670 2671 #if defined(DMAMUX1) 2672 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2673 #endif /* DMAMUX1 */ 2674 2675 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2676 2677 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2678 2679 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2680 2681 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2682 2683 #if defined(DMA2D) 2684 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2685 #endif /* DMA2D */ 2686 2687 #if defined(GFXMMU) 2688 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2689 #endif /* GFXMMU */ 2690 2691 2692 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2693 2694 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2695 2696 #if defined(DMAMUX1) 2697 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2698 #endif /* DMAMUX1 */ 2699 2700 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2701 2702 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2703 2704 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2705 2706 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2707 2708 #if defined(DMA2D) 2709 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2710 #endif /* DMA2D */ 2711 2712 #if defined(GFXMMU) 2713 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2714 #endif /* GFXMMU */ 2715 2716 /** 2717 * @} 2718 */ 2719 2720 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2721 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2722 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2723 * power consumption. 2724 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2725 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2726 * @{ 2727 */ 2728 2729 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2730 2731 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2732 2733 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2734 2735 #if defined(GPIOD) 2736 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2737 #endif /* GPIOD */ 2738 2739 #if defined(GPIOE) 2740 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2741 #endif /* GPIOE */ 2742 2743 #if defined(GPIOF) 2744 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2745 #endif /* GPIOF */ 2746 2747 #if defined(GPIOG) 2748 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2749 #endif /* GPIOG */ 2750 2751 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2752 2753 #if defined(GPIOI) 2754 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2755 #endif /* GPIOI */ 2756 2757 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2758 2759 #if defined(SRAM3) 2760 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2761 #endif /* SRAM3 */ 2762 2763 #if defined(USB_OTG_FS) 2764 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2765 #endif /* USB_OTG_FS */ 2766 2767 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2768 2769 #if defined(DCMI) 2770 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2771 #endif /* DCMI */ 2772 2773 #if defined(AES) 2774 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2775 #endif /* AES */ 2776 2777 #if defined(HASH) 2778 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2779 #endif /* HASH */ 2780 2781 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2782 2783 #if defined(OCTOSPIM) 2784 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2785 #endif /* OCTOSPIM */ 2786 2787 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2788 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2789 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2790 2791 2792 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2793 2794 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2795 2796 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2797 2798 #if defined(GPIOD) 2799 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2800 #endif /* GPIOD */ 2801 2802 #if defined(GPIOE) 2803 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2804 #endif /* GPIOE */ 2805 2806 #if defined(GPIOF) 2807 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2808 #endif /* GPIOF */ 2809 2810 #if defined(GPIOG) 2811 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2812 #endif /* GPIOG */ 2813 2814 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2815 2816 #if defined(GPIOI) 2817 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2818 #endif /* GPIOI */ 2819 2820 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2821 2822 #if defined(SRAM3) 2823 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2824 #endif /* SRAM3 */ 2825 2826 #if defined(USB_OTG_FS) 2827 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2828 #endif /* USB_OTG_FS */ 2829 2830 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2831 2832 #if defined(DCMI) 2833 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2834 #endif /* DCMI */ 2835 2836 #if defined(AES) 2837 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2838 #endif /* AES */ 2839 2840 #if defined(HASH) 2841 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2842 #endif /* HASH */ 2843 2844 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2845 2846 #if defined(OCTOSPIM) 2847 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2848 #endif /* OCTOSPIM */ 2849 2850 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2851 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2852 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2853 2854 /** 2855 * @} 2856 */ 2857 2858 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2859 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2860 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2861 * power consumption. 2862 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2863 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2864 * @{ 2865 */ 2866 2867 #if defined(QUADSPI) 2868 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2869 #endif /* QUADSPI */ 2870 2871 #if defined(OCTOSPI1) 2872 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2873 #endif /* OCTOSPI1 */ 2874 2875 #if defined(OCTOSPI2) 2876 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2877 #endif /* OCTOSPI2 */ 2878 2879 #if defined(FMC_BANK1) 2880 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2881 #endif /* FMC_BANK1 */ 2882 2883 #if defined(QUADSPI) 2884 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2885 #endif /* QUADSPI */ 2886 2887 #if defined(OCTOSPI1) 2888 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2889 #endif /* OCTOSPI1 */ 2890 2891 #if defined(OCTOSPI2) 2892 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2893 #endif /* OCTOSPI2 */ 2894 2895 #if defined(FMC_BANK1) 2896 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2897 #endif /* FMC_BANK1 */ 2898 2899 /** 2900 * @} 2901 */ 2902 2903 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2904 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2906 * power consumption. 2907 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2908 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2909 * @{ 2910 */ 2911 2912 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2913 2914 #if defined(TIM3) 2915 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2916 #endif /* TIM3 */ 2917 2918 #if defined(TIM4) 2919 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2920 #endif /* TIM4 */ 2921 2922 #if defined(TIM5) 2923 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2924 #endif /* TIM5 */ 2925 2926 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2927 2928 #if defined(TIM7) 2929 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2930 #endif /* TIM7 */ 2931 2932 #if defined(LCD) 2933 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 2934 #endif /* LCD */ 2935 2936 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 2937 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2938 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 2939 2940 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2941 2942 #if defined(SPI2) 2943 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2944 #endif /* SPI2 */ 2945 2946 #if defined(SPI3) 2947 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2948 #endif /* SPI3 */ 2949 2950 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2951 2952 #if defined(USART3) 2953 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2954 #endif /* USART3 */ 2955 2956 #if defined(UART4) 2957 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2958 #endif /* UART4 */ 2959 2960 #if defined(UART5) 2961 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2962 #endif /* UART5 */ 2963 2964 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2965 2966 #if defined(I2C2) 2967 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2968 #endif /* I2C2 */ 2969 2970 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2971 2972 #if defined(I2C4) 2973 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2974 #endif /* I2C4 */ 2975 2976 #if defined(CRS) 2977 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2978 #endif /* CRS */ 2979 2980 #if defined(CAN1) 2981 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 2982 #endif /* CAN1 */ 2983 2984 #if defined(CAN2) 2985 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 2986 #endif /* CAN2 */ 2987 2988 #if defined(USB) 2989 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 2990 #endif /* USB */ 2991 2992 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2993 2994 #if defined(DAC1) 2995 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 2996 #endif /* DAC1 */ 2997 2998 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 2999 3000 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3001 3002 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3003 3004 #if defined(SWPMI1) 3005 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3006 #endif /* SWPMI1 */ 3007 3008 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3009 3010 3011 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3012 3013 #if defined(TIM3) 3014 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3015 #endif /* TIM3 */ 3016 3017 #if defined(TIM4) 3018 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3019 #endif /* TIM4 */ 3020 3021 #if defined(TIM5) 3022 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3023 #endif /* TIM5 */ 3024 3025 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3026 3027 #if defined(TIM7) 3028 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3029 #endif /* TIM7 */ 3030 3031 #if defined(LCD) 3032 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 3033 #endif /* LCD */ 3034 3035 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3036 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 3037 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3038 3039 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3040 3041 #if defined(SPI2) 3042 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3043 #endif /* SPI2 */ 3044 3045 #if defined(SPI3) 3046 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 3047 #endif /* SPI3 */ 3048 3049 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3050 3051 #if defined(USART3) 3052 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3053 #endif /* USART3 */ 3054 3055 #if defined(UART4) 3056 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3057 #endif /* UART4 */ 3058 3059 #if defined(UART5) 3060 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3061 #endif /* UART5 */ 3062 3063 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3064 3065 #if defined(I2C2) 3066 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3067 #endif /* I2C2 */ 3068 3069 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 3070 3071 #if defined(I2C4) 3072 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3073 #endif /* I2C4 */ 3074 3075 #if defined(CRS) 3076 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3077 #endif /* CRS */ 3078 3079 #if defined(CAN1) 3080 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 3081 #endif /* CAN1 */ 3082 3083 #if defined(CAN2) 3084 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 3085 #endif /* CAN2 */ 3086 3087 #if defined(USB) 3088 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 3089 #endif /* USB */ 3090 3091 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 3092 3093 #if defined(DAC1) 3094 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 3095 #endif /* DAC1 */ 3096 3097 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 3098 3099 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3100 3101 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3102 3103 #if defined(SWPMI1) 3104 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3105 #endif /* SWPMI1 */ 3106 3107 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3108 3109 /** 3110 * @} 3111 */ 3112 3113 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3114 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3115 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3116 * power consumption. 3117 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3118 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3119 * @{ 3120 */ 3121 3122 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3123 3124 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3125 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3126 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3127 3128 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3129 3130 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3131 3132 #if defined(TIM8) 3133 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3134 #endif /* TIM8 */ 3135 3136 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3137 3138 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3139 3140 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3141 3142 #if defined(TIM17) 3143 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3144 #endif /* TIM17 */ 3145 3146 #if defined(SAI1) 3147 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3148 #endif /* SAI1 */ 3149 3150 #if defined(SAI2) 3151 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3152 #endif /* SAI2 */ 3153 3154 #if defined(DFSDM1_Filter0) 3155 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3156 #endif /* DFSDM1_Filter0 */ 3157 3158 #if defined(LTDC) 3159 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3160 #endif /* LTDC */ 3161 3162 #if defined(DSI) 3163 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3164 #endif /* DSI */ 3165 3166 3167 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3168 3169 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3170 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3171 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3172 3173 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3174 3175 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3176 3177 #if defined(TIM8) 3178 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3179 #endif /* TIM8 */ 3180 3181 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3182 3183 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3184 3185 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3186 3187 #if defined(TIM17) 3188 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3189 #endif /* TIM17 */ 3190 3191 #if defined(SAI1) 3192 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3193 #endif /* SAI1 */ 3194 3195 #if defined(SAI2) 3196 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3197 #endif /* SAI2 */ 3198 3199 #if defined(DFSDM1_Filter0) 3200 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3201 #endif /* DFSDM1_Filter0 */ 3202 3203 #if defined(LTDC) 3204 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3205 #endif /* LTDC */ 3206 3207 #if defined(DSI) 3208 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3209 #endif /* DSI */ 3210 3211 /** 3212 * @} 3213 */ 3214 3215 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 3216 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3217 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3218 * power consumption. 3219 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3220 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3221 * @{ 3222 */ 3223 3224 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 3225 3226 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 3227 3228 #if defined(DMAMUX1) 3229 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 3230 #endif /* DMAMUX1 */ 3231 3232 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 3233 3234 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 3235 3236 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 3237 3238 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 3239 3240 #if defined(DMA2D) 3241 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) 3242 #endif /* DMA2D */ 3243 3244 #if defined(GFXMMU) 3245 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) 3246 #endif /* GFXMMU */ 3247 3248 3249 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 3250 3251 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 3252 3253 #if defined(DMAMUX1) 3254 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 3255 #endif /* DMAMUX1 */ 3256 3257 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 3258 3259 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 3260 3261 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 3262 3263 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 3264 3265 #if defined(DMA2D) 3266 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) 3267 #endif /* DMA2D */ 3268 3269 #if defined(GFXMMU) 3270 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) 3271 #endif /* GFXMMU */ 3272 3273 /** 3274 * @} 3275 */ 3276 3277 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 3278 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3279 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3280 * power consumption. 3281 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3282 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3283 * @{ 3284 */ 3285 3286 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 3287 3288 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 3289 3290 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 3291 3292 #if defined(GPIOD) 3293 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 3294 #endif /* GPIOD */ 3295 3296 #if defined(GPIOE) 3297 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 3298 #endif /* GPIOE */ 3299 3300 #if defined(GPIOF) 3301 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 3302 #endif /* GPIOF */ 3303 3304 #if defined(GPIOG) 3305 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 3306 #endif /* GPIOG */ 3307 3308 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 3309 3310 #if defined(GPIOI) 3311 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) 3312 #endif /* GPIOI */ 3313 3314 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 3315 3316 #if defined(SRAM3) 3317 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) 3318 #endif /* SRAM3 */ 3319 3320 #if defined(USB_OTG_FS) 3321 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) 3322 #endif /* USB_OTG_FS */ 3323 3324 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 3325 3326 #if defined(DCMI) 3327 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) 3328 #endif /* DCMI */ 3329 3330 #if defined(AES) 3331 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 3332 #endif /* AES */ 3333 3334 #if defined(HASH) 3335 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 3336 #endif /* HASH */ 3337 3338 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 3339 3340 #if defined(OCTOSPIM) 3341 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) 3342 #endif /* OCTOSPIM */ 3343 3344 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3345 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 3346 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3347 3348 3349 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 3350 3351 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 3352 3353 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 3354 3355 #if defined(GPIOD) 3356 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 3357 #endif /* GPIOD */ 3358 3359 #if defined(GPIOE) 3360 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 3361 #endif /* GPIOE */ 3362 3363 #if defined(GPIOF) 3364 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 3365 #endif /* GPIOF */ 3366 3367 #if defined(GPIOG) 3368 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 3369 #endif /* GPIOG */ 3370 3371 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 3372 3373 #if defined(GPIOI) 3374 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) 3375 #endif /* GPIOI */ 3376 3377 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 3378 3379 #if defined(SRAM3) 3380 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) 3381 #endif /* SRAM3 */ 3382 3383 #if defined(USB_OTG_FS) 3384 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) 3385 #endif /* USB_OTG_FS */ 3386 3387 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 3388 3389 #if defined(DCMI) 3390 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) 3391 #endif /* DCMI */ 3392 3393 #if defined(AES) 3394 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 3395 #endif /* AES */ 3396 3397 #if defined(HASH) 3398 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 3399 #endif /* HASH */ 3400 3401 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 3402 3403 #if defined(OCTOSPIM) 3404 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) 3405 #endif /* OCTOSPIM */ 3406 3407 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3408 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 3409 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3410 3411 /** 3412 * @} 3413 */ 3414 3415 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 3416 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 3417 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3418 * power consumption. 3419 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3420 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3421 * @{ 3422 */ 3423 3424 #if defined(QUADSPI) 3425 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) 3426 #endif /* QUADSPI */ 3427 3428 #if defined(OCTOSPI1) 3429 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) 3430 #endif /* OCTOSPI1 */ 3431 3432 #if defined(OCTOSPI2) 3433 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) 3434 #endif /* OCTOSPI2 */ 3435 3436 #if defined(FMC_BANK1) 3437 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 3438 #endif /* FMC_BANK1 */ 3439 3440 3441 #if defined(QUADSPI) 3442 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) 3443 #endif /* QUADSPI */ 3444 3445 #if defined(OCTOSPI1) 3446 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) 3447 #endif /* OCTOSPI1 */ 3448 3449 #if defined(OCTOSPI2) 3450 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) 3451 #endif /* OCTOSPI2 */ 3452 3453 #if defined(FMC_BANK1) 3454 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 3455 #endif /* FMC_BANK1 */ 3456 3457 /** 3458 * @} 3459 */ 3460 3461 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 3462 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3463 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3464 * power consumption. 3465 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3466 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3467 * @{ 3468 */ 3469 3470 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 3471 3472 #if defined(TIM3) 3473 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 3474 #endif /* TIM3 */ 3475 3476 #if defined(TIM4) 3477 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 3478 #endif /* TIM4 */ 3479 3480 #if defined(TIM5) 3481 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 3482 #endif /* TIM5 */ 3483 3484 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 3485 3486 #if defined(TIM7) 3487 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 3488 #endif /* TIM7 */ 3489 3490 #if defined(LCD) 3491 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) 3492 #endif /* LCD */ 3493 3494 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3495 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 3496 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3497 3498 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 3499 3500 #if defined(SPI2) 3501 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 3502 #endif /* SPI2 */ 3503 3504 #if defined(SPI3) 3505 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 3506 #endif /* SPI3 */ 3507 3508 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 3509 3510 #if defined(USART3) 3511 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 3512 #endif /* USART3 */ 3513 3514 #if defined(UART4) 3515 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 3516 #endif /* UART4 */ 3517 3518 #if defined(UART5) 3519 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 3520 #endif /* UART5 */ 3521 3522 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 3523 3524 #if defined(I2C2) 3525 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 3526 #endif /* I2C2 */ 3527 3528 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 3529 3530 #if defined(I2C4) 3531 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 3532 #endif /* I2C4 */ 3533 3534 #if defined(CRS) 3535 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 3536 #endif /* CRS */ 3537 3538 #if defined(CAN1) 3539 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) 3540 #endif /* CAN1 */ 3541 3542 #if defined(CAN2) 3543 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) 3544 #endif /* CAN2 */ 3545 3546 #if defined(USB) 3547 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 3548 #endif /* USB */ 3549 3550 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 3551 3552 #if defined(DAC1) 3553 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 3554 #endif /* DAC1 */ 3555 3556 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 3557 3558 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 3559 3560 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 3561 3562 #if defined(SWPMI1) 3563 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) 3564 #endif /* SWPMI1 */ 3565 3566 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 3567 3568 3569 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 3570 3571 #if defined(TIM3) 3572 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 3573 #endif /* TIM3 */ 3574 3575 #if defined(TIM4) 3576 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 3577 #endif /* TIM4 */ 3578 3579 #if defined(TIM5) 3580 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 3581 #endif /* TIM5 */ 3582 3583 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 3584 3585 #if defined(TIM7) 3586 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 3587 #endif /* TIM7 */ 3588 3589 #if defined(LCD) 3590 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) 3591 #endif /* LCD */ 3592 3593 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3594 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 3595 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3596 3597 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 3598 3599 #if defined(SPI2) 3600 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 3601 #endif /* SPI2 */ 3602 3603 #if defined(SPI3) 3604 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 3605 #endif /* SPI3 */ 3606 3607 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 3608 3609 #if defined(USART3) 3610 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 3611 #endif /* USART3 */ 3612 3613 #if defined(UART4) 3614 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 3615 #endif /* UART4 */ 3616 3617 #if defined(UART5) 3618 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 3619 #endif /* UART5 */ 3620 3621 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 3622 3623 #if defined(I2C2) 3624 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 3625 #endif /* I2C2 */ 3626 3627 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 3628 3629 #if defined(I2C4) 3630 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 3631 #endif /* I2C4 */ 3632 3633 #if defined(CRS) 3634 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 3635 #endif /* CRS */ 3636 3637 #if defined(CAN1) 3638 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) 3639 #endif /* CAN1 */ 3640 3641 #if defined(CAN2) 3642 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) 3643 #endif /* CAN2 */ 3644 3645 #if defined(USB) 3646 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 3647 #endif /* USB */ 3648 3649 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 3650 3651 #if defined(DAC1) 3652 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 3653 #endif /* DAC1 */ 3654 3655 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 3656 3657 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 3658 3659 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 3660 3661 #if defined(SWPMI1) 3662 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) 3663 #endif /* SWPMI1 */ 3664 3665 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 3666 3667 /** 3668 * @} 3669 */ 3670 3671 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 3672 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3673 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3674 * power consumption. 3675 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3676 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3677 * @{ 3678 */ 3679 3680 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 3681 3682 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3683 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) 3684 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3685 3686 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 3687 3688 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 3689 3690 #if defined(TIM8) 3691 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 3692 #endif /* TIM8 */ 3693 3694 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 3695 3696 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 3697 3698 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 3699 3700 #if defined(TIM17) 3701 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 3702 #endif /* TIM17 */ 3703 3704 #if defined(SAI1) 3705 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 3706 #endif /* SAI1 */ 3707 3708 #if defined(SAI2) 3709 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 3710 #endif /* SAI2 */ 3711 3712 #if defined(DFSDM1_Filter0) 3713 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 3714 #endif /* DFSDM1_Filter0 */ 3715 3716 #if defined(LTDC) 3717 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) 3718 #endif /* LTDC */ 3719 3720 #if defined(DSI) 3721 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) 3722 #endif /* DSI */ 3723 3724 3725 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 3726 3727 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3728 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) 3729 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3730 3731 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 3732 3733 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 3734 3735 #if defined(TIM8) 3736 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 3737 #endif /* TIM8 */ 3738 3739 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 3740 3741 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 3742 3743 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 3744 3745 #if defined(TIM17) 3746 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 3747 #endif /* TIM17 */ 3748 3749 #if defined(SAI1) 3750 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 3751 #endif /* SAI1 */ 3752 3753 #if defined(SAI2) 3754 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 3755 #endif /* SAI2 */ 3756 3757 #if defined(DFSDM1_Filter0) 3758 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 3759 #endif /* DFSDM1_Filter0 */ 3760 3761 #if defined(LTDC) 3762 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) 3763 #endif /* LTDC */ 3764 3765 #if defined(DSI) 3766 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) 3767 #endif /* DSI */ 3768 3769 /** 3770 * @} 3771 */ 3772 3773 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 3774 * @{ 3775 */ 3776 3777 /** @brief Macros to force or release the Backup domain reset. 3778 * @note This function resets the RTC peripheral (including the backup registers) 3779 * and the RTC clock source selection in RCC_CSR register. 3780 * @note The BKPSRAM is not affected by this reset. 3781 * @retval None 3782 */ 3783 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3784 3785 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3786 3787 /** 3788 * @} 3789 */ 3790 3791 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3792 * @{ 3793 */ 3794 3795 /** @brief Macros to enable or disable the RTC clock. 3796 * @note As the RTC is in the Backup domain and write access is denied to 3797 * this domain after reset, you have to enable write access using 3798 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3799 * (to be done once after reset). 3800 * @note These macros must be used after the RTC clock source was selected. 3801 * @retval None 3802 */ 3803 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3804 3805 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3806 3807 /** 3808 * @} 3809 */ 3810 3811 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3812 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3813 * It is used (enabled by hardware) as system clock source after startup 3814 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3815 * of the HSE used directly or indirectly as system clock (if the Clock 3816 * Security System CSS is enabled). 3817 * @note HSI can not be stopped if it is used as system clock source. In this case, 3818 * you have to select another source of the system clock then stop the HSI. 3819 * @note After enabling the HSI, the application software should wait on HSIRDY 3820 * flag to be set indicating that HSI clock is stable and can be used as 3821 * system clock source. 3822 * This parameter can be: ENABLE or DISABLE. 3823 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3824 * clock cycles. 3825 * @retval None 3826 */ 3827 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3828 3829 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3830 3831 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3832 * @note The calibration is used to compensate for the variations in voltage 3833 * and temperature that influence the frequency of the internal HSI RC. 3834 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 3835 * (default is RCC_HSICALIBRATION_DEFAULT). 3836 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). 3837 * @retval None 3838 */ 3839 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3840 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 3841 3842 /** 3843 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 3844 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 3845 * @note The enable of this function has not effect on the HSION bit. 3846 * This parameter can be: ENABLE or DISABLE. 3847 * @retval None 3848 */ 3849 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 3850 3851 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 3852 3853 /** 3854 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3855 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 3856 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3857 * speed because of the HSI startup time. 3858 * @note The enable of this function has not effect on the HSION bit. 3859 * This parameter can be: ENABLE or DISABLE. 3860 * @retval None 3861 */ 3862 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3863 3864 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3865 3866 /** 3867 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3868 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3869 * It is used (enabled by hardware) as system clock source after 3870 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3871 * of failure of the HSE used directly or indirectly as system clock 3872 * (if the Clock Security System CSS is enabled). 3873 * @note MSI can not be stopped if it is used as system clock source. 3874 * In this case, you have to select another source of the system 3875 * clock then stop the MSI. 3876 * @note After enabling the MSI, the application software should wait on 3877 * MSIRDY flag to be set indicating that MSI clock is stable and can 3878 * be used as system clock source. 3879 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3880 * clock cycles. 3881 * @retval None 3882 */ 3883 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 3884 3885 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 3886 3887 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 3888 * @note The calibration is used to compensate for the variations in voltage 3889 * and temperature that influence the frequency of the internal MSI RC. 3890 * Refer to the Application Note AN3300 for more details on how to 3891 * calibrate the MSI. 3892 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 3893 * (default is RCC_MSICALIBRATION_DEFAULT). 3894 * This parameter must be a number between 0 and 255. 3895 * @retval None 3896 */ 3897 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 3898 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 3899 3900 /** 3901 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 3902 * @note After restart from Reset , the MSI clock is around 4 MHz. 3903 * After stop the startup clock can be MSI (at any of its possible 3904 * frequencies, the one that was used before entering stop mode) or HSI. 3905 * After Standby its frequency can be selected between 4 possible values 3906 * (1, 2, 4 or 8 MHz). 3907 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 3908 * (MSIRDY=1). 3909 * @note The MSI clock range after reset can be modified on the fly. 3910 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 3911 * This parameter must be one of the following values: 3912 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 3913 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 3914 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 3915 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 3916 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 3917 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3918 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 3919 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 3920 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 3921 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 3922 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 3923 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 3924 * @retval None 3925 */ 3926 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 3927 do { \ 3928 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 3929 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 3930 } while(0) 3931 3932 /** 3933 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 3934 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 3935 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 3936 * This parameter must be one of the following values: 3937 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 3938 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3939 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 3940 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 3941 * @retval None 3942 */ 3943 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 3944 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 3945 3946 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 3947 * @retval MSI clock range. 3948 * This parameter must be one of the following values: 3949 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 3950 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 3951 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 3952 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 3953 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 3954 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3955 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 3956 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 3957 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 3958 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 3959 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 3960 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 3961 */ 3962 #define __HAL_RCC_GET_MSI_RANGE() \ 3963 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 3964 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 3965 (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) 3966 3967 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 3968 * @note After enabling the LSI, the application software should wait on 3969 * LSIRDY flag to be set indicating that LSI clock is stable and can 3970 * be used to clock the IWDG and/or the RTC. 3971 * @note LSI can not be disabled if the IWDG is running. 3972 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 3973 * clock cycles. 3974 * @retval None 3975 */ 3976 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 3977 3978 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 3979 3980 /** 3981 * @brief Macro to configure the External High Speed oscillator (HSE). 3982 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 3983 * supported by this macro. User should request a transition to HSE Off 3984 * first and then HSE On or HSE Bypass. 3985 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 3986 * software should wait on HSERDY flag to be set indicating that HSE clock 3987 * is stable and can be used to clock the PLL and/or system clock. 3988 * @note HSE state can not be changed if it is used directly or through the 3989 * PLL as system clock. In this case, you have to select another source 3990 * of the system clock then change the HSE state (ex. disable it). 3991 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 3992 * @note This function reset the CSSON bit, so if the clock security system(CSS) 3993 * was previously enabled you have to enable it again after calling this 3994 * function. 3995 * @param __STATE__ specifies the new state of the HSE. 3996 * This parameter can be one of the following values: 3997 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 3998 * 6 HSE oscillator clock cycles. 3999 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4000 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4001 * @retval None 4002 */ 4003 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4004 do { \ 4005 if((__STATE__) == RCC_HSE_ON) \ 4006 { \ 4007 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4008 } \ 4009 else if((__STATE__) == RCC_HSE_BYPASS) \ 4010 { \ 4011 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4012 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4013 } \ 4014 else \ 4015 { \ 4016 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4017 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4018 } \ 4019 } while(0) 4020 4021 /** 4022 * @brief Macro to configure the External Low Speed oscillator (LSE). 4023 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4024 * supported by this macro. User should request a transition to LSE Off 4025 * first and then LSE On or LSE Bypass. 4026 * @note As the LSE is in the Backup domain and write access is denied to 4027 * this domain after reset, you have to enable write access using 4028 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4029 * (to be done once after reset). 4030 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4031 * software should wait on LSERDY flag to be set indicating that LSE clock 4032 * is stable and can be used to clock the RTC. 4033 * @param __STATE__ specifies the new state of the LSE. 4034 * This parameter can be one of the following values: 4035 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4036 * 6 LSE oscillator clock cycles. 4037 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4038 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4039 * @retval None 4040 */ 4041 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4042 do { \ 4043 if((__STATE__) == RCC_LSE_ON) \ 4044 { \ 4045 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4046 } \ 4047 else if((__STATE__) == RCC_LSE_BYPASS) \ 4048 { \ 4049 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4050 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4051 } \ 4052 else \ 4053 { \ 4054 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4055 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4056 } \ 4057 } while(0) 4058 4059 #if defined(RCC_HSI48_SUPPORT) 4060 4061 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4062 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4063 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4064 * flag to be set indicating that HSI48 clock is stable. 4065 * This parameter can be: ENABLE or DISABLE. 4066 * @retval None 4067 */ 4068 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4069 4070 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4071 4072 #endif /* RCC_HSI48_SUPPORT */ 4073 4074 /** @brief Macros to configure the RTC clock (RTCCLK). 4075 * @note As the RTC clock configuration bits are in the Backup domain and write 4076 * access is denied to this domain after reset, you have to enable write 4077 * access using the Power Backup Access macro before to configure 4078 * the RTC clock source (to be done once after reset). 4079 * @note Once the RTC clock is configured it cannot be changed unless the 4080 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 4081 * a Power On Reset (POR). 4082 * 4083 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 4084 * This parameter can be one of the following values: 4085 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4086 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4087 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4088 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4089 * 4090 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4091 * work in STOP and STANDBY modes, and can be used as wakeup source. 4092 * However, when the HSE clock is used as RTC clock source, the RTC 4093 * cannot be used in STOP and STANDBY modes. 4094 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4095 * RTC clock source). 4096 * @retval None 4097 */ 4098 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 4099 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 4100 4101 4102 /** @brief Macro to get the RTC clock source. 4103 * @retval The returned value can be one of the following: 4104 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4105 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4106 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4107 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4108 */ 4109 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 4110 4111 /** @brief Macros to enable or disable the main PLL. 4112 * @note After enabling the main PLL, the application software should wait on 4113 * PLLRDY flag to be set indicating that PLL clock is stable and can 4114 * be used as system clock source. 4115 * @note The main PLL can not be disabled if it is used as system clock source 4116 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4117 * @retval None 4118 */ 4119 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 4120 4121 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 4122 4123 /** @brief Macro to configure the PLL clock source. 4124 * @note This function must be used only when the main PLL is disabled. 4125 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4126 * This parameter can be one of the following values: 4127 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4128 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4129 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4130 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4131 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4132 * @retval None 4133 * 4134 */ 4135 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 4136 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 4137 4138 /** @brief Macro to configure the PLL source division factor M. 4139 * @note This function must be used only when the main PLL is disabled. 4140 * @param __PLLM__ specifies the division factor for PLL VCO input clock 4141 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4142 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4143 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4144 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4145 * of 16 MHz to limit PLL jitter. 4146 * @retval None 4147 * 4148 */ 4149 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 4150 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 4151 4152 /** 4153 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 4154 * @note This function must be used only when the main PLL is disabled. 4155 * 4156 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4157 * This parameter can be one of the following values: 4158 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4159 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4160 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4161 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4162 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4163 * 4164 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 4165 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4166 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4167 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4168 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4169 * of 16 MHz to limit PLL jitter. 4170 * 4171 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 4172 * This parameter must be a number between 8 and 86. 4173 * @note You have to set the PLLN parameter correctly to ensure that the VCO 4174 * output frequency is between 64 and 344 MHz. 4175 * 4176 * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. 4177 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 4178 * else (2 to 31). 4179 * 4180 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 4181 * This parameter must be in the range (2, 4, 6 or 8). 4182 * @note If the USB OTG FS is used in your application, you have to set the 4183 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 4184 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 4185 * correctly. 4186 * @param __PLLR__ specifies the division factor for the main system clock. 4187 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 4188 * This parameter must be in the range (2, 4, 6 or 8). 4189 * @retval None 4190 */ 4191 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4192 4193 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4194 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 4195 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ 4196 (uint32_t)((__PLLP__) << 27U)) 4197 4198 #elif defined(RCC_PLLP_SUPPORT) 4199 4200 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4201 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 4202 (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ 4203 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) 4204 4205 #else 4206 4207 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ 4208 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 4209 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) 4210 4211 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 4212 4213 /** @brief Macro to get the oscillator used as PLL clock source. 4214 * @retval The oscillator used as PLL clock source. The returned value can be one 4215 * of the following: 4216 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 4217 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 4218 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 4219 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 4220 */ 4221 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 4222 4223 /** 4224 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4225 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 4226 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 4227 * be stopped if used as System Clock. 4228 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 4229 * This parameter can be one or a combination of the following values: 4230 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4231 * high-quality audio performance on SAI interface in case. 4232 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4233 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4234 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4235 * @retval None 4236 */ 4237 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4238 4239 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4240 4241 /** 4242 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4243 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 4244 * This parameter can be one of the following values: 4245 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4246 * high-quality audio performance on SAI interface in case. 4247 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4248 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4249 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4250 * @retval SET / RESET 4251 */ 4252 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4253 4254 /** 4255 * @brief Macro to configure the system clock source. 4256 * @param __SYSCLKSOURCE__ specifies the system clock source. 4257 * This parameter can be one of the following values: 4258 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 4259 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4260 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4261 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 4262 * @retval None 4263 */ 4264 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4265 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 4266 4267 /** @brief Macro to get the clock source used as system clock. 4268 * @retval The clock source used as system clock. The returned value can be one 4269 * of the following: 4270 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 4271 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4272 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4273 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 4274 */ 4275 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 4276 4277 /** 4278 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4279 * @note As the LSE is in the Backup domain and write access is denied to 4280 * this domain after reset, you have to enable write access using 4281 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4282 * (to be done once after reset). 4283 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 4284 * This parameter can be one of the following values: 4285 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4286 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4287 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4288 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4289 * @retval None 4290 */ 4291 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4292 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 4293 4294 /** 4295 * @brief Macro to configure the wake up from stop clock. 4296 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 4297 * This parameter can be one of the following values: 4298 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 4299 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4300 * @retval None 4301 */ 4302 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4303 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 4304 4305 4306 /** @brief Macro to configure the MCO clock. 4307 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4308 * This parameter can be one of the following values: 4309 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 4310 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 4311 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 4312 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 4313 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 4314 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 4315 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 4316 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 4317 @if STM32L443xx 4318 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4319 @endif 4320 @if STM32L4A6xx 4321 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4322 @endif 4323 * @param __MCODIV__ specifies the MCO clock prescaler. 4324 * This parameter can be one of the following values: 4325 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 4326 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 4327 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 4328 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 4329 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 4330 */ 4331 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4332 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4333 4334 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4335 * @brief macros to manage the specified RCC Flags and interrupts. 4336 * @{ 4337 */ 4338 4339 /** @brief Enable RCC interrupt(s). 4340 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 4341 * This parameter can be any combination of the following values: 4342 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4343 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4344 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4345 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4346 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4347 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4348 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4349 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4350 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4351 @if STM32L443xx 4352 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4353 @endif 4354 @if STM32L4A6xx 4355 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4356 @endif 4357 * @retval None 4358 */ 4359 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4360 4361 /** @brief Disable RCC interrupt(s). 4362 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 4363 * This parameter can be any combination of the following values: 4364 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4365 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4366 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4367 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4368 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4369 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4370 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4371 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4372 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4373 @if STM32L443xx 4374 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4375 @endif 4376 @if STM32L4A6xx 4377 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4378 @endif 4379 * @retval None 4380 */ 4381 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4382 4383 /** @brief Clear the RCC's interrupt pending bits. 4384 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4385 * This parameter can be any combination of the following values: 4386 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4387 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4388 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4389 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4390 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4391 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4392 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4393 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4394 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4395 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4396 @if STM32L443xx 4397 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4398 @endif 4399 @if STM32L4A6xx 4400 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4401 @endif 4402 * @retval None 4403 */ 4404 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4405 4406 /** @brief Check whether the RCC interrupt has occurred or not. 4407 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 4408 * This parameter can be one of the following values: 4409 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4410 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4411 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4412 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4413 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4414 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4415 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4416 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4417 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4418 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4419 @if STM32L443xx 4420 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4421 @endif 4422 @if STM32L4A6xx 4423 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4424 @endif 4425 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4426 */ 4427 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 4428 4429 /** @brief Set RMVF bit to clear the reset flags. 4430 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4431 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4432 * @retval None 4433 */ 4434 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 4435 4436 /** @brief Check whether the selected RCC flag is set or not. 4437 * @param __FLAG__ specifies the flag to check. 4438 * This parameter can be one of the following values: 4439 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 4440 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4441 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4442 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 4443 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 4444 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 4445 @if STM32L443xx 4446 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4447 @endif 4448 @if STM32L4A6xx 4449 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4450 @endif 4451 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4452 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4453 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4454 * @arg @ref RCC_FLAG_BORRST BOR reset 4455 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 4456 * @arg @ref RCC_FLAG_PINRST Pin reset 4457 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 4458 * @arg @ref RCC_FLAG_SFTRST Software reset 4459 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4460 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4461 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4462 * @retval The new state of __FLAG__ (TRUE or FALSE). 4463 */ 4464 #if defined(RCC_HSI48_SUPPORT) 4465 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4466 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 4467 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4468 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 4469 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4470 #else 4471 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4472 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4473 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 4474 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4475 #endif /* RCC_HSI48_SUPPORT */ 4476 4477 /** 4478 * @} 4479 */ 4480 4481 /** 4482 * @} 4483 */ 4484 4485 /* Private constants ---------------------------------------------------------*/ 4486 /** @defgroup RCC_Private_Constants RCC Private Constants 4487 * @{ 4488 */ 4489 /* Defines used for Flags */ 4490 #define CR_REG_INDEX 1U 4491 #define BDCR_REG_INDEX 2U 4492 #define CSR_REG_INDEX 3U 4493 #if defined(RCC_HSI48_SUPPORT) 4494 #define CRRCR_REG_INDEX 4U 4495 #endif /* RCC_HSI48_SUPPORT */ 4496 4497 #define RCC_FLAG_MASK 0x1FU 4498 /** 4499 * @} 4500 */ 4501 4502 /* Private macros ------------------------------------------------------------*/ 4503 /** @addtogroup RCC_Private_Macros 4504 * @{ 4505 */ 4506 4507 #if defined(RCC_HSI48_SUPPORT) 4508 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4509 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4510 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4511 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 4512 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 4513 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4514 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 4515 #else 4516 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4517 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4518 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4519 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 4520 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4521 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 4522 #endif /* RCC_HSI48_SUPPORT */ 4523 4524 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4525 ((__HSE__) == RCC_HSE_BYPASS)) 4526 4527 #if defined(RCC_BDCR_LSESYSDIS) 4528 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 4529 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) 4530 #else 4531 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4532 ((__LSE__) == RCC_LSE_BYPASS)) 4533 #endif /* RCC_BDCR_LSESYSDIS */ 4534 4535 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4536 4537 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 4538 4539 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4540 4541 #if defined(RCC_CSR_LSIPREDIV) 4542 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 4543 #endif /* RCC_CSR_LSIPREDIV */ 4544 4545 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 4546 4547 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 4548 4549 #if defined(RCC_HSI48_SUPPORT) 4550 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4551 #endif /* RCC_HSI48_SUPPORT */ 4552 4553 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 4554 ((__PLL__) == RCC_PLL_ON)) 4555 4556 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 4557 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 4558 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 4559 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 4560 4561 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 4562 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 4563 #else 4564 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 4565 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ 4566 4567 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 4568 4569 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4570 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 4571 #else 4572 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 4573 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 4574 4575 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4576 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4577 4578 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4579 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4580 4581 #if defined(RCC_PLLSAI1_SUPPORT) 4582 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 4583 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 4584 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 4585 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 4586 #endif /* RCC_PLLSAI1_SUPPORT */ 4587 4588 #if defined(RCC_PLLSAI2_SUPPORT) 4589 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 4590 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4591 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 4592 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 4593 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 4594 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4595 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ 4596 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ 4597 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) 4598 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 4599 #endif /* RCC_PLLSAI2_SUPPORT */ 4600 4601 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 4602 ((__RANGE__) == RCC_MSIRANGE_1) || \ 4603 ((__RANGE__) == RCC_MSIRANGE_2) || \ 4604 ((__RANGE__) == RCC_MSIRANGE_3) || \ 4605 ((__RANGE__) == RCC_MSIRANGE_4) || \ 4606 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4607 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4608 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4609 ((__RANGE__) == RCC_MSIRANGE_8) || \ 4610 ((__RANGE__) == RCC_MSIRANGE_9) || \ 4611 ((__RANGE__) == RCC_MSIRANGE_10) || \ 4612 ((__RANGE__) == RCC_MSIRANGE_11)) 4613 4614 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 4615 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4616 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4617 ((__RANGE__) == RCC_MSIRANGE_7)) 4618 4619 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 4620 4621 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 4622 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4623 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4624 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4625 4626 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 4627 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 4628 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 4629 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 4630 ((__HCLK__) == RCC_SYSCLK_DIV512)) 4631 4632 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 4633 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 4634 ((__PCLK__) == RCC_HCLK_DIV16)) 4635 4636 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 4637 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 4638 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 4639 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 4640 4641 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 4642 4643 #if defined(RCC_HSI48_SUPPORT) 4644 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4645 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4646 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4647 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4648 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4649 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4650 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4651 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 4652 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 4653 #else 4654 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4655 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4656 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4657 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4658 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4659 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4660 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4661 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 4662 #endif /* RCC_HSI48_SUPPORT */ 4663 4664 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 4665 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 4666 ((__DIV__) == RCC_MCODIV_16)) 4667 4668 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 4669 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 4670 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 4671 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 4672 4673 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 4674 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4675 /** 4676 * @} 4677 */ 4678 4679 /* Include RCC HAL Extended module */ 4680 #include "stm32l4xx_hal_rcc_ex.h" 4681 4682 /* Exported functions --------------------------------------------------------*/ 4683 /** @addtogroup RCC_Exported_Functions 4684 * @{ 4685 */ 4686 4687 4688 /** @addtogroup RCC_Exported_Functions_Group1 4689 * @{ 4690 */ 4691 4692 /* Initialization and de-initialization functions ******************************/ 4693 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4694 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4695 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 4696 4697 /** 4698 * @} 4699 */ 4700 4701 /** @addtogroup RCC_Exported_Functions_Group2 4702 * @{ 4703 */ 4704 4705 /* Peripheral Control functions ************************************************/ 4706 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4707 void HAL_RCC_EnableCSS(void); 4708 uint32_t HAL_RCC_GetSysClockFreq(void); 4709 uint32_t HAL_RCC_GetHCLKFreq(void); 4710 uint32_t HAL_RCC_GetPCLK1Freq(void); 4711 uint32_t HAL_RCC_GetPCLK2Freq(void); 4712 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4713 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4714 /* CSS NMI IRQ handler */ 4715 void HAL_RCC_NMI_IRQHandler(void); 4716 /* User Callbacks in non blocking mode (IT mode) */ 4717 void HAL_RCC_CSSCallback(void); 4718 4719 /** 4720 * @} 4721 */ 4722 4723 /** 4724 * @} 4725 */ 4726 4727 /** 4728 * @} 4729 */ 4730 4731 /** 4732 * @} 4733 */ 4734 4735 #ifdef __cplusplus 4736 } 4737 #endif 4738 4739 #endif /* __STM32L4xx_HAL_RCC_H */ 4740 4741 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4742
