1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_ADC_H 38 #define __STM32L4xx_HAL_ADC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /* Include low level driver */ 48 #include "stm32l4xx_ll_adc.h" 49 50 /** @addtogroup STM32L4xx_HAL_Driver 51 * @{ 52 */ 53 54 /** @addtogroup ADC 55 * @{ 56 */ 57 58 /* Exported types ------------------------------------------------------------*/ 59 /** @defgroup ADC_Exported_Types ADC Exported Types 60 * @{ 61 */ 62 63 /** 64 * @brief ADC group regular oversampling structure definition 65 */ 66 typedef struct 67 { 68 uint32_t Ratio; /*!< Configures the oversampling ratio. 69 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 70 71 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 72 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 73 74 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 75 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 76 77 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 78 The oversampling is either temporary stopped or reset upon an injected 79 sequence interruption. 80 If oversampling is enabled on both regular and injected groups, this parameter 81 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 82 (the oversampling buffer is zeroed during injection sequence). 83 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 84 85 }ADC_OversamplingTypeDef; 86 87 /** 88 * @brief Structure definition of ADC instance and ADC group regular. 89 * @note Parameters of this structure are shared within 2 scopes: 90 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 91 * ScanConvMode, EOCSelection, LowPowerAutoWait. 92 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 93 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 94 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 95 * ADC state can be either: 96 * - For all parameters: ADC disabled 97 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 98 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 99 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 100 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 101 * (which fulfills the ADC state condition) on the fly). 102 */ 103 typedef struct 104 { 105 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 106 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 107 Note: The ADC clock configuration is common to all ADC instances. 108 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 109 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 110 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 111 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 112 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 113 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 114 Note: This parameter can be modified only if all ADC instances are disabled. */ 115 116 uint32_t Resolution; /*!< Configure the ADC resolution. 117 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 118 119 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 120 Refer to reference manual for alignments formats versus resolutions. 121 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 122 123 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 124 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 125 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 126 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 127 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 128 Scan direction is upward: from rank 1 to rank 'n'. 129 This parameter can be a value of @ref ADC_Scan_mode */ 130 131 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 132 This parameter can be a value of @ref ADC_EOCSelection. */ 133 134 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 135 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 136 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 137 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 138 for low frequency applications. 139 This parameter can be set to ENABLE or DISABLE. 140 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag 141 to free the IRQ vector sequencer. 142 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 143 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 144 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 145 146 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 147 after the first ADC conversion start trigger occurred (software start or external trigger). 148 This parameter can be set to ENABLE or DISABLE. */ 149 150 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 151 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 152 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 153 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 154 continuous mode or external trigger that could launch a conversion). */ 155 156 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 157 (main sequence subdivided in successive parts). 158 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 159 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 160 This parameter can be set to ENABLE or DISABLE. */ 161 162 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 163 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 164 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 165 166 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 167 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 168 This parameter can be a value of @ref ADC_regular_external_trigger_source. 169 Caution: external trigger source is common to all ADC instances. */ 170 171 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 172 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 173 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 174 175 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 176 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 177 This parameter can be set to ENABLE or DISABLE. 178 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 179 180 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 181 This parameter applies to ADC group regular only. 182 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 183 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 184 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 185 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 186 Note: Error reporting with respect to the conversion mode: 187 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 188 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 189 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 190 191 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 192 This parameter can be set to ENABLE or DISABLE. 193 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 194 195 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 196 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 197 198 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 199 uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. 200 This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. 201 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 202 203 #endif 204 }ADC_InitTypeDef; 205 206 /** 207 * @brief Structure definition of ADC channel for regular group 208 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 209 * ADC state can be either: 210 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 211 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 212 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 213 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 214 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 215 * on the fly). 216 */ 217 typedef struct 218 { 219 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 220 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 221 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 222 223 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 224 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 225 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 226 the new channel setting (or parameter number of conversions adjusted) */ 227 228 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 229 Unit: ADC clock cycles 230 Conversion time is the addition of sampling time and processing time 231 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 232 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 233 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 234 It overwrites the last setting. 235 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 236 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 237 Refer to device datasheet for timings values. */ 238 239 uint32_t SingleDiff; /*!< Select single-ended or differential input. 240 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 241 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 242 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 243 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 244 It overwrites the last setting. 245 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 246 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 247 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 248 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 249 of another parameter update on the fly) */ 250 251 uint32_t OffsetNumber; /*!< Select the offset number 252 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 253 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 254 255 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 256 Offset value must be a positive number. 257 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 258 0x3FF, 0xFF or 0x3F respectively. 259 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 260 without continuous mode or external trigger that could launch a conversion). */ 261 262 }ADC_ChannelConfTypeDef; 263 264 /** 265 * @brief Structure definition of ADC analog watchdog 266 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 267 * ADC state can be either: 268 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 269 */ 270 typedef struct 271 { 272 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 273 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 274 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 275 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 276 277 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 278 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 279 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 280 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 281 282 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 283 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 284 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 285 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 286 287 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 288 This parameter can be set to ENABLE or DISABLE */ 289 290 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 291 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 292 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 293 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 294 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 295 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 296 impacted: the comparison of analog watchdog thresholds is done on 297 oversampling final computation (after ratio and shift application): 298 ADC data register bitfield [15:4] (12 most significant bits). */ 299 300 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 301 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 302 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 303 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 304 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 305 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 306 impacted: the comparison of analog watchdog thresholds is done on 307 oversampling final computation (after ratio and shift application): 308 ADC data register bitfield [15:4] (12 most significant bits). */ 309 }ADC_AnalogWDGConfTypeDef; 310 311 /** 312 * @brief ADC group injected contexts queue configuration 313 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 314 */ 315 typedef struct 316 { 317 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 318 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 319 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 320 321 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 322 }ADC_InjectionConfigTypeDef; 323 324 /** @defgroup ADC_States ADC States 325 * @{ 326 */ 327 328 /** 329 * @brief HAL ADC state machine: ADC states definition (bitfields) 330 * @note ADC state machine is managed by bitfields, state must be compared 331 * with bit by bit. 332 * For example: 333 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 334 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 335 */ 336 /* States of ADC global scope */ 337 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 338 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 339 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 340 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 341 342 /* States of ADC errors */ 343 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 344 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 345 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 346 347 /* States of ADC group regular */ 348 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 349 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 350 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 351 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 352 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ 353 354 /* States of ADC group injected */ 355 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 356 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 357 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 358 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 359 360 /* States of ADC analog watchdogs */ 361 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 362 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 363 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 364 365 /* States of ADC multi-mode */ 366 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 367 368 /** 369 * @} 370 */ 371 372 /** 373 * @brief ADC handle Structure definition 374 */ 375 typedef struct __ADC_HandleTypeDef 376 { 377 ADC_TypeDef *Instance; /*!< Register base address */ 378 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 379 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 380 HAL_LockTypeDef Lock; /*!< ADC locking object */ 381 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 382 __IO uint32_t ErrorCode; /*!< ADC Error code */ 383 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 384 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 385 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 386 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 387 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 388 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 389 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 390 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 391 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 392 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 393 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 394 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 395 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 396 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 397 }ADC_HandleTypeDef; 398 399 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 400 /** 401 * @brief HAL ADC Callback ID enumeration definition 402 */ 403 typedef enum 404 { 405 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 406 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 407 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 408 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 409 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 410 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 411 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 412 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 413 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 414 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 415 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 416 } HAL_ADC_CallbackIDTypeDef; 417 418 /** 419 * @brief HAL ADC Callback pointer definition 420 */ 421 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 422 423 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 424 425 /** 426 * @} 427 */ 428 429 430 /* Exported constants --------------------------------------------------------*/ 431 432 /** @defgroup ADC_Exported_Constants ADC Exported Constants 433 * @{ 434 */ 435 436 /** @defgroup ADC_Error_Code ADC Error Code 437 * @{ 438 */ 439 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 440 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, 441 enable/disable, erroneous state, ...) */ 442 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 443 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 444 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 445 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 446 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 447 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 453 * @{ 454 */ 455 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 456 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 457 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 458 459 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 460 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 461 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 462 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 463 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 464 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 465 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 466 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 467 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 468 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 469 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 470 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 476 * @{ 477 */ 478 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 479 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 480 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 481 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 487 * @{ 488 */ 489 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 490 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 491 /** 492 * @} 493 */ 494 495 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 496 * @{ 497 */ 498 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 499 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 505 * @{ 506 */ 507 /* ADC group regular trigger sources for all ADC instances */ 508 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 509 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 510 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 511 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 512 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 513 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 514 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 515 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 516 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 517 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 518 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 519 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 520 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 521 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 522 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 523 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 524 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 530 * @{ 531 */ 532 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 533 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 534 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 535 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 541 * @{ 542 */ 543 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 544 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 550 * @{ 551 */ 552 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 553 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 554 /** 555 * @} 556 */ 557 558 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 559 * @{ 560 */ 561 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 562 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 563 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 564 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 565 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 566 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 567 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 568 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 569 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 570 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 571 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 572 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 573 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 574 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 575 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 576 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 582 * @{ 583 */ 584 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 585 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 586 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 587 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 588 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 589 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 590 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 591 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 592 #if defined(ADC_SMPR1_SMPPLUS) 593 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 594 #endif 595 /** 596 * @} 597 */ 598 599 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 600 * @{ 601 */ 602 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 603 /* all ADC instances (refer to Reference Manual). */ 604 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 605 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 606 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 607 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 608 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 609 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 610 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 611 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 612 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 613 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 614 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 615 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 616 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 617 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 618 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 619 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 620 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 621 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 622 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 623 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 624 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 625 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ 626 #if defined(ADC1) && !defined(ADC2) 627 #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 628 #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 629 #elif defined(ADC2) 630 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 631 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 632 #if defined(ADC3) 633 #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 634 #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 635 #endif 636 #endif 637 /** 638 * @} 639 */ 640 641 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 642 * @{ 643 */ 644 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 645 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 646 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 652 * @{ 653 */ 654 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 655 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 656 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 657 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 658 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 659 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 660 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 661 /** 662 * @} 663 */ 664 665 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 666 * @{ 667 */ 668 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 669 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 670 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 671 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 672 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 673 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 674 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 675 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 676 /** 677 * @} 678 */ 679 680 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 681 * @{ 682 */ 683 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 684 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 685 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 686 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 687 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 688 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 689 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 690 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 691 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 697 * @{ 698 */ 699 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 700 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 706 * @{ 707 */ 708 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 709 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 710 /** 711 * @} 712 */ 713 714 715 /** @defgroup ADC_Event_type ADC Event type 716 * @{ 717 */ 718 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 719 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 720 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 721 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 722 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 723 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 724 /** 725 * @} 726 */ 727 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 728 729 /** @defgroup ADC_interrupts_definition ADC interrupts definition 730 * @{ 731 */ 732 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 733 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 734 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 735 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 736 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 737 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 738 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 739 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 740 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 741 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 742 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 743 744 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 745 746 /** 747 * @} 748 */ 749 750 /** @defgroup ADC_flags_definition ADC flags definition 751 * @{ 752 */ 753 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 754 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 755 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 756 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 757 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 758 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 759 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 760 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 761 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 762 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 763 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 764 765 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ 766 767 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 768 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 769 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ 770 771 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ 772 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 773 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 774 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ 775 776 /** 777 * @} 778 */ 779 780 /** 781 * @} 782 */ 783 784 /* Private macro -------------------------------------------------------------*/ 785 786 /** @defgroup ADC_Private_Macros ADC Private Macros 787 * @{ 788 */ 789 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 790 /* code of final user. */ 791 792 /** 793 * @brief Return resolution bits in CFGR register RES[1:0] field. 794 * @param __HANDLE__ ADC handle 795 * @retval Value of bitfield RES in CFGR register. 796 */ 797 #define ADC_GET_RESOLUTION(__HANDLE__) \ 798 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 799 800 /** 801 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 802 * @param __HANDLE__ ADC handle 803 * @retval None 804 */ 805 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 806 807 /** 808 * @brief Verification of ADC state: enabled or disabled. 809 * @param __HANDLE__ ADC handle 810 * @retval SET (ADC enabled) or RESET (ADC disabled) 811 */ 812 #define ADC_IS_ENABLE(__HANDLE__) \ 813 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 814 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 815 ) ? SET : RESET) 816 817 /** 818 * @brief Check if conversion is on going on regular group. 819 * @param __HANDLE__ ADC handle 820 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 821 */ 822 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 823 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 824 825 /** 826 * @brief Simultaneously clear and set specific bits of the handle State. 827 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 828 * the first parameter is the ADC handle State, the second parameter is the 829 * bit field to clear, the third and last parameter is the bit field to set. 830 * @retval None 831 */ 832 #define ADC_STATE_CLR_SET MODIFY_REG 833 834 /** 835 * @brief Verify that a given value is aligned with the ADC resolution range. 836 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 837 * @param __ADC_VALUE__ value checked against the resolution. 838 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 839 */ 840 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 841 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 842 843 /** 844 * @brief Verify the length of the scheduled regular conversions group. 845 * @param __LENGTH__ number of programmed conversions. 846 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 847 */ 848 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 849 850 851 /** 852 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 853 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 854 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 855 */ 856 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 857 858 859 /** 860 * @brief Verify the ADC clock setting. 861 * @param __ADC_CLOCK__ programmed ADC clock. 862 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 863 */ 864 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 865 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 866 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 867 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 868 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 869 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 870 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 871 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 872 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 873 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 874 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 875 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 876 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 877 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 878 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 879 880 /** 881 * @brief Verify the ADC resolution setting. 882 * @param __RESOLUTION__ programmed ADC resolution. 883 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 884 */ 885 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 886 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 887 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 888 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 889 890 /** 891 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 892 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 893 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 894 */ 895 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 896 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 897 898 /** 899 * @brief Verify the ADC converted data alignment. 900 * @param __ALIGN__ programmed ADC converted data alignment. 901 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 902 */ 903 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 904 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 905 906 /** 907 * @brief Verify the ADC scan mode. 908 * @param __SCAN_MODE__ programmed ADC scan mode. 909 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 910 */ 911 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 912 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 913 914 /** 915 * @brief Verify the ADC edge trigger setting for regular group. 916 * @param __EDGE__ programmed ADC edge trigger setting. 917 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 918 */ 919 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 920 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 921 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 922 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 923 924 /** 925 * @brief Verify the ADC regular conversions external trigger. 926 * @param __HANDLE__ ADC handle 927 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 928 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 929 */ 930 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 931 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 932 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 933 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 934 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 935 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 936 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 937 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 938 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 939 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 940 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 941 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 942 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 943 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 944 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 945 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 946 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 947 948 /** 949 * @brief Verify the ADC regular conversions check for converted data availability. 950 * @param __EOC_SELECTION__ converted data availability check. 951 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 952 */ 953 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 954 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 955 956 /** 957 * @brief Verify the ADC regular conversions overrun handling. 958 * @param __OVR__ ADC regular conversions overrun handling. 959 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 960 */ 961 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 962 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 963 964 /** 965 * @brief Verify the ADC conversions sampling time. 966 * @param __TIME__ ADC conversions sampling time. 967 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 968 */ 969 #if defined(ADC_SMPR1_SMPPLUS) 970 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 971 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 972 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 973 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 974 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 975 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 976 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 977 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 978 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 979 #else 980 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 981 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 982 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 983 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 984 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 985 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 986 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 987 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 988 #endif 989 990 /** 991 * @brief Verify the ADC regular channel setting. 992 * @param __CHANNEL__ programmed ADC regular channel. 993 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 994 */ 995 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 996 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 997 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 998 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 999 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1000 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1001 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1002 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1003 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1004 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1005 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1006 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1007 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1008 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1009 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1010 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1011 1012 /** 1013 * @} 1014 */ 1015 1016 1017 /* Private constants ---------------------------------------------------------*/ 1018 1019 /** @defgroup ADC_Private_Constants ADC Private Constants 1020 * @{ 1021 */ 1022 1023 /* Fixed timeout values for ADC conversion (including sampling time) */ 1024 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1025 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1026 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1027 /* Minimum ADC Clock frequency is 0.14 MHz */ 1028 /* Maximum conversion time is */ 1029 /* 653 / 0.14 MHz = 4.66 ms */ 1030 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1031 1032 /* Delay for temperature sensor stabilization time. */ 1033 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1034 /* Unit: us */ 1035 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1036 1037 /** 1038 * @} 1039 */ 1040 1041 /* Exported macro ------------------------------------------------------------*/ 1042 1043 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1044 * @{ 1045 */ 1046 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1047 /* final user. */ 1048 1049 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1050 * @{ 1051 */ 1052 1053 /** @brief Reset ADC handle state. 1054 * @param __HANDLE__ ADC handle 1055 * @retval None 1056 */ 1057 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1058 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1059 do{ \ 1060 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1061 (__HANDLE__)->MspInitCallback = NULL; \ 1062 (__HANDLE__)->MspDeInitCallback = NULL; \ 1063 } while(0) 1064 #else 1065 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1066 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1067 #endif 1068 1069 /** 1070 * @brief Enable ADC interrupt. 1071 * @param __HANDLE__ ADC handle 1072 * @param __INTERRUPT__ ADC Interrupt 1073 * This parameter can be one of the following values: 1074 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1075 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1076 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1077 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1078 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1079 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1080 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1081 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1082 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1083 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1084 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1085 * @retval None 1086 */ 1087 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1088 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1089 1090 /** 1091 * @brief Disable ADC interrupt. 1092 * @param __HANDLE__ ADC handle 1093 * @param __INTERRUPT__ ADC Interrupt 1094 * This parameter can be one of the following values: 1095 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1096 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1097 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1098 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1099 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1100 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1101 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1102 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1103 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1104 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1105 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1106 * @retval None 1107 */ 1108 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1109 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1110 1111 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1112 * @param __HANDLE__ ADC handle 1113 * @param __INTERRUPT__ ADC interrupt source to check 1114 * This parameter can be one of the following values: 1115 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1116 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1117 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1118 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1119 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1120 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1121 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1122 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1123 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1124 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1125 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1126 * @retval State of interruption (SET or RESET) 1127 */ 1128 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1129 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1130 1131 /** 1132 * @brief Check whether the specified ADC flag is set or not. 1133 * @param __HANDLE__ ADC handle 1134 * @param __FLAG__ ADC flag 1135 * This parameter can be one of the following values: 1136 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1137 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1138 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1139 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1140 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1141 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1142 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1143 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1144 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1145 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1146 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1147 * @retval State of flag (TRUE or FALSE). 1148 */ 1149 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1150 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1151 1152 /** 1153 * @brief Clear the specified ADC flag. 1154 * @param __HANDLE__ ADC handle 1155 * @param __FLAG__ ADC flag 1156 * This parameter can be one of the following values: 1157 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1158 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1159 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1160 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1161 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1162 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1163 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1164 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1165 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1166 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1167 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1168 * @retval None 1169 */ 1170 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1171 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1172 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1173 1174 /** 1175 * @} 1176 */ 1177 1178 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1179 * @{ 1180 */ 1181 1182 /** 1183 * @brief Helper macro to get ADC channel number in decimal format 1184 * from literals ADC_CHANNEL_x. 1185 * @note Example: 1186 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1187 * will return decimal number "4". 1188 * @note The input can be a value from functions where a channel 1189 * number is returned, either defined with number 1190 * or with bitfield (only one bit must be set). 1191 * @param __CHANNEL__ This parameter can be one of the following values: 1192 * @arg @ref ADC_CHANNEL_0 1193 * @arg @ref ADC_CHANNEL_1 (7) 1194 * @arg @ref ADC_CHANNEL_2 (7) 1195 * @arg @ref ADC_CHANNEL_3 (7) 1196 * @arg @ref ADC_CHANNEL_4 (7) 1197 * @arg @ref ADC_CHANNEL_5 (7) 1198 * @arg @ref ADC_CHANNEL_6 1199 * @arg @ref ADC_CHANNEL_7 1200 * @arg @ref ADC_CHANNEL_8 1201 * @arg @ref ADC_CHANNEL_9 1202 * @arg @ref ADC_CHANNEL_10 1203 * @arg @ref ADC_CHANNEL_11 1204 * @arg @ref ADC_CHANNEL_12 1205 * @arg @ref ADC_CHANNEL_13 1206 * @arg @ref ADC_CHANNEL_14 1207 * @arg @ref ADC_CHANNEL_15 1208 * @arg @ref ADC_CHANNEL_16 1209 * @arg @ref ADC_CHANNEL_17 1210 * @arg @ref ADC_CHANNEL_18 1211 * @arg @ref ADC_CHANNEL_VREFINT (1) 1212 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1213 * @arg @ref ADC_CHANNEL_VBAT (4) 1214 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1215 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1216 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1217 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1218 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1219 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1220 * 1221 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1222 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1223 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1224 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1225 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1226 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1227 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1228 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1229 * @retval Value between Min_Data=0 and Max_Data=18 1230 */ 1231 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1232 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1233 1234 /** 1235 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1236 * from number in decimal format. 1237 * @note Example: 1238 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1239 * will return a data equivalent to "ADC_CHANNEL_4". 1240 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1241 * @retval Returned value can be one of the following values: 1242 * @arg @ref ADC_CHANNEL_0 1243 * @arg @ref ADC_CHANNEL_1 (7) 1244 * @arg @ref ADC_CHANNEL_2 (7) 1245 * @arg @ref ADC_CHANNEL_3 (7) 1246 * @arg @ref ADC_CHANNEL_4 (7) 1247 * @arg @ref ADC_CHANNEL_5 (7) 1248 * @arg @ref ADC_CHANNEL_6 1249 * @arg @ref ADC_CHANNEL_7 1250 * @arg @ref ADC_CHANNEL_8 1251 * @arg @ref ADC_CHANNEL_9 1252 * @arg @ref ADC_CHANNEL_10 1253 * @arg @ref ADC_CHANNEL_11 1254 * @arg @ref ADC_CHANNEL_12 1255 * @arg @ref ADC_CHANNEL_13 1256 * @arg @ref ADC_CHANNEL_14 1257 * @arg @ref ADC_CHANNEL_15 1258 * @arg @ref ADC_CHANNEL_16 1259 * @arg @ref ADC_CHANNEL_17 1260 * @arg @ref ADC_CHANNEL_18 1261 * @arg @ref ADC_CHANNEL_VREFINT (1) 1262 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1263 * @arg @ref ADC_CHANNEL_VBAT (4) 1264 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1265 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1266 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1267 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1268 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1269 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1270 * 1271 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1272 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1273 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1274 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1275 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1276 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1277 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1278 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 1279 * (1, 2, 3, 4) For ADC channel read back from ADC register, 1280 * comparison with internal channel parameter to be done 1281 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1282 */ 1283 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1284 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1285 1286 /** 1287 * @brief Helper macro to determine whether the selected channel 1288 * corresponds to literal definitions of driver. 1289 * @note The different literal definitions of ADC channels are: 1290 * - ADC internal channel: 1291 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1292 * - ADC external channel (channel connected to a GPIO pin): 1293 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1294 * @note The channel parameter must be a value defined from literal 1295 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1296 * ADC_CHANNEL_TEMPSENSOR, ...), 1297 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1298 * must not be a value from functions where a channel number is 1299 * returned from ADC registers, 1300 * because internal and external channels share the same channel 1301 * number in ADC registers. The differentiation is made only with 1302 * parameters definitions of driver. 1303 * @param __CHANNEL__ This parameter can be one of the following values: 1304 * @arg @ref ADC_CHANNEL_0 1305 * @arg @ref ADC_CHANNEL_1 (7) 1306 * @arg @ref ADC_CHANNEL_2 (7) 1307 * @arg @ref ADC_CHANNEL_3 (7) 1308 * @arg @ref ADC_CHANNEL_4 (7) 1309 * @arg @ref ADC_CHANNEL_5 (7) 1310 * @arg @ref ADC_CHANNEL_6 1311 * @arg @ref ADC_CHANNEL_7 1312 * @arg @ref ADC_CHANNEL_8 1313 * @arg @ref ADC_CHANNEL_9 1314 * @arg @ref ADC_CHANNEL_10 1315 * @arg @ref ADC_CHANNEL_11 1316 * @arg @ref ADC_CHANNEL_12 1317 * @arg @ref ADC_CHANNEL_13 1318 * @arg @ref ADC_CHANNEL_14 1319 * @arg @ref ADC_CHANNEL_15 1320 * @arg @ref ADC_CHANNEL_16 1321 * @arg @ref ADC_CHANNEL_17 1322 * @arg @ref ADC_CHANNEL_18 1323 * @arg @ref ADC_CHANNEL_VREFINT (1) 1324 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1325 * @arg @ref ADC_CHANNEL_VBAT (4) 1326 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1327 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1328 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1329 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1330 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1331 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1332 * 1333 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1334 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1335 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1336 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1337 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1338 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1339 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1340 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1341 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1342 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1343 */ 1344 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1345 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1346 1347 /** 1348 * @brief Helper macro to convert a channel defined from parameter 1349 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1350 * ADC_CHANNEL_TEMPSENSOR, ...), 1351 * to its equivalent parameter definition of a ADC external channel 1352 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1353 * @note The channel parameter can be, additionally to a value 1354 * defined from parameter definition of a ADC internal channel 1355 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1356 * a value defined from parameter definition of 1357 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1358 * or a value from functions where a channel number is returned 1359 * from ADC registers. 1360 * @param __CHANNEL__ This parameter can be one of the following values: 1361 * @arg @ref ADC_CHANNEL_0 1362 * @arg @ref ADC_CHANNEL_1 (7) 1363 * @arg @ref ADC_CHANNEL_2 (7) 1364 * @arg @ref ADC_CHANNEL_3 (7) 1365 * @arg @ref ADC_CHANNEL_4 (7) 1366 * @arg @ref ADC_CHANNEL_5 (7) 1367 * @arg @ref ADC_CHANNEL_6 1368 * @arg @ref ADC_CHANNEL_7 1369 * @arg @ref ADC_CHANNEL_8 1370 * @arg @ref ADC_CHANNEL_9 1371 * @arg @ref ADC_CHANNEL_10 1372 * @arg @ref ADC_CHANNEL_11 1373 * @arg @ref ADC_CHANNEL_12 1374 * @arg @ref ADC_CHANNEL_13 1375 * @arg @ref ADC_CHANNEL_14 1376 * @arg @ref ADC_CHANNEL_15 1377 * @arg @ref ADC_CHANNEL_16 1378 * @arg @ref ADC_CHANNEL_17 1379 * @arg @ref ADC_CHANNEL_18 1380 * @arg @ref ADC_CHANNEL_VREFINT (1) 1381 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1382 * @arg @ref ADC_CHANNEL_VBAT (4) 1383 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1384 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1385 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1386 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1387 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1388 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1389 * 1390 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1391 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1392 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1393 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1394 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1395 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1396 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1397 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1398 * @retval Returned value can be one of the following values: 1399 * @arg @ref ADC_CHANNEL_0 1400 * @arg @ref ADC_CHANNEL_1 1401 * @arg @ref ADC_CHANNEL_2 1402 * @arg @ref ADC_CHANNEL_3 1403 * @arg @ref ADC_CHANNEL_4 1404 * @arg @ref ADC_CHANNEL_5 1405 * @arg @ref ADC_CHANNEL_6 1406 * @arg @ref ADC_CHANNEL_7 1407 * @arg @ref ADC_CHANNEL_8 1408 * @arg @ref ADC_CHANNEL_9 1409 * @arg @ref ADC_CHANNEL_10 1410 * @arg @ref ADC_CHANNEL_11 1411 * @arg @ref ADC_CHANNEL_12 1412 * @arg @ref ADC_CHANNEL_13 1413 * @arg @ref ADC_CHANNEL_14 1414 * @arg @ref ADC_CHANNEL_15 1415 * @arg @ref ADC_CHANNEL_16 1416 * @arg @ref ADC_CHANNEL_17 1417 * @arg @ref ADC_CHANNEL_18 1418 */ 1419 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1420 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1421 1422 /** 1423 * @brief Helper macro to determine whether the internal channel 1424 * selected is available on the ADC instance selected. 1425 * @note The channel parameter must be a value defined from parameter 1426 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1427 * ADC_CHANNEL_TEMPSENSOR, ...), 1428 * must not be a value defined from parameter definition of 1429 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1430 * or a value from functions where a channel number is 1431 * returned from ADC registers, 1432 * because internal and external channels share the same channel 1433 * number in ADC registers. The differentiation is made only with 1434 * parameters definitions of driver. 1435 * @param __ADC_INSTANCE__ ADC instance 1436 * @param __CHANNEL__ This parameter can be one of the following values: 1437 * @arg @ref ADC_CHANNEL_VREFINT (1) 1438 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1439 * @arg @ref ADC_CHANNEL_VBAT (4) 1440 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1441 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1442 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1443 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1444 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1445 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1446 * 1447 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1448 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1449 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1450 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1451 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1452 * (6) On STM32L4, parameter available on devices with several ADC instances. 1453 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1454 * Value "1" if the internal channel selected is available on the ADC instance selected. 1455 */ 1456 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1457 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1458 1459 #if defined(ADC_MULTIMODE_SUPPORT) 1460 /** 1461 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1462 * or ADC slave from raw value with both ADC conversion data concatenated. 1463 * @note This macro is intended to be used when multimode transfer by DMA 1464 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1465 * In this case the transferred data need to processed with this macro 1466 * to separate the conversion data of ADC master and ADC slave. 1467 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1468 * @arg @ref LL_ADC_MULTI_MASTER 1469 * @arg @ref LL_ADC_MULTI_SLAVE 1470 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1471 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1472 */ 1473 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1474 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1475 #endif 1476 1477 /** 1478 * @brief Helper macro to select the ADC common instance 1479 * to which is belonging the selected ADC instance. 1480 * @note ADC common register instance can be used for: 1481 * - Set parameters common to several ADC instances 1482 * - Multimode (for devices with several ADC instances) 1483 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1484 * @param __ADCx__ ADC instance 1485 * @retval ADC common register instance 1486 */ 1487 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1488 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1489 1490 /** 1491 * @brief Helper macro to check if all ADC instances sharing the same 1492 * ADC common instance are disabled. 1493 * @note This check is required by functions with setting conditioned to 1494 * ADC state: 1495 * All ADC instances of the ADC common group must be disabled. 1496 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1497 * @note On devices with only 1 ADC common instance, parameter of this macro 1498 * is useless and can be ignored (parameter kept for compatibility 1499 * with devices featuring several ADC common instances). 1500 * @param __ADCXY_COMMON__ ADC common instance 1501 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1502 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1503 * are disabled. 1504 * Value "1" if at least one ADC instance sharing the same ADC common instance 1505 * is enabled. 1506 */ 1507 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1508 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1509 1510 /** 1511 * @brief Helper macro to define the ADC conversion data full-scale digital 1512 * value corresponding to the selected ADC resolution. 1513 * @note ADC conversion data full-scale corresponds to voltage range 1514 * determined by analog voltage references Vref+ and Vref- 1515 * (refer to reference manual). 1516 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1517 * @arg @ref ADC_RESOLUTION_12B 1518 * @arg @ref ADC_RESOLUTION_10B 1519 * @arg @ref ADC_RESOLUTION_8B 1520 * @arg @ref ADC_RESOLUTION_6B 1521 * @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield) 1522 */ 1523 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1524 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1525 1526 /** 1527 * @brief Helper macro to convert the ADC conversion data from 1528 * a resolution to another resolution. 1529 * @param __DATA__ ADC conversion data to be converted 1530 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1531 * This parameter can be one of the following values: 1532 * @arg @ref ADC_RESOLUTION_12B 1533 * @arg @ref ADC_RESOLUTION_10B 1534 * @arg @ref ADC_RESOLUTION_8B 1535 * @arg @ref ADC_RESOLUTION_6B 1536 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1537 * This parameter can be one of the following values: 1538 * @arg @ref ADC_RESOLUTION_12B 1539 * @arg @ref ADC_RESOLUTION_10B 1540 * @arg @ref ADC_RESOLUTION_8B 1541 * @arg @ref ADC_RESOLUTION_6B 1542 * @retval ADC conversion data to the requested resolution 1543 */ 1544 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1545 __ADC_RESOLUTION_CURRENT__,\ 1546 __ADC_RESOLUTION_TARGET__) \ 1547 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1548 (__ADC_RESOLUTION_CURRENT__),\ 1549 (__ADC_RESOLUTION_TARGET__)) 1550 1551 /** 1552 * @brief Helper macro to calculate the voltage (unit: mVolt) 1553 * corresponding to a ADC conversion data (unit: digital value). 1554 * @note Analog reference voltage (Vref+) must be either known from 1555 * user board environment or can be calculated using ADC measurement 1556 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1557 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1558 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1559 * (unit: digital value). 1560 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1561 * @arg @ref ADC_RESOLUTION_12B 1562 * @arg @ref ADC_RESOLUTION_10B 1563 * @arg @ref ADC_RESOLUTION_8B 1564 * @arg @ref ADC_RESOLUTION_6B 1565 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1566 */ 1567 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1568 __ADC_DATA__,\ 1569 __ADC_RESOLUTION__) \ 1570 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1571 (__ADC_DATA__),\ 1572 (__ADC_RESOLUTION__)) 1573 1574 /** 1575 * @brief Helper macro to calculate analog reference voltage (Vref+) 1576 * (unit: mVolt) from ADC conversion data of internal voltage 1577 * reference VrefInt. 1578 * @note Computation is using VrefInt calibration value 1579 * stored in system memory for each device during production. 1580 * @note This voltage depends on user board environment: voltage level 1581 * connected to pin Vref+. 1582 * On devices with small package, the pin Vref+ is not present 1583 * and internally bonded to pin Vdda. 1584 * @note On this STM32 serie, calibration data of internal voltage reference 1585 * VrefInt corresponds to a resolution of 12 bits, 1586 * this is the recommended ADC resolution to convert voltage of 1587 * internal voltage reference VrefInt. 1588 * Otherwise, this macro performs the processing to scale 1589 * ADC conversion data to 12 bits. 1590 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1591 * of internal voltage reference VrefInt (unit: digital value). 1592 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1593 * @arg @ref ADC_RESOLUTION_12B 1594 * @arg @ref ADC_RESOLUTION_10B 1595 * @arg @ref ADC_RESOLUTION_8B 1596 * @arg @ref ADC_RESOLUTION_6B 1597 * @retval Analog reference voltage (unit: mV) 1598 */ 1599 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1600 __ADC_RESOLUTION__) \ 1601 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1602 (__ADC_RESOLUTION__)) 1603 1604 /** 1605 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1606 * from ADC conversion data of internal temperature sensor. 1607 * @note Computation is using temperature sensor calibration values 1608 * stored in system memory for each device during production. 1609 * @note Calculation formula: 1610 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1611 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1612 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1613 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1614 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1615 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1616 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1617 * TEMP_DEGC_CAL1 (calibrated in factory) 1618 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1619 * TEMP_DEGC_CAL2 (calibrated in factory) 1620 * Caution: Calculation relevancy under reserve that calibration 1621 * parameters are correct (address and data). 1622 * To calculate temperature using temperature sensor 1623 * datasheet typical values (generic values less, therefore 1624 * less accurate than calibrated values), 1625 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1626 * @note As calculation input, the analog reference voltage (Vref+) must be 1627 * defined as it impacts the ADC LSB equivalent voltage. 1628 * @note Analog reference voltage (Vref+) must be either known from 1629 * user board environment or can be calculated using ADC measurement 1630 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1631 * @note On this STM32 serie, calibration data of temperature sensor 1632 * corresponds to a resolution of 12 bits, 1633 * this is the recommended ADC resolution to convert voltage of 1634 * temperature sensor. 1635 * Otherwise, this macro performs the processing to scale 1636 * ADC conversion data to 12 bits. 1637 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1638 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1639 * temperature sensor (unit: digital value). 1640 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1641 * sensor voltage has been measured. 1642 * This parameter can be one of the following values: 1643 * @arg @ref ADC_RESOLUTION_12B 1644 * @arg @ref ADC_RESOLUTION_10B 1645 * @arg @ref ADC_RESOLUTION_8B 1646 * @arg @ref ADC_RESOLUTION_6B 1647 * @retval Temperature (unit: degree Celsius) 1648 */ 1649 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1650 __TEMPSENSOR_ADC_DATA__,\ 1651 __ADC_RESOLUTION__) \ 1652 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1653 (__TEMPSENSOR_ADC_DATA__),\ 1654 (__ADC_RESOLUTION__)) 1655 1656 /** 1657 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1658 * from ADC conversion data of internal temperature sensor. 1659 * @note Computation is using temperature sensor typical values 1660 * (refer to device datasheet). 1661 * @note Calculation formula: 1662 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1663 * / Avg_Slope + CALx_TEMP 1664 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1665 * (unit: digital value) 1666 * Avg_Slope = temperature sensor slope 1667 * (unit: uV/Degree Celsius) 1668 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1669 * temperature CALx_TEMP (unit: mV) 1670 * Caution: Calculation relevancy under reserve the temperature sensor 1671 * of the current device has characteristics in line with 1672 * datasheet typical values. 1673 * If temperature sensor calibration values are available on 1674 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1675 * temperature calculation will be more accurate using 1676 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1677 * @note As calculation input, the analog reference voltage (Vref+) must be 1678 * defined as it impacts the ADC LSB equivalent voltage. 1679 * @note Analog reference voltage (Vref+) must be either known from 1680 * user board environment or can be calculated using ADC measurement 1681 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1682 * @note ADC measurement data must correspond to a resolution of 12bits 1683 * (full scale digital value 4095). If not the case, the data must be 1684 * preliminarily rescaled to an equivalent resolution of 12 bits. 1685 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1686 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 1687 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1688 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1689 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1690 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1691 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1692 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1693 * This parameter can be one of the following values: 1694 * @arg @ref ADC_RESOLUTION_12B 1695 * @arg @ref ADC_RESOLUTION_10B 1696 * @arg @ref ADC_RESOLUTION_8B 1697 * @arg @ref ADC_RESOLUTION_6B 1698 * @retval Temperature (unit: degree Celsius) 1699 */ 1700 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1701 __TEMPSENSOR_TYP_CALX_V__,\ 1702 __TEMPSENSOR_CALX_TEMP__,\ 1703 __VREFANALOG_VOLTAGE__,\ 1704 __TEMPSENSOR_ADC_DATA__,\ 1705 __ADC_RESOLUTION__) \ 1706 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1707 (__TEMPSENSOR_TYP_CALX_V__),\ 1708 (__TEMPSENSOR_CALX_TEMP__),\ 1709 (__VREFANALOG_VOLTAGE__),\ 1710 (__TEMPSENSOR_ADC_DATA__),\ 1711 (__ADC_RESOLUTION__)) 1712 1713 /** 1714 * @} 1715 */ 1716 1717 /** 1718 * @} 1719 */ 1720 1721 /* Include ADC HAL Extended module */ 1722 #include "stm32l4xx_hal_adc_ex.h" 1723 1724 /* Exported functions --------------------------------------------------------*/ 1725 /** @addtogroup ADC_Exported_Functions 1726 * @{ 1727 */ 1728 1729 /** @addtogroup ADC_Exported_Functions_Group1 1730 * @brief Initialization and Configuration functions 1731 * @{ 1732 */ 1733 /* Initialization and de-initialization functions ****************************/ 1734 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 1735 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1736 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 1737 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 1738 1739 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1740 /* Callbacks Register/UnRegister functions ***********************************/ 1741 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 1742 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1743 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1744 /** 1745 * @} 1746 */ 1747 1748 /** @addtogroup ADC_Exported_Functions_Group2 1749 * @brief IO operation functions 1750 * @{ 1751 */ 1752 /* IO operation functions *****************************************************/ 1753 1754 /* Blocking mode: Polling */ 1755 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 1756 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 1757 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1758 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 1759 1760 /* Non-blocking mode: Interruption */ 1761 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 1762 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 1763 1764 /* Non-blocking mode: DMA */ 1765 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 1766 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 1767 1768 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1769 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 1770 1771 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1772 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 1773 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 1774 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 1775 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 1776 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1777 /** 1778 * @} 1779 */ 1780 1781 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1782 * @brief Peripheral Control functions 1783 * @{ 1784 */ 1785 /* Peripheral Control functions ***********************************************/ 1786 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 1787 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 1788 1789 /** 1790 * @} 1791 */ 1792 1793 /* Peripheral State functions *************************************************/ 1794 /** @addtogroup ADC_Exported_Functions_Group4 1795 * @{ 1796 */ 1797 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 1798 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1799 1800 /** 1801 * @} 1802 */ 1803 1804 /** 1805 * @} 1806 */ 1807 1808 /* Private functions -----------------------------------------------------------*/ 1809 /** @addtogroup ADC_Private_Functions ADC Private Functions 1810 * @{ 1811 */ 1812 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); 1813 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 1814 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); 1815 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1816 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1817 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1818 1819 /** 1820 * @} 1821 */ 1822 1823 /** 1824 * @} 1825 */ 1826 1827 /** 1828 * @} 1829 */ 1830 1831 #ifdef __cplusplus 1832 } 1833 #endif 1834 1835 1836 #endif /* __STM32L4xx_HAL_ADC_H */ 1837 1838 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1839
