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Searched refs:WRITE_REG (Results 1 – 25 of 130) sorted by relevance

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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_iwdg.h128 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
163 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
174 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
185 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
196 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
215 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); in LL_IWDG_SetPrescaler()
245 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); in LL_IWDG_SetReloadCounter()
268 WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); in LL_IWDG_SetWindow()
Dstm32l4xx_ll_dma.h418 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1055 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
1056 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
1061 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
1062 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
1085 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetMemoryAddress()
1107 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetPeriphAddress()
1169 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MSrcAddress()
1191 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MDstAddress()
1861 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]
Dstm32l4xx_ll_cortex.h509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
526 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
556 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
602 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
627 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
Dstm32l4xx_hal_iwdg.h132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l4xx_ll_gpio.h246 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
801 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
802 WRITE_REG(GPIOx->LCKR, PinMask); in LL_GPIO_LockPin()
803 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
905 WRITE_REG(GPIOx->ODR, PortValue); in LL_GPIO_WriteOutputPort()
974 WRITE_REG(GPIOx->BSRR, PinMask); in LL_GPIO_SetOutputPin()
1003 WRITE_REG(GPIOx->BRR, PinMask); in LL_GPIO_ResetOutputPin()
1032 WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); in LL_GPIO_TogglePin()
Dstm32l4xx_ll_crc.h137 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE_…
279 WRITE_REG(CRCx->INIT, InitCrc); in LL_CRC_SetInitialData()
309 WRITE_REG(CRCx->POL, PolynomCoef); in LL_CRC_SetPolynomialCoef()
343 WRITE_REG(CRCx->DR, InData); in LL_CRC_FeedData32()
447 WRITE_REG(CRCx->IDR, InData); in LL_CRC_Write_IDR()
Dstm32l4xx_ll_swpmi.h221 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL…
405 WRITE_REG(SWPMIx->BRR, BitRatePrescaler); in LL_SWPMI_SetBitRatePrescaler()
587 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF); in LL_SWPMI_ClearFlag_RXBF()
598 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF); in LL_SWPMI_ClearFlag_TXBE()
609 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF); in LL_SWPMI_ClearFlag_RXBER()
620 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF); in LL_SWPMI_ClearFlag_RXOVR()
631 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF); in LL_SWPMI_ClearFlag_TXUNR()
642 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF); in LL_SWPMI_ClearFlag_TC()
653 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF); in LL_SWPMI_ClearFlag_SR()
1091 WRITE_REG(SWPMIx->TDR, TxData); in LL_SWPMI_TransmitData32()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_iwdg.h128 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
163 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
174 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
185 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
196 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
215 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); in LL_IWDG_SetPrescaler()
245 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); in LL_IWDG_SetReloadCounter()
268 WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); in LL_IWDG_SetWindow()
Dstm32l0xx_hal_iwdg.h132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l0xx_ll_cortex.h460 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
477 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
507 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
553 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
555 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
557 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
578 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
Dstm32l0xx_ll_gpio.h230 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
688 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
689 WRITE_REG(GPIOx->LCKR, PinMask); in LL_GPIO_LockPin()
690 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
792 WRITE_REG(GPIOx->ODR, PortValue); in LL_GPIO_WriteOutputPort()
861 WRITE_REG(GPIOx->BSRR, PinMask); in LL_GPIO_SetOutputPin()
890 WRITE_REG(GPIOx->BRR, PinMask); in LL_GPIO_ResetOutputPin()
919 WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); in LL_GPIO_TogglePin()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_iwdg.h127 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
162 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); in LL_IWDG_Enable()
173 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); in LL_IWDG_ReloadCounter()
184 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); in LL_IWDG_EnableWriteAccess()
195 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); in LL_IWDG_DisableWriteAccess()
214 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); in LL_IWDG_SetPrescaler()
244 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); in LL_IWDG_SetReloadCounter()
Dstm32l1xx_ll_gpio.h234 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU…
727 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
728 WRITE_REG(GPIOx->LCKR, PinMask); in LL_GPIO_LockPin()
729 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); in LL_GPIO_LockPin()
831 WRITE_REG(GPIOx->ODR, PortValue); in LL_GPIO_WriteOutputPort()
900 WRITE_REG(GPIOx->BSRR, PinMask); in LL_GPIO_SetOutputPin()
931 WRITE_REG(GPIOx->BRR, PinMask); in LL_GPIO_ResetOutputPin()
933 WRITE_REG(GPIOx->BSRR, (PinMask << 16)); in LL_GPIO_ResetOutputPin()
963 WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); in LL_GPIO_TogglePin()
Dstm32l1xx_ll_cortex.h509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
526 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
556 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
602 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
627 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
Dstm32l1xx_hal_iwdg.h121 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
129 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_…
189 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
196 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_…
Dstm32l1xx_ll_crc.h81 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
116 WRITE_REG(CRCx->CR, CRC_CR_RESET); in LL_CRC_ResetCRCCalculationUnit()
136 WRITE_REG(CRCx->DR, InData); in LL_CRC_FeedData32()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_firewall.c160 WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress)); in HAL_FIREWALL_Config()
162 WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength)); in HAL_FIREWALL_Config()
165 WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress)); in HAL_FIREWALL_Config()
167 WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength)); in HAL_FIREWALL_Config()
170 WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress)); in HAL_FIREWALL_Config()
172 WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); in HAL_FIREWALL_Config()
Dstm32l0xx_hal_flash.c501 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); in HAL_FLASH_Unlock()
502 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); in HAL_FLASH_Unlock()
506 WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); in HAL_FLASH_Unlock()
507 WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); in HAL_FLASH_Unlock()
541 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); in HAL_FLASH_OB_Unlock()
542 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); in HAL_FLASH_OB_Unlock()
546 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); in HAL_FLASH_OB_Unlock()
547 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); in HAL_FLASH_OB_Unlock()
Dstm32l0xx_hal_wwdg.c191 WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); in HAL_WWDG_Init()
194 …WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)… in HAL_WWDG_Init()
249 WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); in HAL_WWDG_Refresh()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_firewall.c169 WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress)); in HAL_FIREWALL_Config()
171 WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength)); in HAL_FIREWALL_Config()
174 WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress)); in HAL_FIREWALL_Config()
176 WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength)); in HAL_FIREWALL_Config()
179 WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress)); in HAL_FIREWALL_Config()
181 WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); in HAL_FIREWALL_Config()
Dstm32l4xx_hal_usart_ex.c219 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_EnableSlaveMode()
261 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_DisableSlaveMode()
310 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_ConfigNSS()
350 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_EnableFifoMode()
391 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_DisableFifoMode()
440 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_SetTxFifoThreshold()
489 WRITE_REG(husart->Instance->CR1, tmpcr1); in HAL_USARTEx_SetRxFifoThreshold()
Dstm32l4xx_hal_qspi.c587 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
717 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
741 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
790 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
1118 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1268 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1546 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1648 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1651 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1654 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
[all …]
Dstm32l4xx_hal_dma2d.c781 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); in HAL_DMA2D_BlendingStart()
816 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); in HAL_DMA2D_BlendingStart_IT()
1017 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); in HAL_DMA2D_CLUTLoad()
1030 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); in HAL_DMA2D_CLUTLoad()
1071 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); in HAL_DMA2D_CLUTLoad_IT()
1087 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); in HAL_DMA2D_CLUTLoad_IT()
1679 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); in HAL_DMA2D_ConfigLayer()
1684 …WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|… in HAL_DMA2D_ConfigLayer()
1696 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); in HAL_DMA2D_ConfigLayer()
1701 …WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|… in HAL_DMA2D_ConfigLayer()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_flash.c492 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); in HAL_FLASH_Unlock()
493 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); in HAL_FLASH_Unlock()
497 WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); in HAL_FLASH_Unlock()
498 WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); in HAL_FLASH_Unlock()
532 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); in HAL_FLASH_OB_Unlock()
533 WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); in HAL_FLASH_OB_Unlock()
537 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); in HAL_FLASH_OB_Unlock()
538 WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); in HAL_FLASH_OB_Unlock()
Dstm32l1xx_hal_wwdg.c191 WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); in HAL_WWDG_Init()
194 …WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)… in HAL_WWDG_Init()
249 WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); in HAL_WWDG_Refresh()

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