1 /** 2 * \file 3 * 4 * \brief Component description for WDT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_WDT_COMPONENT_ 30 #define _SAML21_WDT_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR WDT */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_WDT Watchdog Timer */ 36 /*@{*/ 37 38 #define WDT_U2251 39 #define REV_WDT 0x101 40 41 /* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t :1; /*!< bit: 0 Reserved */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ 48 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 49 uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } WDT_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */ 56 #define WDT_CTRLA_RESETVALUE _U(0x00) /**< \brief (WDT_CTRLA reset_value) Control */ 57 58 #define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */ 59 #define WDT_CTRLA_ENABLE (_U(0x1) << WDT_CTRLA_ENABLE_Pos) 60 #define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */ 61 #define WDT_CTRLA_WEN (_U(0x1) << WDT_CTRLA_WEN_Pos) 62 #define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */ 63 #define WDT_CTRLA_ALWAYSON (_U(0x1) << WDT_CTRLA_ALWAYSON_Pos) 64 #define WDT_CTRLA_MASK _U(0x86) /**< \brief (WDT_CTRLA) MASK Register */ 65 66 /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ 71 uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ 72 } bit; /*!< Structure used for bit access */ 73 uint8_t reg; /*!< Type used for register access */ 74 } WDT_CONFIG_Type; 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ 78 #define WDT_CONFIG_RESETVALUE _U(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */ 79 80 #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ 81 #define WDT_CONFIG_PER_Msk (_U(0xF) << WDT_CONFIG_PER_Pos) 82 #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)) 83 #define WDT_CONFIG_PER_CYC8_Val _U(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */ 84 #define WDT_CONFIG_PER_CYC16_Val _U(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */ 85 #define WDT_CONFIG_PER_CYC32_Val _U(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */ 86 #define WDT_CONFIG_PER_CYC64_Val _U(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */ 87 #define WDT_CONFIG_PER_CYC128_Val _U(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */ 88 #define WDT_CONFIG_PER_CYC256_Val _U(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */ 89 #define WDT_CONFIG_PER_CYC512_Val _U(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */ 90 #define WDT_CONFIG_PER_CYC1024_Val _U(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */ 91 #define WDT_CONFIG_PER_CYC2048_Val _U(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */ 92 #define WDT_CONFIG_PER_CYC4096_Val _U(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */ 93 #define WDT_CONFIG_PER_CYC8192_Val _U(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */ 94 #define WDT_CONFIG_PER_CYC16384_Val _U(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */ 95 #define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos) 96 #define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos) 97 #define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos) 98 #define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos) 99 #define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos) 100 #define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos) 101 #define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos) 102 #define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos) 103 #define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos) 104 #define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos) 105 #define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos) 106 #define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos) 107 #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ 108 #define WDT_CONFIG_WINDOW_Msk (_U(0xF) << WDT_CONFIG_WINDOW_Pos) 109 #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)) 110 #define WDT_CONFIG_WINDOW_CYC8_Val _U(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */ 111 #define WDT_CONFIG_WINDOW_CYC16_Val _U(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */ 112 #define WDT_CONFIG_WINDOW_CYC32_Val _U(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */ 113 #define WDT_CONFIG_WINDOW_CYC64_Val _U(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */ 114 #define WDT_CONFIG_WINDOW_CYC128_Val _U(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */ 115 #define WDT_CONFIG_WINDOW_CYC256_Val _U(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */ 116 #define WDT_CONFIG_WINDOW_CYC512_Val _U(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */ 117 #define WDT_CONFIG_WINDOW_CYC1024_Val _U(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */ 118 #define WDT_CONFIG_WINDOW_CYC2048_Val _U(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */ 119 #define WDT_CONFIG_WINDOW_CYC4096_Val _U(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */ 120 #define WDT_CONFIG_WINDOW_CYC8192_Val _U(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */ 121 #define WDT_CONFIG_WINDOW_CYC16384_Val _U(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */ 122 #define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) 123 #define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) 124 #define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) 125 #define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) 126 #define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) 127 #define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) 128 #define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) 129 #define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) 130 #define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) 131 #define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) 132 #define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) 133 #define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) 134 #define WDT_CONFIG_MASK _U(0xFF) /**< \brief (WDT_CONFIG) MASK Register */ 135 136 /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef union { 139 struct { 140 uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ 141 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint8_t reg; /*!< Type used for register access */ 144 } WDT_EWCTRL_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ 148 #define WDT_EWCTRL_RESETVALUE _U(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ 149 150 #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ 151 #define WDT_EWCTRL_EWOFFSET_Msk (_U(0xF) << WDT_EWCTRL_EWOFFSET_Pos) 152 #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)) 153 #define WDT_EWCTRL_EWOFFSET_CYC8_Val _U(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */ 154 #define WDT_EWCTRL_EWOFFSET_CYC16_Val _U(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */ 155 #define WDT_EWCTRL_EWOFFSET_CYC32_Val _U(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */ 156 #define WDT_EWCTRL_EWOFFSET_CYC64_Val _U(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */ 157 #define WDT_EWCTRL_EWOFFSET_CYC128_Val _U(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */ 158 #define WDT_EWCTRL_EWOFFSET_CYC256_Val _U(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */ 159 #define WDT_EWCTRL_EWOFFSET_CYC512_Val _U(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */ 160 #define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */ 161 #define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */ 162 #define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */ 163 #define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */ 164 #define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */ 165 #define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) 166 #define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) 167 #define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) 168 #define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) 169 #define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) 170 #define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) 171 #define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) 172 #define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) 173 #define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) 174 #define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) 175 #define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) 176 #define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos) 177 #define WDT_EWCTRL_MASK _U(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */ 178 179 /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 184 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 185 } bit; /*!< Structure used for bit access */ 186 uint8_t reg; /*!< Type used for register access */ 187 } WDT_INTENCLR_Type; 188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 189 190 #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ 191 #define WDT_INTENCLR_RESETVALUE _U(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ 192 193 #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ 194 #define WDT_INTENCLR_EW (_U(0x1) << WDT_INTENCLR_EW_Pos) 195 #define WDT_INTENCLR_MASK _U(0x01) /**< \brief (WDT_INTENCLR) MASK Register */ 196 197 /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 202 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 203 } bit; /*!< Structure used for bit access */ 204 uint8_t reg; /*!< Type used for register access */ 205 } WDT_INTENSET_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ 209 #define WDT_INTENSET_RESETVALUE _U(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ 210 211 #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ 212 #define WDT_INTENSET_EW (_U(0x1) << WDT_INTENSET_EW_Pos) 213 #define WDT_INTENSET_MASK _U(0x01) /**< \brief (WDT_INTENSET) MASK Register */ 214 215 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ 216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 217 typedef union { // __I to avoid read-modify-write on write-to-clear register 218 struct { 219 __I uint8_t EW:1; /*!< bit: 0 Early Warning */ 220 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 221 } bit; /*!< Structure used for bit access */ 222 uint8_t reg; /*!< Type used for register access */ 223 } WDT_INTFLAG_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ 227 #define WDT_INTFLAG_RESETVALUE _U(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ 228 229 #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ 230 #define WDT_INTFLAG_EW (_U(0x1) << WDT_INTFLAG_EW_Pos) 231 #define WDT_INTFLAG_MASK _U(0x01) /**< \brief (WDT_INTFLAG) MASK Register */ 232 233 /* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */ 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 235 typedef union { 236 struct { 237 uint32_t :1; /*!< bit: 0 Reserved */ 238 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ 239 uint32_t WEN:1; /*!< bit: 2 Window Enable Busy */ 240 uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Busy */ 241 uint32_t CLEAR:1; /*!< bit: 4 Clear Busy */ 242 uint32_t :27; /*!< bit: 5..31 Reserved */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } WDT_SYNCBUSY_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */ 249 #define WDT_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */ 250 251 #define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Busy */ 252 #define WDT_SYNCBUSY_ENABLE (_U(0x1) << WDT_SYNCBUSY_ENABLE_Pos) 253 #define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Busy */ 254 #define WDT_SYNCBUSY_WEN (_U(0x1) << WDT_SYNCBUSY_WEN_Pos) 255 #define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Busy */ 256 #define WDT_SYNCBUSY_ALWAYSON (_U(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos) 257 #define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Busy */ 258 #define WDT_SYNCBUSY_CLEAR (_U(0x1) << WDT_SYNCBUSY_CLEAR_Pos) 259 #define WDT_SYNCBUSY_MASK _U(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */ 260 261 /* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ 266 } bit; /*!< Structure used for bit access */ 267 uint8_t reg; /*!< Type used for register access */ 268 } WDT_CLEAR_Type; 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 270 271 #define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */ 272 #define WDT_CLEAR_RESETVALUE _U(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */ 273 274 #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ 275 #define WDT_CLEAR_CLEAR_Msk (_U(0xFF) << WDT_CLEAR_CLEAR_Pos) 276 #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)) 277 #define WDT_CLEAR_CLEAR_KEY_Val _U(0xA5) /**< \brief (WDT_CLEAR) Clear Key */ 278 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) 279 #define WDT_CLEAR_MASK _U(0xFF) /**< \brief (WDT_CLEAR) MASK Register */ 280 281 /** \brief WDT hardware registers */ 282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 283 typedef struct { 284 __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */ 285 __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ 286 __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ 287 RoReg8 Reserved1[0x1]; 288 __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ 289 __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ 290 __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ 291 RoReg8 Reserved2[0x1]; 292 __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */ 293 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */ 294 } Wdt; 295 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 296 297 /*@}*/ 298 299 #endif /* _SAML21_WDT_COMPONENT_ */ 300
