1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_TIM_H 38 #define STM32L4xx_HAL_TIM_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup TIM 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup TIM_Exported_Types TIM Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief TIM Time base Configuration Structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 66 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 67 68 uint32_t CounterMode; /*!< Specifies the counter mode. 69 This parameter can be a value of @ref TIM_Counter_Mode */ 70 71 uint32_t Period; /*!< Specifies the period value to be loaded into the active 72 Auto-Reload Register at the next update event. 73 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 74 75 uint32_t ClockDivision; /*!< Specifies the clock division. 76 This parameter can be a value of @ref TIM_ClockDivision */ 77 78 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 79 reaches zero, an update event is generated and counting restarts 80 from the RCR value (N). 81 This means in PWM mode that (N+1) corresponds to: 82 - the number of PWM periods in edge-aligned mode 83 - the number of half PWM period in center-aligned mode 84 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 85 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 86 87 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 88 This parameter can be a value of @ref TIM_AutoReloadPreload */ 89 } TIM_Base_InitTypeDef; 90 91 /** 92 * @brief TIM Output Compare Configuration Structure definition 93 */ 94 typedef struct 95 { 96 uint32_t OCMode; /*!< Specifies the TIM mode. 97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 98 99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 101 102 uint32_t OCPolarity; /*!< Specifies the output polarity. 103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 104 105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 107 @note This parameter is valid only for timer instances supporting break feature. */ 108 109 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 110 This parameter can be a value of @ref TIM_Output_Fast_State 111 @note This parameter is valid only in PWM1 and PWM2 mode. */ 112 113 114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 116 @note This parameter is valid only for timer instances supporting break feature. */ 117 118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 120 @note This parameter is valid only for timer instances supporting break feature. */ 121 } TIM_OC_InitTypeDef; 122 123 /** 124 * @brief TIM One Pulse Mode Configuration Structure definition 125 */ 126 typedef struct 127 { 128 uint32_t OCMode; /*!< Specifies the TIM mode. 129 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 130 131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 132 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 133 134 uint32_t OCPolarity; /*!< Specifies the output polarity. 135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 136 137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 139 @note This parameter is valid only for timer instances supporting break feature. */ 140 141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 143 @note This parameter is valid only for timer instances supporting break feature. */ 144 145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 147 @note This parameter is valid only for timer instances supporting break feature. */ 148 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICFilter; /*!< Specifies the input capture filter. 156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 157 } TIM_OnePulse_InitTypeDef; 158 159 /** 160 * @brief TIM Input Capture Configuration Structure definition 161 */ 162 typedef struct 163 { 164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 166 167 uint32_t ICSelection; /*!< Specifies the input. 168 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 169 170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 172 173 uint32_t ICFilter; /*!< Specifies the input capture filter. 174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 175 } TIM_IC_InitTypeDef; 176 177 /** 178 * @brief TIM Encoder Configuration Structure definition 179 */ 180 typedef struct 181 { 182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Encoder_Mode */ 184 185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 187 188 uint32_t IC1Selection; /*!< Specifies the input. 189 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 190 191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 193 194 uint32_t IC1Filter; /*!< Specifies the input capture filter. 195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 196 197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 199 200 uint32_t IC2Selection; /*!< Specifies the input. 201 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 202 203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 205 206 uint32_t IC2Filter; /*!< Specifies the input capture filter. 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_Encoder_InitTypeDef; 209 210 /** 211 * @brief Clock Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClockSource; /*!< TIM clock sources 216 This parameter can be a value of @ref TIM_Clock_Source */ 217 uint32_t ClockPolarity; /*!< TIM clock polarity 218 This parameter can be a value of @ref TIM_Clock_Polarity */ 219 uint32_t ClockPrescaler; /*!< TIM clock prescaler 220 This parameter can be a value of @ref TIM_Clock_Prescaler */ 221 uint32_t ClockFilter; /*!< TIM clock filter 222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 223 } TIM_ClockConfigTypeDef; 224 225 /** 226 * @brief TIM Clear Input Configuration Handle Structure definition 227 */ 228 typedef struct 229 { 230 uint32_t ClearInputState; /*!< TIM clear Input state 231 This parameter can be ENABLE or DISABLE */ 232 uint32_t ClearInputSource; /*!< TIM clear Input sources 233 This parameter can be a value of @ref TIM_ClearInput_Source */ 234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 235 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ 238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 240 } TIM_ClearInputConfigTypeDef; 241 242 /** 243 * @brief TIM Master configuration Structure definition 244 * @note Advanced timers provide TRGO2 internal line which is redirected 245 * to the ADC 246 */ 247 typedef struct 248 { 249 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 250 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 251 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 252 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 253 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 254 This parameter can be a value of @ref TIM_Master_Slave_Mode */ 255 } TIM_MasterConfigTypeDef; 256 257 /** 258 * @brief TIM Slave configuration Structure definition 259 */ 260 typedef struct 261 { 262 uint32_t SlaveMode; /*!< Slave mode selection 263 This parameter can be a value of @ref TIM_Slave_Mode */ 264 uint32_t InputTrigger; /*!< Input Trigger source 265 This parameter can be a value of @ref TIM_Trigger_Selection */ 266 uint32_t TriggerPolarity; /*!< Input Trigger polarity 267 This parameter can be a value of @ref TIM_Trigger_Polarity */ 268 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 269 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 270 uint32_t TriggerFilter; /*!< Input trigger filter 271 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 272 273 } TIM_SlaveConfigTypeDef; 274 275 /** 276 * @brief TIM Break input(s) and Dead time configuration Structure definition 277 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 278 * filter and polarity. 279 */ 280 typedef struct 281 { 282 uint32_t OffStateRunMode; /*!< TIM off state in run mode 283 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 284 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 285 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 286 uint32_t LockLevel; /*!< TIM Lock level 287 This parameter can be a value of @ref TIM_Lock_level */ 288 uint32_t DeadTime; /*!< TIM dead Time 289 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 290 uint32_t BreakState; /*!< TIM Break State 291 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 292 uint32_t BreakPolarity; /*!< TIM Break input polarity 293 This parameter can be a value of @ref TIM_Break_Polarity */ 294 uint32_t BreakFilter; /*!< Specifies the break input filter. 295 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 296 uint32_t Break2State; /*!< TIM Break2 State 297 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 298 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 299 This parameter can be a value of @ref TIM_Break2_Polarity */ 300 uint32_t Break2Filter; /*!< TIM break2 input filter. 301 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 302 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 303 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 304 } TIM_BreakDeadTimeConfigTypeDef; 305 306 /** 307 * @brief HAL State structures definition 308 */ 309 typedef enum 310 { 311 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 312 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 313 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 314 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 315 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 316 } HAL_TIM_StateTypeDef; 317 318 /** 319 * @brief HAL Active channel structures definition 320 */ 321 typedef enum 322 { 323 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 324 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 325 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 326 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 327 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 328 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 329 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 330 } HAL_TIM_ActiveChannel; 331 332 /** 333 * @brief TIM Time Base Handle Structure definition 334 */ 335 typedef struct __TIM_HandleTypeDef 336 { 337 TIM_TypeDef *Instance; /*!< Register base address */ 338 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 339 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 340 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 341 This array is accessed by a @ref DMA_Handle_index */ 342 HAL_LockTypeDef Lock; /*!< Locking object */ 343 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 344 345 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 346 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 347 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 348 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 349 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 350 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 351 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 352 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 353 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 354 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 355 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 356 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 357 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 358 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 359 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 360 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 361 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 362 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 363 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 364 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 365 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 366 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 367 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 368 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 369 370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 371 } TIM_HandleTypeDef; 372 373 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 374 /** 375 * @brief HAL TIM Callback ID enumeration definition 376 */ 377 typedef enum 378 { 379 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */ 380 HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */ 381 HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */ 382 HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */ 383 HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */ 384 HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */ 385 HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */ 386 HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */ 387 HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */ 388 HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */ 389 HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */ 390 HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */ 391 HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Hall Sensor MspDeInit Callback ID */ 392 HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Hall Sensor MspDeInit Callback ID */ 393 394 HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */ 395 HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */ 396 HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */ 397 HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */ 398 HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */ 399 HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */ 400 HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */ 401 HAL_TIM_BREAK_CB_ID = 0x15U, /*!< TIM Break Callback ID */ 402 HAL_TIM_BREAK2_CB_ID = 0x16U /*!< TIM Break2 Callback ID */ 403 404 } HAL_TIM_CallbackIDTypeDef; 405 406 /** 407 * @brief HAL TIM Callback pointer definition 408 */ 409 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 410 411 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 412 413 /** 414 * @} 415 */ 416 /* End of exported types -----------------------------------------------------*/ 417 418 /* Exported constants --------------------------------------------------------*/ 419 /** @defgroup TIM_Exported_Constants TIM Exported Constants 420 * @{ 421 */ 422 423 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 424 * @{ 425 */ 426 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 427 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 428 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 429 /** 430 * @} 431 */ 432 433 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 434 * @{ 435 */ 436 #define TIM_DMABASE_CR1 0x00000000U 437 #define TIM_DMABASE_CR2 0x00000001U 438 #define TIM_DMABASE_SMCR 0x00000002U 439 #define TIM_DMABASE_DIER 0x00000003U 440 #define TIM_DMABASE_SR 0x00000004U 441 #define TIM_DMABASE_EGR 0x00000005U 442 #define TIM_DMABASE_CCMR1 0x00000006U 443 #define TIM_DMABASE_CCMR2 0x00000007U 444 #define TIM_DMABASE_CCER 0x00000008U 445 #define TIM_DMABASE_CNT 0x00000009U 446 #define TIM_DMABASE_PSC 0x0000000AU 447 #define TIM_DMABASE_ARR 0x0000000BU 448 #define TIM_DMABASE_RCR 0x0000000CU 449 #define TIM_DMABASE_CCR1 0x0000000DU 450 #define TIM_DMABASE_CCR2 0x0000000EU 451 #define TIM_DMABASE_CCR3 0x0000000FU 452 #define TIM_DMABASE_CCR4 0x00000010U 453 #define TIM_DMABASE_BDTR 0x00000011U 454 #define TIM_DMABASE_DCR 0x00000012U 455 #define TIM_DMABASE_DMAR 0x00000013U 456 #define TIM_DMABASE_OR1 0x00000014U 457 #define TIM_DMABASE_CCMR3 0x00000015U 458 #define TIM_DMABASE_CCR5 0x00000016U 459 #define TIM_DMABASE_CCR6 0x00000017U 460 #define TIM_DMABASE_OR2 0x00000018U 461 #define TIM_DMABASE_OR3 0x00000019U 462 /** 463 * @} 464 */ 465 466 /** @defgroup TIM_Event_Source TIM Event Source 467 * @{ 468 */ 469 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 470 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 471 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 472 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 473 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 474 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 475 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 476 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 477 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 478 /** 479 * @} 480 */ 481 482 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 483 * @{ 484 */ 485 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 486 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 487 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 493 * @{ 494 */ 495 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 496 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 497 /** 498 * @} 499 */ 500 501 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 502 * @{ 503 */ 504 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 505 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 506 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 507 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup TIM_Counter_Mode TIM Counter Mode 513 * @{ 514 */ 515 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 516 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 517 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 518 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 519 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup TIM_ClockDivision TIM Clock Division 525 * @{ 526 */ 527 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 528 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 529 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 530 /** 531 * @} 532 */ 533 534 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 535 * @{ 536 */ 537 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 538 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 539 /** 540 * @} 541 */ 542 543 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 544 * @{ 545 */ 546 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 547 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 548 549 /** 550 * @} 551 */ 552 553 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 554 * @{ 555 */ 556 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 557 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 563 * @{ 564 */ 565 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 566 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 572 * @{ 573 */ 574 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 575 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 581 * @{ 582 */ 583 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 584 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 590 * @{ 591 */ 592 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 593 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 599 * @{ 600 */ 601 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 602 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 608 * @{ 609 */ 610 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 611 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 612 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 613 /** 614 * @} 615 */ 616 617 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 618 * @{ 619 */ 620 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 621 connected to IC1, IC2, IC3 or IC4, respectively */ 622 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 623 connected to IC2, IC1, IC4 or IC3, respectively */ 624 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 625 /** 626 * @} 627 */ 628 629 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 630 * @{ 631 */ 632 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 633 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 634 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 635 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 641 * @{ 642 */ 643 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 644 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 650 * @{ 651 */ 652 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 653 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 654 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 660 * @{ 661 */ 662 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 663 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 664 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 665 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 666 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 667 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 668 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 669 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 670 /** 671 * @} 672 */ 673 674 /** @defgroup TIM_Commutation_Source TIM Commutation Source 675 * @{ 676 */ 677 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 678 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup TIM_DMA_sources TIM DMA Sources 684 * @{ 685 */ 686 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 687 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 688 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 689 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 690 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 691 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 692 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 693 /** 694 * @} 695 */ 696 697 /** @defgroup TIM_Flag_definition TIM Flag Definition 698 * @{ 699 */ 700 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 701 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 702 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 703 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 704 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 705 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 706 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 707 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 708 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 709 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 710 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 711 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 712 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 713 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 714 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 715 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 716 /** 717 * @} 718 */ 719 720 /** @defgroup TIM_Channel TIM Channel 721 * @{ 722 */ 723 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 724 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 725 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 726 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 727 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 728 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 729 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 730 /** 731 * @} 732 */ 733 734 /** @defgroup TIM_Clock_Source TIM Clock Source 735 * @{ 736 */ 737 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 738 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 739 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 740 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 741 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 742 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 743 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 744 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 745 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 746 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 747 /** 748 * @} 749 */ 750 751 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 752 * @{ 753 */ 754 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 755 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 756 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 757 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 758 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 759 /** 760 * @} 761 */ 762 763 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 764 * @{ 765 */ 766 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 767 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 768 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 769 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 770 /** 771 * @} 772 */ 773 774 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 775 * @{ 776 */ 777 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 778 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 779 /** 780 * @} 781 */ 782 783 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 784 * @{ 785 */ 786 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 787 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 788 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 789 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 790 /** 791 * @} 792 */ 793 794 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 795 * @{ 796 */ 797 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 798 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 799 /** 800 * @} 801 */ 802 803 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 804 * @{ 805 */ 806 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 807 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 808 /** 809 * @} 810 */ 811 /** @defgroup TIM_Lock_level TIM Lock level 812 * @{ 813 */ 814 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 815 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 816 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 817 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 823 * @{ 824 */ 825 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 826 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 827 /** 828 * @} 829 */ 830 831 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 832 * @{ 833 */ 834 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 835 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 836 /** 837 * @} 838 */ 839 840 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 841 * @{ 842 */ 843 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 844 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 845 /** 846 * @} 847 */ 848 849 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 850 * @{ 851 */ 852 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 853 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 854 /** 855 * @} 856 */ 857 858 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 859 * @{ 860 */ 861 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 862 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 863 (if none of the break inputs BRK and BRK2 is active) */ 864 /** 865 * @} 866 */ 867 868 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 869 * @{ 870 */ 871 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 872 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 873 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 874 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 880 * @{ 881 */ 882 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 883 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 884 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 885 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 886 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 887 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 888 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 889 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 890 /** 891 * @} 892 */ 893 894 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 895 * @{ 896 */ 897 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 898 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 899 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 900 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 901 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 902 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 903 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 904 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 905 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 906 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 907 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 908 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 909 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 910 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 911 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 912 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 913 /** 914 * @} 915 */ 916 917 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 918 * @{ 919 */ 920 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 921 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 922 /** 923 * @} 924 */ 925 926 /** @defgroup TIM_Slave_Mode TIM Slave mode 927 * @{ 928 */ 929 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 930 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 931 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 932 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 933 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 934 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 935 /** 936 * @} 937 */ 938 939 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 940 * @{ 941 */ 942 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 943 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 944 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 945 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 946 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 947 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 948 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 949 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 950 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 951 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 952 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 953 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 954 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 955 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 956 /** 957 * @} 958 */ 959 960 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 961 * @{ 962 */ 963 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 964 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 965 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 966 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 967 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 968 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 969 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 970 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 971 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 972 /** 973 * @} 974 */ 975 976 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 977 * @{ 978 */ 979 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 980 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 981 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 982 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 983 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 984 /** 985 * @} 986 */ 987 988 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 989 * @{ 990 */ 991 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 992 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 993 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 994 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 995 /** 996 * @} 997 */ 998 999 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1000 * @{ 1001 */ 1002 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1003 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1004 /** 1005 * @} 1006 */ 1007 1008 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1009 * @{ 1010 */ 1011 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1012 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1013 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1014 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1015 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1016 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1017 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1018 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1019 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1020 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1021 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1022 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1023 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1024 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1025 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1026 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1027 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1028 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1029 /** 1030 * @} 1031 */ 1032 1033 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1034 * @{ 1035 */ 1036 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1037 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1038 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1039 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1040 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1041 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1042 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1048 * @{ 1049 */ 1050 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1051 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1052 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1053 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1054 /** 1055 * @} 1056 */ 1057 1058 /** @defgroup TIM_Break_System TIM Break System 1059 * @{ 1060 */ 1061 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 1062 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1063 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 1064 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1065 /** 1066 * @} 1067 */ 1068 1069 /** 1070 * @} 1071 */ 1072 /* End of exported constants -------------------------------------------------*/ 1073 1074 /* Exported macros -----------------------------------------------------------*/ 1075 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1076 * @{ 1077 */ 1078 1079 /** @brief Reset TIM handle state. 1080 * @param __HANDLE__ TIM handle. 1081 * @retval None 1082 */ 1083 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1084 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1085 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1086 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1087 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1088 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1089 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1090 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1091 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1092 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1093 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1094 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1095 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1096 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1097 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1098 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1099 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1100 } while(0) 1101 #else 1102 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1103 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1104 1105 /** 1106 * @brief Enable the TIM peripheral. 1107 * @param __HANDLE__ TIM handle 1108 * @retval None 1109 */ 1110 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1111 1112 /** 1113 * @brief Enable the TIM main Output. 1114 * @param __HANDLE__ TIM handle 1115 * @retval None 1116 */ 1117 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1118 1119 /** 1120 * @brief Disable the TIM peripheral. 1121 * @param __HANDLE__ TIM handle 1122 * @retval None 1123 */ 1124 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1125 do { \ 1126 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1127 { \ 1128 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1129 { \ 1130 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1131 } \ 1132 } \ 1133 } while(0) 1134 1135 /** 1136 * @brief Disable the TIM main Output. 1137 * @param __HANDLE__ TIM handle 1138 * @retval None 1139 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1140 */ 1141 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1142 do { \ 1143 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1144 { \ 1145 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1146 { \ 1147 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1148 } \ 1149 } \ 1150 } while(0) 1151 1152 /** 1153 * @brief Disable the TIM main Output. 1154 * @param __HANDLE__ TIM handle 1155 * @retval None 1156 * @note The Main Output Enable of a timer instance is disabled unconditionally 1157 */ 1158 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1159 1160 /** @brief Enable the specified TIM interrupt. 1161 * @param __HANDLE__ specifies the TIM Handle. 1162 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1163 * This parameter can be one of the following values: 1164 * @arg TIM_IT_UPDATE: Update interrupt 1165 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1166 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1167 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1168 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1169 * @arg TIM_IT_COM: Commutation interrupt 1170 * @arg TIM_IT_TRIGGER: Trigger interrupt 1171 * @arg TIM_IT_BREAK: Break interrupt 1172 * @retval None 1173 */ 1174 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1175 1176 /** @brief Disable the specified TIM interrupt. 1177 * @param __HANDLE__ specifies the TIM Handle. 1178 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1179 * This parameter can be one of the following values: 1180 * @arg TIM_IT_UPDATE: Update interrupt 1181 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1182 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1183 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1184 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1185 * @arg TIM_IT_COM: Commutation interrupt 1186 * @arg TIM_IT_TRIGGER: Trigger interrupt 1187 * @arg TIM_IT_BREAK: Break interrupt 1188 * @retval None 1189 */ 1190 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1191 1192 /** @brief Enable the specified DMA request. 1193 * @param __HANDLE__ specifies the TIM Handle. 1194 * @param __DMA__ specifies the TIM DMA request to enable. 1195 * This parameter can be one of the following values: 1196 * @arg TIM_DMA_UPDATE: Update DMA request 1197 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1198 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1199 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1200 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1201 * @arg TIM_DMA_COM: Commutation DMA request 1202 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1203 * @retval None 1204 */ 1205 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1206 1207 /** @brief Disable the specified DMA request. 1208 * @param __HANDLE__ specifies the TIM Handle. 1209 * @param __DMA__ specifies the TIM DMA request to disable. 1210 * This parameter can be one of the following values: 1211 * @arg TIM_DMA_UPDATE: Update DMA request 1212 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1213 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1214 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1215 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1216 * @arg TIM_DMA_COM: Commutation DMA request 1217 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1218 * @retval None 1219 */ 1220 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1221 1222 /** @brief Check whether the specified TIM interrupt flag is set or not. 1223 * @param __HANDLE__ specifies the TIM Handle. 1224 * @param __FLAG__ specifies the TIM interrupt flag to check. 1225 * This parameter can be one of the following values: 1226 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1227 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1228 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1229 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1230 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1231 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1232 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1233 * @arg TIM_FLAG_COM: Commutation interrupt flag 1234 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1235 * @arg TIM_FLAG_BREAK: Break interrupt flag 1236 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1237 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1238 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1239 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1240 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1241 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1242 * @retval The new state of __FLAG__ (TRUE or FALSE). 1243 */ 1244 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1245 1246 /** @brief Clear the specified TIM interrupt flag. 1247 * @param __HANDLE__ specifies the TIM Handle. 1248 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1249 * This parameter can be one of the following values: 1250 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1251 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1252 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1253 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1254 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1255 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1256 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1257 * @arg TIM_FLAG_COM: Commutation interrupt flag 1258 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1259 * @arg TIM_FLAG_BREAK: Break interrupt flag 1260 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1261 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1262 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1263 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1264 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1265 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1266 * @retval The new state of __FLAG__ (TRUE or FALSE). 1267 */ 1268 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1269 1270 /** 1271 * @brief Check whether the specified TIM interrupt source is enabled or not. 1272 * @param __HANDLE__ TIM handle 1273 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1274 * This parameter can be one of the following values: 1275 * @arg TIM_IT_UPDATE: Update interrupt 1276 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1277 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1278 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1279 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1280 * @arg TIM_IT_COM: Commutation interrupt 1281 * @arg TIM_IT_TRIGGER: Trigger interrupt 1282 * @arg TIM_IT_BREAK: Break interrupt 1283 * @retval The state of TIM_IT (SET or RESET). 1284 */ 1285 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 1286 1287 /** @brief Clear the TIM interrupt pending bits. 1288 * @param __HANDLE__ TIM handle 1289 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1290 * This parameter can be one of the following values: 1291 * @arg TIM_IT_UPDATE: Update interrupt 1292 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1293 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1294 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1295 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1296 * @arg TIM_IT_COM: Commutation interrupt 1297 * @arg TIM_IT_TRIGGER: Trigger interrupt 1298 * @arg TIM_IT_BREAK: Break interrupt 1299 * @retval None 1300 */ 1301 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1302 1303 /** 1304 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1305 * @param __HANDLE__ TIM handle. 1306 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1307 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1308 mode. 1309 */ 1310 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1311 1312 /** 1313 * @brief Set the TIM Prescaler on runtime. 1314 * @param __HANDLE__ TIM handle. 1315 * @param __PRESC__ specifies the Prescaler new value. 1316 * @retval None 1317 */ 1318 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1319 1320 /** 1321 * @brief Set the TIM Counter Register value on runtime. 1322 * @param __HANDLE__ TIM handle. 1323 * @param __COUNTER__ specifies the Counter register new value. 1324 * @retval None 1325 */ 1326 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1327 1328 /** 1329 * @brief Get the TIM Counter Register value on runtime. 1330 * @param __HANDLE__ TIM handle. 1331 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1332 */ 1333 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ 1334 ((__HANDLE__)->Instance->CNT) 1335 1336 /** 1337 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1338 * @param __HANDLE__ TIM handle. 1339 * @param __AUTORELOAD__ specifies the Counter register new value. 1340 * @retval None 1341 */ 1342 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1343 do{ \ 1344 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1345 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1346 } while(0) 1347 1348 /** 1349 * @brief Get the TIM Autoreload Register value on runtime. 1350 * @param __HANDLE__ TIM handle. 1351 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1352 */ 1353 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ 1354 ((__HANDLE__)->Instance->ARR) 1355 1356 /** 1357 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1358 * @param __HANDLE__ TIM handle. 1359 * @param __CKD__ specifies the clock division value. 1360 * This parameter can be one of the following value: 1361 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1362 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1363 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1364 * @retval None 1365 */ 1366 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1367 do{ \ 1368 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1369 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1370 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1371 } while(0) 1372 1373 /** 1374 * @brief Get the TIM Clock Division value on runtime. 1375 * @param __HANDLE__ TIM handle. 1376 * @retval The clock division can be one of the following values: 1377 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1378 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1379 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1380 */ 1381 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ 1382 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1383 1384 /** 1385 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1386 * @param __HANDLE__ TIM handle. 1387 * @param __CHANNEL__ TIM Channels to be configured. 1388 * This parameter can be one of the following values: 1389 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1390 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1391 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1392 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1393 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1394 * This parameter can be one of the following values: 1395 * @arg TIM_ICPSC_DIV1: no prescaler 1396 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1397 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1398 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1399 * @retval None 1400 */ 1401 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1402 do{ \ 1403 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1404 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1405 } while(0) 1406 1407 /** 1408 * @brief Get the TIM Input Capture prescaler on runtime. 1409 * @param __HANDLE__ TIM handle. 1410 * @param __CHANNEL__ TIM Channels to be configured. 1411 * This parameter can be one of the following values: 1412 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1413 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1414 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1415 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1416 * @retval The input capture prescaler can be one of the following values: 1417 * @arg TIM_ICPSC_DIV1: no prescaler 1418 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1419 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1420 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1421 */ 1422 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1423 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1424 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1425 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1426 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1427 1428 /** 1429 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1430 * @param __HANDLE__ TIM handle. 1431 * @param __CHANNEL__ TIM Channels to be configured. 1432 * This parameter can be one of the following values: 1433 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1434 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1435 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1436 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1437 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1438 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1439 * @param __COMPARE__ specifies the Capture Compare register new value. 1440 * @retval None 1441 */ 1442 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1443 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1444 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1445 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1446 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1447 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1448 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1449 1450 /** 1451 * @brief Get the TIM Capture Compare Register value on runtime. 1452 * @param __HANDLE__ TIM handle. 1453 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1454 * This parameter can be one of the following values: 1455 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1456 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1457 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1458 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1459 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1460 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1461 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1462 */ 1463 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1464 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1465 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1466 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1467 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1468 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1469 ((__HANDLE__)->Instance->CCR6)) 1470 1471 /** 1472 * @brief Set the TIM Output compare preload. 1473 * @param __HANDLE__ TIM handle. 1474 * @param __CHANNEL__ TIM Channels to be configured. 1475 * This parameter can be one of the following values: 1476 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1477 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1478 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1479 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1480 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1481 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1482 * @retval None 1483 */ 1484 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1485 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1486 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1487 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1488 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1489 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1490 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1491 1492 /** 1493 * @brief Reset the TIM Output compare preload. 1494 * @param __HANDLE__ TIM handle. 1495 * @param __CHANNEL__ TIM Channels to be configured. 1496 * This parameter can be one of the following values: 1497 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1498 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1499 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1500 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1501 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1502 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1503 * @retval None 1504 */ 1505 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1506 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ 1507 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ 1508 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ 1509 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ 1510 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ 1511 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) 1512 1513 /** 1514 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1515 * @param __HANDLE__ TIM handle. 1516 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1517 * overflow/underflow generates an update interrupt or DMA request (if 1518 * enabled) 1519 * @retval None 1520 */ 1521 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 1522 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1523 1524 /** 1525 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1526 * @param __HANDLE__ TIM handle. 1527 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1528 * following events generate an update interrupt or DMA request (if 1529 * enabled): 1530 * _ Counter overflow underflow 1531 * _ Setting the UG bit 1532 * _ Update generation through the slave mode controller 1533 * @retval None 1534 */ 1535 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 1536 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1537 1538 /** 1539 * @brief Set the TIM Capture x input polarity on runtime. 1540 * @param __HANDLE__ TIM handle. 1541 * @param __CHANNEL__ TIM Channels to be configured. 1542 * This parameter can be one of the following values: 1543 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1544 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1545 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1546 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1547 * @param __POLARITY__ Polarity for TIx source 1548 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1549 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1550 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1551 * @retval None 1552 */ 1553 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1554 do{ \ 1555 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1556 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1557 }while(0) 1558 1559 /** 1560 * @} 1561 */ 1562 /* End of exported macros ----------------------------------------------------*/ 1563 1564 /* Private constants ---------------------------------------------------------*/ 1565 /** @defgroup TIM_Private_Constants TIM Private Constants 1566 * @{ 1567 */ 1568 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1569 channels have been disabled */ 1570 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1571 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1572 /** 1573 * @} 1574 */ 1575 /* End of private constants --------------------------------------------------*/ 1576 1577 /* Private macros ------------------------------------------------------------*/ 1578 /** @defgroup TIM_Private_Macros TIM Private Macros 1579 * @{ 1580 */ 1581 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1582 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ 1583 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1584 1585 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1586 ((__BASE__) == TIM_DMABASE_CR2) || \ 1587 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1588 ((__BASE__) == TIM_DMABASE_DIER) || \ 1589 ((__BASE__) == TIM_DMABASE_SR) || \ 1590 ((__BASE__) == TIM_DMABASE_EGR) || \ 1591 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1592 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1593 ((__BASE__) == TIM_DMABASE_CCER) || \ 1594 ((__BASE__) == TIM_DMABASE_CNT) || \ 1595 ((__BASE__) == TIM_DMABASE_PSC) || \ 1596 ((__BASE__) == TIM_DMABASE_ARR) || \ 1597 ((__BASE__) == TIM_DMABASE_RCR) || \ 1598 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1599 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1600 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1601 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1602 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1603 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1604 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1605 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1606 ((__BASE__) == TIM_DMABASE_OR1) || \ 1607 ((__BASE__) == TIM_DMABASE_OR2) || \ 1608 ((__BASE__) == TIM_DMABASE_OR3)) 1609 1610 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1611 1612 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1613 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1614 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1615 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1616 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1617 1618 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1619 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1620 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1621 1622 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1623 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1624 1625 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1626 ((__STATE__) == TIM_OCFAST_ENABLE)) 1627 1628 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1629 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1630 1631 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1632 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1633 1634 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1635 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1636 1637 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1638 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1639 1640 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1641 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1642 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1643 1644 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1645 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1646 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1647 1648 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1649 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1650 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1651 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1652 1653 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1654 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1655 1656 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1657 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1658 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1659 1660 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1661 1662 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1663 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1664 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1665 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1666 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1667 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1668 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1669 1670 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1671 ((__CHANNEL__) == TIM_CHANNEL_2)) 1672 1673 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1674 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1675 ((__CHANNEL__) == TIM_CHANNEL_3)) 1676 1677 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1678 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1679 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1680 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1681 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1682 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1683 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1684 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1685 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1686 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1687 1688 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1689 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1690 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1691 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1692 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1693 1694 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1695 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1696 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1697 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1698 1699 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1700 1701 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1702 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1703 1704 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1705 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1706 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1707 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1708 1709 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1710 1711 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1712 ((__STATE__) == TIM_OSSR_DISABLE)) 1713 1714 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1715 ((__STATE__) == TIM_OSSI_DISABLE)) 1716 1717 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1718 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1719 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1720 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1721 1722 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1723 1724 1725 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1726 ((__STATE__) == TIM_BREAK_DISABLE)) 1727 1728 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1729 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1730 1731 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1732 ((__STATE__) == TIM_BREAK2_DISABLE)) 1733 1734 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1735 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1736 1737 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1738 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1739 1740 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1741 1742 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1743 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1744 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1745 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1746 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1747 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1748 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1749 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1750 1751 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1752 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1753 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1754 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1755 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1756 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1757 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1758 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1759 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1760 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1761 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1762 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1763 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1764 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1765 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1766 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1767 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1768 1769 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1770 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1771 1772 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1773 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1774 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1775 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1776 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1777 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1778 1779 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1780 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1781 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1782 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1783 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1784 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1785 1786 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1787 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1788 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1789 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1790 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1791 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1792 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1793 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1794 1795 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1796 ((__SELECTION__) == TIM_TS_ITR1) || \ 1797 ((__SELECTION__) == TIM_TS_ITR2) || \ 1798 ((__SELECTION__) == TIM_TS_ITR3) || \ 1799 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1800 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1801 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1802 ((__SELECTION__) == TIM_TS_ETRF)) 1803 1804 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1805 ((__SELECTION__) == TIM_TS_ITR1) || \ 1806 ((__SELECTION__) == TIM_TS_ITR2) || \ 1807 ((__SELECTION__) == TIM_TS_ITR3) || \ 1808 ((__SELECTION__) == TIM_TS_NONE)) 1809 1810 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1811 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1812 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1813 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1814 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1815 1816 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1817 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1818 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1819 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1820 1821 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1822 1823 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1824 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1825 1826 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1827 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1828 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1829 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1830 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1831 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1832 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1833 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1834 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1835 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1836 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1837 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1838 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1839 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1840 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1841 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1842 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1843 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1844 1845 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1846 1847 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1848 1849 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 1850 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 1851 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ 1852 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 1853 1854 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__HANDLE__) ((((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_TRIGGER) || \ 1855 ((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ? 1UL : 0UL) 1856 1857 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1858 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1859 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1860 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1861 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1862 1863 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1864 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ 1865 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ 1866 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ 1867 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 1868 1869 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1870 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1871 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1872 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1873 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1874 1875 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1876 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1877 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1878 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1879 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1880 1881 /** 1882 * @} 1883 */ 1884 /* End of private macros -----------------------------------------------------*/ 1885 1886 /* Include TIM HAL Extended module */ 1887 #include "stm32l4xx_hal_tim_ex.h" 1888 1889 /* Exported functions --------------------------------------------------------*/ 1890 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1891 * @{ 1892 */ 1893 1894 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions 1895 * @brief Time Base functions 1896 * @{ 1897 */ 1898 /* Time Base functions ********************************************************/ 1899 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1900 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1901 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1902 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1903 /* Blocking mode: Polling */ 1904 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1905 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1906 /* Non-Blocking mode: Interrupt */ 1907 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1908 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1909 /* Non-Blocking mode: DMA */ 1910 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1911 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1912 /** 1913 * @} 1914 */ 1915 1916 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions 1917 * @brief Time Output Compare functions 1918 * @{ 1919 */ 1920 /* Timer Output Compare functions *********************************************/ 1921 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1922 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1923 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1924 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1925 /* Blocking mode: Polling */ 1926 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1927 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1928 /* Non-Blocking mode: Interrupt */ 1929 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1930 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1931 /* Non-Blocking mode: DMA */ 1932 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1933 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1934 /** 1935 * @} 1936 */ 1937 1938 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions 1939 * @brief Time PWM functions 1940 * @{ 1941 */ 1942 /* Timer PWM functions ********************************************************/ 1943 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 1944 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 1945 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 1946 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 1947 /* Blocking mode: Polling */ 1948 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1949 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1950 /* Non-Blocking mode: Interrupt */ 1951 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1952 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1953 /* Non-Blocking mode: DMA */ 1954 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1955 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1956 /** 1957 * @} 1958 */ 1959 1960 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions 1961 * @brief Time Input Capture functions 1962 * @{ 1963 */ 1964 /* Timer Input Capture functions **********************************************/ 1965 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 1966 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 1967 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 1968 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 1969 /* Blocking mode: Polling */ 1970 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1971 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1972 /* Non-Blocking mode: Interrupt */ 1973 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1974 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1975 /* Non-Blocking mode: DMA */ 1976 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1977 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1978 /** 1979 * @} 1980 */ 1981 1982 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions 1983 * @brief Time One Pulse functions 1984 * @{ 1985 */ 1986 /* Timer One Pulse functions **************************************************/ 1987 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 1988 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 1989 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 1990 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 1991 /* Blocking mode: Polling */ 1992 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1993 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1994 /* Non-Blocking mode: Interrupt */ 1995 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1996 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1997 /** 1998 * @} 1999 */ 2000 2001 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions 2002 * @brief Time Encoder functions 2003 * @{ 2004 */ 2005 /* Timer Encoder functions ****************************************************/ 2006 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2007 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2008 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2009 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2010 /* Blocking mode: Polling */ 2011 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2012 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2013 /* Non-Blocking mode: Interrupt */ 2014 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2015 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2016 /* Non-Blocking mode: DMA */ 2017 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 2018 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2019 /** 2020 * @} 2021 */ 2022 2023 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2024 * @brief IRQ handler management 2025 * @{ 2026 */ 2027 /* Interrupt Handler functions ***********************************************/ 2028 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2029 /** 2030 * @} 2031 */ 2032 2033 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 2034 * @brief Peripheral Control functions 2035 * @{ 2036 */ 2037 /* Control functions *********************************************************/ 2038 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2039 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2040 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2041 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); 2042 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); 2043 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2044 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2045 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2046 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2047 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 2048 uint32_t *BurstBuffer, uint32_t BurstLength); 2049 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2050 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 2051 uint32_t *BurstBuffer, uint32_t BurstLength); 2052 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2053 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2054 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2055 /** 2056 * @} 2057 */ 2058 2059 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2060 * @brief TIM Callbacks functions 2061 * @{ 2062 */ 2063 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2064 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2065 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2066 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2067 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2068 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2069 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2070 2071 /* Callbacks Register/UnRegister functions ***********************************/ 2072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2073 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); 2074 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2076 2077 /** 2078 * @} 2079 */ 2080 2081 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 2082 * @brief Peripheral State functions 2083 * @{ 2084 */ 2085 /* Peripheral State functions ************************************************/ 2086 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2087 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2088 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2089 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2090 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2091 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2092 /** 2093 * @} 2094 */ 2095 2096 /** 2097 * @} 2098 */ 2099 /* End of exported functions -------------------------------------------------*/ 2100 2101 /* Private functions----------------------------------------------------------*/ 2102 /** @defgroup TIM_Private_Functions TIM Private Functions 2103 * @{ 2104 */ 2105 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2106 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2107 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2108 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2109 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2110 2111 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2112 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2113 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2114 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2115 2116 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2117 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2118 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2119 2120 /** 2121 * @} 2122 */ 2123 /* End of private functions --------------------------------------------------*/ 2124 2125 /** 2126 * @} 2127 */ 2128 2129 /** 2130 * @} 2131 */ 2132 2133 #ifdef __cplusplus 2134 } 2135 #endif 2136 2137 #endif /* STM32L4xx_HAL_TIM_H */ 2138 2139 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2140
