Searched refs:TIM_DCR_DBL_Msk (Results 1 – 8 of 8) sorted by relevance
5810 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro5811 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
6172 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro6173 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
6331 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro6332 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
6068 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro6069 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
6892 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro6893 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
7194 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro7195 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…
14613 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ macro14614 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (D…