Searched refs:RCC_SYSCLK_DIV2 (Results 1 – 4 of 4) sorted by relevance
1101 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()1102 hpre = RCC_SYSCLK_DIV2; in HAL_RCC_ClockConfig()1107 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()1108 hpre = RCC_SYSCLK_DIV2; in HAL_RCC_ClockConfig()1151 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()1152 hpre = RCC_SYSCLK_DIV2; in HAL_RCC_ClockConfig()1182 if(hpre == RCC_SYSCLK_DIV2) in HAL_RCC_ClockConfig()
185 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) |…487 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ macro
213 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) |…477 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ macro
474 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ macro4626 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2)…