RCC_SYSCLK_DIV1 (reference) in projects: loramac-node-2.7.6

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Searched refs:RCC_SYSCLK_DIV1 (Results 1 – 14 of 14) sorted by relevance

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
D	stm32l4xx_hal_rcc.c	`1048 uint32_t hpre = RCC_SYSCLK_DIV1; in HAL_RCC_ClockConfig() 1098 if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) in HAL_RCC_ClockConfig() 1104 …CC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) in HAL_RCC_ClockConfig() 1184 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); in HAL_RCC_ClockConfig()`
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/
D	board.c	`239 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/SKiM881AXL/
D	board.c	`344 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL073/
D	board.c	`372 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL152/
D	board.c	`372 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/SKiM880B/
D	board.c	`372 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/SKiM980A/
D	board.c	`372 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL476/
D	board.c	`383 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NAMote72/
D	board.c	`444 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
D	stm32l0xx_hal_rcc.h	`185 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… 486 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided / macro`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
D	stm32l1xx_hal_rcc.c	`1294 if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) in RCC_SetFlashLatencyFromMSIRange()`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
D	stm32l0xx_hal_rcc.c	`1443 if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) in RCC_SetFlashLatencyFromMSIRange()`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
D	stm32l1xx_hal_rcc.h	`213 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|… 476 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided / macro`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
D	stm32l4xx_hal_rcc.h	`473 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided / macro 4626 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2)…`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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