Searched refs:RCC_ICSCR_MSITRIM_Pos (Results 1 – 12 of 12) sorted by relevance
106 #define RCC_ICSCR_MSITRIM_BITNUMBER RCC_ICSCR_MSITRIM_Pos
1496 …InitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; in HAL_RCC_GetOscConfig()
2672 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); in LL_RCC_MSI_SetCalibTrimming()2682 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); in LL_RCC_MSI_GetCalibTrimming()
3898 … MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
10608 #define RCC_ICSCR_MSITRIM_Pos (8U) macro10609 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */10611 #define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */10612 #define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */10613 #define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */10614 #define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */10615 #define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */10616 #define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */10617 #define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */10618 #define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
3496 #define RCC_ICSCR_MSITRIM_Pos (24U) macro3497 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
3755 #define RCC_ICSCR_MSITRIM_Pos (24U) macro3756 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
3897 #define RCC_ICSCR_MSITRIM_Pos (24U) macro3898 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
3789 #define RCC_ICSCR_MSITRIM_Pos (24U) macro3790 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
4182 #define RCC_ICSCR_MSITRIM_Pos (24U) macro4183 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
4252 #define RCC_ICSCR_MSITRIM_Pos (24U) macro4253 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
