RCC_HCLK_DIV1 (reference) in projects: loramac-node-2.7.6

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Searched refs:RCC_HCLK_DIV1 (Results 1 – 12 of 12) sorted by relevance

/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/
D	board.c	`240 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 241 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
D	stm32l4xx_hal_timebase_tim_template.c	`109 if (uwAPB1Prescaler == RCC_HCLK_DIV1) in HAL_InitTick()`
/loramac-node-2.7.6/src/boards/SKiM881AXL/
D	board.c	`345 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 346 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL073/
D	board.c	`373 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 374 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL152/
D	board.c	`373 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 374 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/SKiM880B/
D	board.c	`373 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 374 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/SKiM980A/
D	board.c	`373 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 374 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NucleoL476/
D	board.c	`384 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 385 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/NAMote72/
D	board.c	`445 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig() 446 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; in SystemClockConfig()`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
D	stm32l0xx_hal_rcc.h	`190 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \ 503 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided / macro`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
D	stm32l1xx_hal_rcc.h	`218 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \ 493 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided / macro`
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
D	stm32l4xx_hal_rcc.h	`489 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided / macro 4632 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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