Searched refs:RCC_CCIPR_CLK48SEL_1 (Results 1 – 4 of 4) sorted by relevance
614 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMM…635 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1653 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
550 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock…568 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock so…586 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock so…
1300 case RCC_CCIPR_CLK48SEL_1: /* PLL ? */ in HAL_RCCEx_GetPeriphCLKFreq()1392 case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */ in HAL_RCCEx_GetPeriphCLKFreq()
11584 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */ macro
